GB2524547A - Delta Sigma modulators - Google Patents

Abstract

To overcome what is referred to as the delayless path problem or the delay-free path problem in a time-interleaved delta-sigma modulator, a problematic coupling (30, figure 3) from the output of one quantizer 62 to the input circuit of another quantizer 64 is replaced by a coupling 31 from the output of the feedback DAC 102, and the error in the output of the quantizer 64 caused by coupling a signal based on a preceding quantizer 62 output, instead of the present quantizer 62 output, is corrected by a correction circuit 50, such as a differentiator, fed from the output of the quantizer 62 and coupled to a subtracter in the output circuit of the quantizer 64.  There may be more than two interleaved channels (figure 11). The technique is applicable to both discrete-time and continuous-time modulators (figure 7).

Description

Delta Sigma Modulators

Field of the invention

This invention relates to Delta Sigma modulators.

Background of the invention

Delta Sigma (DS, or AI) modulators have applications in Analogue to Digital Converters (ADC5), Digital to Analogue Converters (DACs), Class 0 amplifiers, etc. They have become very popular converters for high-resolution applications because of their oversarnpling and noise shaping nature. These characteristics make them more robust to their components' nonlinearities and nonidealities.

Indeed, by trading accuracy with speed, OS converters have become more attractive in the context of present CMOS technology evolution. The rapid growth of the portable communication device markets such as audio systems and consumer electronics has been led to an increasing demand for low power high resolution ADC designs over the last decade. The Z modulator can achieve a very high resolution analog-to-digital conversion for relatively low-bandwidth signals by using the oversarnpling and the noise shaping techniques.

It is known that Z modulators do not require precise analog components and sharp cut-off frequencies for their analog anti-aliasing filters.

The noise-shaping loop filter of a A>I modulator can be implemented as a single-loop Discrete-Time (DT) structure (Figure la) by using Switched-Capacitor (SC) circuits or as a single-loop Continuous-Time (CT) structure (Figure ib) through active-RC or Gm-C filters. In Figures la and ib, the reference numbers and symbols employed are applied throughout the remaining Figures to similar items. Referring to Figure la, a DT modulator accepts an input x(n), which is fed to a single loop comprising a feed-forward path 2 including a filter (accumulator) 4, which provides an output q(n) to an Analog to Digital Converter ADC 6 (quantizer), the output of the ADC providing the output y(n) of the modulator. The output of the modulator is fed in a feedback path 8, which includes a DAC 10, the output of the DAC being subtracted from the input signal in a combiner 12. Filter 4 is of a switched capacitor type, providing an accumulation function, and its transfer function is Hd(z), where z is the z-transform for discrete time systems. The transfer function for DAC 10 is HdoAc(z). Switched Capacitor filter circuits of OT structures are insensitive to clock jitter and the frequency response of the noise-shaping filter can be relatively accurately set by capacitor ratios.

For the purposes of the present specification, and in the context of AZ modulation, the terms Analog to Digital Converter, ADC, and quantizer are regarded as having the same meaning.

Referring to Figure ib, a CT AZ modulator has an input signal x(t) applied to a single loop comprising a Continuous Time (CT) integrator filter 3 in its feed forward path 2, providing an output q0(t) followed by a sample and hold switch 5, providing an output q(nT), which is fed to ADC (quantizer) 6. ADC 6 provides an output y(n), which is fed back in feedback path 8 via DAC 9 to combiner 12, where it is subtracted from the input signal x(t).

Filter 3 and DAC 9 in the feedback path 8 are represented by Laplacian transfer functions in the continuous time domain He(s), HCQAC(s). Filter 3 provides an integration function. CT AZ modulators benefit from operating at higher sampling frequencies in comparison to their DT counterparts. The errors of the sample-and-hold circuit are shaped by the loop filter and CT AZ modulators have an implicit anti-aliasing filter in their forward signal path.

However, CT AZ modulators suffer from several drawbacks: excess loop delay, jitter sensitivity and RC time constant variations.

The signal bandwidth that AZ modulators can deal with is narrow and is restricted by the OverSampling Ratio (OSR) and deployed technology. To increase the signal bandwidth the modulator can process, a variety of methods are used. The first one is to increase the order of the modulator. AZ modulators commonly have a filter (accumulator or integrator) in the forward signal path. Inserting a second integrator in the feed forward path converts the modulator from first order to second order. The order may be increased at will, but at a price, where the stability problem needs to be dealt with very carefully.

The second is to increase the number of bits for the ADC/quantizer, which makes the modulator more complicated. The third is to increase the sampling frequency. However, the most serious disadvantage of the third method is the technology limitations.

A fourth method to increase bandwidth is to employ the time-interleaving (TI) technique. This is a known technique which is based on a concept of an array or plurality of AZ modulators coupled in parallel to an input sampled signal, each modulator providing a respective processing channel. The input samples are distributed cyclically to the modulator channels, one sample to the first modulator channel, the next sample to the second, etc., In this way, for M interconnected parallel modulators that are working concurrently, the effective sampling rate and the OSR become M times the clock rate and the OSR of each modulator respectively. It should be noted that the required resolution can be acquired without increasing the order of the modulator or the number of bits for the quantizer. Much work has been carried out to simplify the design of TI AZ modulators, see M. Kozak, M. Karaman, and I. Kale, "Efficient Architectures for Time-Interleaved Oversampling Delta-Sigma Converters," IEEE Trans. Circuits Syst II, Analog Digit. Signal Process, vol. 47, no. 8, pp. 802-810, Aug.

2000; M. Kozak and I. Kale, "Novel Topologies for Time-Interleaved Delta-Sigma Modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 47, no. 7, pp. 639-654, Jul. 2000. It has been demonstrated that a TI structure with a number of processing channels or paths may be simplified so that the paths are integrated in a single AZ modulator structure. Each modulator path is routed to a respective ADC (quantizer), each ADC (quantizer) having a respective feedback path including a DAC. Hence for a Time Interleaved AZ modulator, which will have at least two paths, there are at least two quantizers working in parallel, each with a respective feedback path including a DAC. This is more fully explained below.

As explained more fully below, a problem arises with time interleaved AZ modulators, in that with two quantizers operating in parallel paths, there is necessarily a critical path, or so-called delayless path, between the output of one quantizer to the input of the other quantizer. Because of delays arising in paths of the modulators, this may prevent correct operation. One method to eliminate the delayless path problem is to move feedback to the digital domain instead of performing it in the analog domain: see K. S. Lee, Y. Choi and F. Maloberti," Domino Free 4-Path Time-Interleaved Second Order Sigma-Delta Modulator," IEEE ISCAS, pp. 473-476, 2004 which discloses a four path discrete time TI modulator where, instead of directly generating the 4-consecutive modulator outputs for time slot n, ni-i, n+2, ni-3 for each of four quantizers, only the n-th time slot modulator output and three predictive terms are generated by the quantizers. The disadvantage of this method is that the first quantizer requires more comparators than the number of the comparators in the second quantizer.

A second method is to use a sample-and-hold in front of the first quantizer and quantizing the signal when the output of the second DAC is ready [1. C. CaIdwell and D. A. Johns," A Time-Interleaved Continuous-Time A Modulator with 20-MHz Signal Bandwidth, IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1578-1588, July 2006.]. This method needs a complicated timing generator, a sample-and-hold and also faster integrators.

The problem therefore remains of overcoming the delayless path problem in a comparatively simple and efficient manner

Summary of the Invention

An embodiment of the invention is based on an error correction technique for overcoming the delayless path issue in time interleaved delta sigma modulators. An error is intentionally induced in the analog domain through the use of the output of one DAC in one feedback path from a first quantizer, which is applied to the input of a second quantizer associated with another feedback path and DAC. Although this output may relate to a previous time sample, the error thus created is then substantially corrected in the digital domain at the outputs of the quantizers, which may effectively eliminate the delayless feedback path.

Accordingly in one embodiment the invention provides a time interleaved delta sigma modulator including: a plurality of paths for respective time interleaved data channels, which paths comprise a respective feed forward path arrangement including at least one filter stage, a first one of said paths including a first quantizer means being connected to a first feedback path including a first digital to analog conversion means, a second one of said paths including a second quantizer means being connected to a second feedback path including a second digital to analog conversion means, and the output of the first digital to analog conversion means having a coupling to the input of the second quantizer means, and the output of the first quantizer being coupled to the output of the second quantizer means via a correction means for correcting errors introduced by said coupling.

The invention recognises that errors are created by delays causing timing misalignment, but because input signals vary relatively slowly in comparison to the clocking of the modulator, said coupling may provide the signal value from the first digital to analog conversion means (DAC) obtained at a previous clock interval. This will permit the second quantizer means to perform its quantisation operation. The error induced may then be corrected in the digital domain by means of an error correction circuit coupled between the outputs of the first and second quantizers means. Conveniently, said coupling is a direct coupling, not incorporating any delay or filtering circuits. Conveniently, the correction may be of the differencing form (1-z1), representing the difference between the present time sample, and the previous one.

The present invention is applicable to any number of channels/paths, two or more, in a time interleaved arrangement. Preferably the paths of the modulator share the same filter (integrator! accumulator) stages in the feed forward arrangement. The invention is applicable to modulators having one or more modulator loops, although the invention is particularly applicable to a single loop arrangement in a time interleaved arrangement. Further the invention is applicable to both DT and CT modulators, although it is particularly useful with CT modulators, as will become clear below.

Brief Description of the Drawings

Preferred embodiments of the invention will now be described by way of example with reference to the accompanying drawings, wherein: Figure 1 comprises Block diagrams of a) the known DT Single-Loop MI modulator and b) the known CT Single-Loop AZ modulator r; Figure 2 is a block diagram of a 3rn-order single-loop DT AZ modulator; Figure 3 is a block diagram of a 3rd-order Single-Loop Two-Path DTTI AZ modulator with shared accumulators; Figure 4 is a waveform diagram showing the outputs of Qi, Q2, DAC1 and DAC2 of Figure 3; Figure 5 is a block diagram of a first embodiment of the invention, comprising a 3rd-order Single-Loop Two-Path DTTI AZ modulator with shared accumulators and digital correction network; Figure 6 are block diagrams of a) a Single-Loop Two-Path DTTI AZ modulator and b) a Single-Loop Two-Path CTTI AZ modulator; Figure 7 is a block diagram of a second embodiment of the invention comprising a 3rd-order Single-Loop Two-Path CTTI AZ modulator with shared integrators; Figure 8 shows the signal transfer functions of the 3rd-order Single-Loop Two-Path Dill and the 3rd-order Single-Loop Two-Path CTTI AZ modulators.

of Figures 5 and 7; Figure 9 shows noise transfer functions of the 3rd-order Single-Loop Two-Path CTTI AZ modulator of Figure 7 and a 3rd-order Single-Loop Two-Path DTTI AZ modulator; Figure 10 is a block diagram of a third embodiment of the invention comprising a 4th-order Single-Loop Two-Path DTTI AZ modulator with shared accumulators; and Figure 11 is a block diagram of a fourth embodiment of the invention comprising a 3rd-order Single-Loop Four-Path DTTI AZ modulator with shared accumulators.

Description of the Embodiments

CT AZ modulators benefit from operating at higher sampling frequencies in comparison to their DT counterparts. The errors of the sample-and-hold circuit are shaped by the loop filter and the CT AZ modulators have an implicit anti-aliasing filter in their forward signal path. However, CT AZ modulators suffer from several drawbacks: excess loop delay, jitter sensitivity and RC time constant variations.

One way to convert a DT AZ modulator to an equivalent CT AZ modulator is the known impulse-invariant transformation [M. Ortmanns and F. Gerfers, Continuous-Time Sigma-Delta A/fl Conversion. Berlin: Springer, 2006].

Another is the use of the modified z-transform. The impulse-invariant transformation is employed below. A DT AZ modulator and a CT AZ modulator are shown in Figure 1, and are said to be equivalent when their quantizer inputs are equal at the sampling instants.

q(n) = (1) The procedure for the design of a AZ modulator is based on choosing: the order and architecture of the AZ modulator, the OverSampling Ratio (OSR) S and the number of bits for the quantizer. By using the time-interleaving technique and M interconnected parallel modulators that are working concurrently, the effective sampling rate and the OSR become M times the clock rate and the OSR of each modulator respectively; it should be noted with this technique the required resolution can be acquired without increasing the order of the modulator or the number of bits for the quantizer and also without utilizing a state of the art technology.

A 31dorder single loop two path Discrete-Time Time-Interleaved (DTTI) AZ modulator (below, Figure 3) may be derived from the time domain node equations of a conventional DT AZ modulator, which is shown in Figure 2. In Figure 2, a first accumulator filter 4a obtains an input from combiner 12a, and has a transfer function az1(1-z11, i.e.an accumulation function, with scaling a.

Second and third accumulators 4b and 4c with respective transfer functions bz 1(1-zj cz1(1-zj1 obtain inputs from respective combiners 12b, 12c. In this Figure, single step quantizer 6 represents the ADC. It is assumed that the DAC 10 in the feedback loop 8 is ideal (hbn.c(1). The time domain equations of the modulator are written for two consecutive time slots as (2n)th and (2n+1)th as follows: i'1(2n) = -1) -ay(2n-1) + v(2n -1) (2. a) v,(2n) = bv1(2n -1) -by(2n-1)± v,(2n-1) (2. b) v3 (2,,) = cv2(2n -1)-cy(2n-1) + V3 (2n -(2 c) = Q1v3(2n)I (2.d) and v1( 2n+I) = a. 2n)-ay(2n)4-vj(2n) (3.a) T'( 2n+1)= b"1 (2n)-by(2nh-v212n) (3. b) T';( 2,i ±1) = cv2( 2,,)-çv( 2,1)4-v( 2,,) (3. c) v(2u±]) = Q[v(2n +1)] (3.d) where [-] represents the quantization function. The input is distributed between two channels through an input multiplexer which operates at twice the clock frequency of each channel. The input "is relabelled as follows: r1( n)=.t( 2n) , x.,( ;z)= x( 2;i-1) (4) Similarly, the other nodes of the modulator are relabelled: (5a) vn1( n)= v2( 2n) , 22(") v,( 2r, 1) (5.b) T'i(fl) =i'(2n) i,(n.) = v( 2n -I) (5.c) 15)i"= )(2fl) , )2")= )2n (5.d) By sharing only one set of accumulators, the input demultiplexer is removed and the input "-is shared between channels. Hence equation (4) results in (6) as follows: (6) Equation sets (7) and (8) are derived by substituting equation set (5) and equation (6) into equation sets (2) and (3) respectively as follows: V jj ii) = (tAt/I)-(/)1⁄2( )± v12( " (7. a) v-1( ,,) = bv12( n)-bv2(n)+ v-2(n) (7. b) v3 ii) = n) -Q'zI n)-i-v32( i,) (7. c) and 1121/2±1) = (LIt")-°YiI fl)+ V111 /1) (8.a) 1221 n+1) = by1 (,, )-by1(n)+v,1(n) (8. b) ii ± 1) = CT'21( ) -cv1 (ti)+ i' Viz) (8. c) Equation set (8) can be rewritten as equation set (9): v1,1 ii) = a.(n-1)-ay1( n-i)+1'jjl,ti) (9.a) t'--,In)=bvi1In-i)-bviln-i)+v-,1(n-i) (9.b) "32(" ) = 2 i -/ )-C)'1 -/ )± " " -/ (9. c) Equation set (10) is derived by further substituting equation set (7) into equation set (8).

"1-,In)= 2aan-/)-a( y1rn-/)+v-(n-/))+vi,(n-/) (10 a) v22(n)=ab.(n-i)+2bv12(n-i)-bv1(n-1)-b(1+a)y,(n-i)+ v,2(n-i) (10 b) t'3-pt)=bevl-(it-i)+2cv22pt-i)-cyl1n-i,)-e11+b)v2(n-i)+ v32(n-i) (bc) The DIII AZ modulator which is shown in Figure 3 is derived directly from the time domain equation sets (7) and (10). The motive behind sharing one set of accumulator filters in a single feed forward path is to eliminate the instability that can arise due to the DC offset mismatch of the two individual accumulator set based two channel interleaving case. Known DIII AZ modulators need an input demultiplexer which samples the input signal at the highest clock frequency of the DIII AZ modulator and distributes it between channels. This fast demultiplexer is a limiting factor for the performance of the DIII AZ modulators. The architecture shown in Figure 3 does not need an input demultiplexer and the input signal is shared between channels. Removing the input demultiplexer has no effect on the NTF of the DTTI AZ modulator but it causes some notches in its SIF at the following frequencies 05a l.5Fs, which is shown in Figure 10 where is the clock frequency of the DIII AZ modulator.

Referring to the 3rd-order single-loop two-path DTTI AZ modulator with shared accumulators Figure 3, the two paths comprise a feed forward path arrangement 2 having three accumulator filters 4a, 4b, 4c each with a respective transfer function az1(1 - bz1(1 -zj cz1(1 -zj1, thus providing a third order arrangement. Each accumulator is preceded by a respective signal combiner 12a, 12b, 12c. The input signal x(n) is fed to signal combiners 12a, 12b via respective scalers 2, a. The output of accumulator 4a, vi(n) is fed to combiners 12b, 12c via scalers 2, b. The output of accumulator 4b, v22(n) is fed to combiners 12c, 12d via respective scalers 2, c, and the output of accumulator 4c, v32(n) is fed direct to combiner 12d and quantizer Q2.

The output of accumulator 4c is fed direct to a second path quantizer (ADC) Q2 62, and, via signal combiner 12d, to the input of a first path quantizer (ADC) 01 64. The output of 02 62 is fed in a second feedback path 8 to DAC 102 and then to subtracting inputs of each signal combiner 12a -12c, via scaling amplifiers 14, having respective values 1, 1-i-a, 1+b. The output of 01 64 is fed in a first feedback path 8 to DAC 101 and then to subtracting inputs of each signal combiner 12a -12c, via scaling amplifiers 16, having values 1. The output of 02 62, y2(n), is fed in a Delayless Path 30 having a scaler c, to a summing input of combiner 12d. The output yi(n) is fed via a x2 scaler 32 and delay circuit 34, to a signal combiner 36, where it is combined with the output y2(n), scaled by 2 as at 38 to provide the output signal y(n).

As regards operation of the single path Time Interleaved modulator, it will be noted there is an analog adder 12d in front of quantizer 01 and the input signal there generated is then applied to the quantizer 01. In discrete time delta-sigma modulators, quantizers sample this input. As stated in the above formulas, v32(n) and v31 (n) are the respective inputs of the second and first quantizers. v32(n) is the output of third accumulator 4c but v31(n) is: (v31 (n)=c*v22(n)c*y2(n)+v32(n)) (We will use an analog adder to generate v31(n) from v32(n), v22(n) and y2(n)). That means that v31(n) is generated by the outputs of the second and third accumulators 4b, 4c and also the output of the second quantizer Q2. The direct relation between v31(n) to y2(n) comprises the "delayless path".

An issue which makes implementation of the single-path TI A modulators impractical is this so-called "delayless feedback path" problem that comes from equation (7.c) above in which (" (the input of quantizer 01) is directly linked to Y2()* This means that the output of the second quantizer (02) is connected to the input of another quantizer (01) without any delay. One method to eliminate the delayless path is to move this feedback to the digital domain instead of performing it in the analog domain [K. S. Lee, referenced above]. The disadvantage of this method is that the first quantizer (01) requires more comparators than the number of the comparators in the second quantizer (02) . Another second method is to use a sample-and-hold in front of the first quantizer (01) and quantizing the signal when the output of DAC2 is ready [T.

C. CaIdwell, referenced above]. This method needs a complicated timing generator, a sample-and-hold and also faster accumulators.

An embodiment of the invention, as shown in Figure 5, overcomes the delayless path issue by an error correction technique. We intentionally induce an error in the analog domain through the use of the output of DAC2 102 as shown in Figure 5. The error is substantially corrected in the digital domain which effectively eliminates the delayless feedback path.

To better understand how this works we shall perform a step by step analysis of what happens. A timing diagram as depicted in Figure 4 shows the delay from the outputs of quantizers 01 and 02 and their propagation through to the outputs of DAC1 and DAC2 as. As a result the output of DAC2 that is sampled at the nth time slot is y2("M where we should have hadY2("). To overcome this inconsistency we look at the input and output of 01, as depicted in Figure 4. Quantizer 01 quantizes the signal "31(") as follows: Yi (n) = (21131(11)1 (11) Equation (12) is derived by substituting (7.c) into (11): Yi () = (21 CV22(fl) -CV, (;z) + 1/12(11)1 (12) The output of DAC2 is used in (13) and equation (12) is rewritten as: y1(n)=Q[CT2,(n)_cy2(n_])+v,2(n)]+Cy,(n_])_cJ2(n) (13) The output of 01 is called Yie(") in (14): = Yle(tl) +ev,( -Il) -ey,(,) (14) error= rAy = r(2@) --1)) (15) Yi(z) = l(z) -CU-z')Y2(z) (16) As appears from (14), (the output of 01) needs to be corrected before it is applied to the input of DAC1; otherwise it causes instability in the modulator as it will change the modulators dynamics by increasing its order. A first order differencer block (1-z5 is used to perform this correction as described in (16).

Equation (16) illustrates the point that 01 is able to quantize its input without any additional circuit in the analog domain by merely using the output of DAC2.

The differencer block only corrects the error in equation (14) and it has no effect on the quantization error or the signal.

The 3Fd order single-loop two path DTTI AZ modulator forming a first embodiment of the invention is shown in Figure 5. Referring to Figure 5, feed forward path arrangement comprises three accumulator filters 4a, 4b, 4c each with a respective transfer function az1(1 -z11, bz1(1 -z1)1 cz1(1 -thus providing a third order arrangement. Each accumulator is preceded by a respective signal combiner 12a, 12b, 12c. The input signal x(n) is fed to signal combiners 12a, 12b via scalers 2, a. The output of accumulator 4a, v12(n) is fed to combiners 12b, 12c via scalers 2, b. The output of accumulator 4b, v22(n) is fed to combiners 12c, 12d via scalers 2, c, and the output of accumulator 4c, v32(n) is fed direct to combiner 12d and quantizer 02.

The output of accumulator 4c is fed direct to second path quantizer 02 62, and, via signal combiner 12d, to the input of first path quantizer 01 64. The output of 02 is fed in a second feedback path 8 to DAC 102 and then to subtracting inputs of each signal combiner 12a-12d, via scaling amplifiers 14 having valuesi, 1+a, 1+b, and c. It will be noted there is a direct coupling 31 from the output of DAC 102 to the input of 01 64. The output of 01 is fed in a first feedback path 8 to DAC 101 and then to subtracting inputs of each signal combiner 12a-12c, via scaling amplifiers 1. The output of Q2, y2(n) is fed via an error correction circuit 50 having the transfer function c(1-z1) to a subtracting input of a signal combiner 51, where it is combined with the output of 01, y10(n), to give output yi(n). The output yi(n) is fed via a x2 scaler 52 and delay circuit 54, to a signal combiner 56, were it is combined in combiner 56 with the output y2(n), scaled by 2 as at 58.

The significant advantages and disadvantages of the Lee paper, referenced above, the CaIdwell paper, referenced above, and the present invention are summarized in the Table below: Method Comparator comparator Advantage Disadvantage ________________ count for Qi count for Q1 ___________________ __________________________ Lee 48 16 Additonal analog More comparators for Q1 blocks not needed required CaIdwell 16 16 Fewer Sample/Hold, complex comparators timing generator and fast _______________ ______________ _____________ __________________ integrators required Invention 32 16 Additonal analog More comparators blocks not needed required for Qi than _______________ ______________ _____________ __________________ caldwell The signal swing at the input of quantizer 01 is increased in the first and the present methods because scaling is not an option and it will lead to loss of Signal-to-Noise Ratio (SNR), the first and the present methods require 48 and 32 comparators for quantizer 01 respectively, in comparison to the second method which requires 16 comparators as depicted in Table I. The CTTI AZ modulator equivalent of the DTTI AZ modulator of Figure 5 can be obtained in three steps as follows: The first step is to determine the loop filters of the DTTI AZ modulator. In this design, the DTTI AZ modulator has six loop filters (17F17(z) , FF,(z) Hio(z) H21(z) H34(z) and 114d(z)) These loop filters for the DTTI AZ modulator are as depicted in Figure 6(a). The second step is to convert the DT loop filters into equivalent CT loop filters by using the impulse-invariant transformation. The equivalent CTTI AZ modulator is shown in Figure 6(b) where the DT loop filters of Figure 6(a) have been replaced with the equivalent CT loop filters FFi(s) FF21.(x) HiJs) H2(s) H3(s) and H41.(s) The third step is to convert the modulator of Figure 6(b) into a 3 order CTTI AZ modulator as shown in Figure 7. To overcome the excess-loop delay issue, two additional feedback paths from the outputs of DAC1 and DAC2 to the inputs of each quantizer (01 and Q2) are used. The loop filters of the modulator as shown in Figure 7 can be found and matched to those in Figure 6(b) to determine the coefficients fir, fc f4r, , foe fir, fi f9 and in Figure 7.

Referring to the 3rd-order Single-Loop Two-Path GUI AZ modulator with shared integrators of Figure 7, three sets of integrator filters 3a, 3b, 3c, in a feed forward path arrangement have their inputs provided by signal combiners 12a, 12b, 12c, combiners 12b and 12c each comprising two combiners in series.

Each integrator filter has a transfer function of the form ills, with respective scaling coefficients a, b, c. The input signal x(t) is fed to signal combiners 12a, 12b, 12c via scaling amplifiers having respective values 2, a, 2/3(ab). The output of integrator 3a, v12(t) is fed to combiners 12b, 12c via respective scaler amplifiers 2, b, the output of integrator 4b, v22(t) is fed to combiners 12c, 12d via scaling amplifiers 2, c, and the output of integrator 4c, v32(n) is fed direct to combiners 12d, 12e.

The output of integrator 3c is fed via signal combiner i2d to first path quantizer (ADC) 01 64, and via signal combiner i2e to the input of second quantizer (ADC) Q2 62. The output of Q2 62 is fed in a second feedback path 8 to DAG 92 and then to subtracting inputs of each signal combiner 12a -12e, via respective scaling amplifiers fc2, fc4, fC, fcw, fc8. It will be noted there is a direct coupling 31 from the output of DAC 92 to the input of 01 64. The output of 01 64, modified as at 51, is fed in a first feedback path 8 to DAC 94 and then to subtracting inputs of each signal combiner 12a -12e, via scaling amplifiers f34, fc& fcg, fc7. The output of 02, y2(n) is fed via an error correction circuit 50 having the transfer function c(i-z1) to a subtracting input of a signal combiner 51, where it is combined with the output of 01, yie(n), to give output yi(n). The output yi(n) is fed via a x2 scaler 52 and delay circuit 54, to a signal combiner 56, were it is combined in combiner 56 with the output y2(n), scaled by 2 as at 58 to give the final output y(n).

It will be noted that the outputs of DAG 92, 94 are each fed to each of quantizers 01, Q2, via signal combiners 12d, 12e, to overcome excess loop delay.

The OSR of the overall modulator shown in Figure 7 from x(t) to Y(") is 16 and has been designed to operate at 320MHz clock frequency for a 10MHz signal bandwidth. The resolution of 01 and 02 are 5bits and 4bits respectively.

After correcting the error as stated by equation (21) in the digital domain, Yi(' will be 4bits in length. Therefore, DAC1 and DAC2 both require 4bit DACs. To simplify the design, generally, the coefficient c scaling the first order differencer (1-z') in the digital domain should be chosen to be a number which is a power of two. This choice results in replacing the potentially complicated multiplier with a simple hard-wired shift.

The STFs of the DTTI and CTTI AZ modulators are plotted in Figure 8.

Since the'T1'Id') and IVTF2d(z) both have an identical amplitude, only the Thd is plotted in Figure 9 and is compared to the NTF of the conventional DT AZ modulator of Figure 4.

Referring now to Figure 10, which shows a third embodiment of the invention comprising a 4th-order Single-Loop Two-Path DTTI AZ modulator with shared accumulators, similar parts to those of previous embodiments, in particular Figure 5, are denoted by the same reference numeral. In contrast to Figure 5, Figure 10 comprises a 4th order single-path DITI AZ modulator, having four accumulator filter stages 4a, 4b, 4c, 4f. Accumulator 4f has a transfer function dz1(1 -z1)1, and has an input fed by combiner 12f, which receives a feedback signal from second path DAC 102, scaled by (li-c), a feedback signal from first path DAC 101, and the output from accumulator 4c, v32(n). The output of accumulator 4f, v42(n), is applied direct to the input of quantizer 02 62, and to signal combiner 12g, where it is combined with the output v32(n), scaled by d, and by the feedback signal from DAC 102, scaled by d, to provide a resultant signal v41(n) to the input of quantizer 01 64. The output of quantizer 01 is combined at 51 with the output of Q2, digitally corrected in correction circuit SOd by a factor d(1-z1).

Referring now to Figure 11, which shows a fourth embodiment of the invention comprising a 3rd-order Single-Loop Four-Path DTTI AZ modulator with shared accumulators, similar parts to those of previous embodiments, in particular Figure 5, are denoted by the same reference numeral. Figure 10 comprises a 3d order four-path DTTI AZ modulator, having three accumulator stages 4a, 4b, 4c in a feed forward path arrangement. Four quantizers of respective first, second, third and fourth paths are employed operating in parallel, 01 64, 02 62, Q3 66, 04 68. Quantizer 01 64 accepts an input from signal combiner 70, Quantizer 02 62 accepts an input from signal combiner 72, Quantizer 03 66 accepts an input from signal combiner 74, and Quantizer 04 68 accepts an input direct from accumulator 4c.

The output of quantizer 04 68 is applied direct to signal combiner 56 via a x4 scaler, which provides the final output y(n), and to a fourth feedback path which include a DAC 104. The output of quantizer Q3 66 is applied to a signal combiner 71, and thence to a third feedback path which include a DAC 103.

The output of quantizer 02 62 is applied to a signal combiner 73, and thence to a second feedback path which include a DAC 102. The output of quantizer 01 64 is applied to a signal combiner 75, and thence to a first feedback path which include a DAC 101.

The input signal x(n) is split into four parallel paths and is applied to combiners 12a, 12b, 12c, 12d, via respective scalers 4, 6a, 4ab, abc. The output of accumulator 4a, v14(n), is applied to combiners 12b, 72, 70 via respective scalers 4, bc, 3bc. The output of accumulator 4b, v24(n), is applied to combiners 12c, 74, 72, 70 via respective scalers 4, c, 2c, 3c. The output of accumulator 4c, v34(n), is applied directly to combiners 74, 72, 70.

The output of quantizer 04 68 is applied to signal combiner 56, scaled by a factor of 4, and via digital correction circuit 80, to signal combiners 71, 73, 75, via respective scalers c, c(b+1), c(b(a+2) +1). The output of quantizer 03 66 is applied to signal combiner 71, the output of 71 being scaled by a factor of 4, and applied to combiner 56 via a delay circuit z1. The output of 71 is also applied via digital correction circuit 82 to combiners 73, 75 via respective scalers c, c(b+1). The output of quantizer 02 62 is applied to signal combiner 73, the output of 73 being scaled by a factor of 4, and applied to combiner 56 via two delay circuits z1. The output of 73 is also applied via digital correction circuit 84 to combiner 75 via respective scaler c. The output of quantizer 01 64 is applied to signal combiner 75, the output of 75 being scaled by a factor of 4, and applied to combiner 56 via three delay circuits z1. The output of 73 is also applied via digital correction circuit 84 to combiner 75 via respective scaler c.

The feedback signal in the first path from DAC 101 is applied directly to combiners 12a, 12b, 12c. The feedback signal in the second path from DAC 102 is applied to combiners 12a, 12b, 12c, 70, via respective scalers (none), li-a, li-b, c. The feedback signal in the third path from DAC 103 is applied to combiners 12a, 12b, 12c, 70, 72 via respective scalers (none), 1+2a, 1+ab+2b, c(b+1), c. The feedback signal in the fourth path from DAC 104 is applied to combiners 12a, 12b, 12c, 70, 72, 74 via respective scalers (none), 1+3a, li-3abi-3b, c+2bc+abc, c(b+1), c. It will be noted there are direct couplings from the outputs of DACs 102 -104 to quantizers Q1-Q3.

In the single path modulator embodiments above, sharing the integrators/ accumulators between the input paths makes them robust to path mismatch effects compared to the typical Time-Interleaved (TI) modulators which have individual integrators in all paths. Practical issues like finite dc gain and bandwidth of the opamps, the DAC mismatches and offsets of the quantizers may not introduce any noticeable degradation in performance. For an OverSampling Ratio (OSR) of 16 and a clock frequency of 320MHz with all practical non-idealities the maximum SNDR of this modulator may be 78dB.

The present invention at least in embodiments provides a mechanism for resolving the delayless feedback path issue in TI MI modulators with reduced comparator count.

Claims (13)

1. CLAIMS1. A time interleaved delta sigma modulator including: a plurality of paths for respective time interleaved data channels, said paths comprising a feed forward path arrangement, including at least one filter stage, a first one of said paths including a first quantizer means being connected to a first feedback path including a first digital to analog conversion means, a second one of said paths including a second quantizer means being connected to a second feedback path including a second digital to analog conversion means, and the output of the first digital to analog conversion means having a coupling to the input of the second quantizer means, and the output of the first quantizer means being coupled to the output of the second quantizer means via a correction means for correcting errors introduced by said coupling.
2. 2. A time interleaved sigma delta modulator, according to claim 1, wherein the modulator is a discrete time modulator.
3. 3. A time interleaved sigma delta modulator, according to claim 2, wherein said feed forward path arrangement has at least first and second accumulator stages, and the output of the second stage is coupled to the input of the second quantizer means, and the outputs of both the first and second stages are coupled to the input of the first quantizer means.
4. 4. A time interleaved sigma delta modulator, according to claim 2, wherein said feed forward path arrangement has at least first, second and third accumulator stages, wherein an input signal is fed to the first and second stages, an output from the first stage is fed to the second and third stages, an output from the second stage is fed to the third stage and said first quantizer means, and an output from the third stage is fed to said first quantizer means, and directly or via further accumulator stages to said second quantizer means.
5. 5. A time interleaved sigma delta modulator, according to claim 3 or 4, wherein said feed forward path arrangement has at least first, second and third accumulator stages, wherein said first feedback path and said second feedback path are each coupled to each of said first, second and third accumulator stages.
6. 6. A time interleaved sigma delta modulator, according to claim 1, wherein the modulator is a continuous time modulator.
7. 7. A time interleaved sigma delta modulator, according to claim 6, wherein said feed forward path arrangement has at least first and second integrator stages, and the output of the second stage is coupled to the input of the second quantizer means, and the outputs of both the first and second stages are coupled to the input of the first quantizer means.
8. 8. A time interleaved sigma delta modulator, according to claim 6, wherein said feed forward path arrangement has at least first, second and third integrator stages, wherein an input signal is fed to the first, second and third stages, an output from the first integrator stage is fed to the second stage and to the third stage, an output from the second integrator stage is fed to the third stage and said first quantizer means, and an output from the third integrator stage is fed to said first quantizer means, and directly or via further integrator stages to said second quantizer means.
9. 9. A time interleaved sigma delta modulator, according to claim 7 or 8, wherein said feed forward path arrangement has at least first, second and third integrator stages, wherein said first feedback path and said second feedback path are each coupled to each of said first, second and third integrator stages.
10. 10. A time interleaved sigma delta modulator, according to any of claims 7 to 9, wherein said first feedback path and said second feedback path are each coupled to each of the inputs of said first and second quantizer means.
11. 11. A time interleaved sigma delta modulator, according to any preceding claim, wherein said correction means is a digital differencing circuit having a transfer function of the form (1-z1).
12. 12. A time interleaved sigma delta modulator, according to claim 11, wherein a coefficient scaling said transfer function of the form (1-z1) comprises a number which is a power of two.
13. 13. A time interleaved sigma delta modulator, according to any preceding claim, wherein the modulator has at least three paths with respective first, second and third quantizer means, said third quantizer means being connected to a third feedback path including a third digital to analog conversion means, the output of the third digital to analog conversion means having a further coupling to the inputs of the first and second quantizer means, and the output of the third quantizer means being coupled to the outputs of the first and second quantizer means via respective further correction means for correcting errors introduced by said further coupling.