GB2524051A

GB2524051A - Apparatus and method for filtering digital signals

Info

Publication number: GB2524051A
Application number: GB1404402.8A
Authority: GB
Inventors: Dusan Raic; Janez Trontelj
Original assignee: Univerza v Ljubljani
Current assignee: Univerza v Ljubljani
Priority date: 2014-03-12
Filing date: 2014-03-12
Publication date: 2015-09-16
Also published as: GB201404402D0

Abstract

The decimating register 15 in a cascaded-integrator-comb filter is clocked at a lower rate but in synchronism with the integrating filter section 10, so that the delay in the register 15 is the same as in the delay elements 14 of the integrating stage. This addresses a problem in that during the first cycle of a down-sampling period the output of a down-sampling register may not be defined. The decimating register 15 and the delay elements in the comb filter 20 may share a common clock enable signal EFIR or a common clock signal (fSR, figure 5). An interpolation filter may be implemented in a similar fashion.

Description

Apparatus and Method for Filtering Digital Signals The present disclosure relates to methods and apparatus for digital signal processing, and more particularly to digital filters, still more particularly to filters comprising intergrators and/or comprising comb filters, still more particularly to filters comprising cascaded filter elements such as cascaded integrator-comb filters Cascaded integrator-comb (CIC) decimation filters are widely used in communication and data processing systems. Such filters find particular application in high-precision analog to digital conversion. Such analog to digital conversion may employ oversampling, and sigma-delta modulation.

A GIG decimation filter typically comprises an integrator stage coupled to a comb filter stage by a down-sampler. Such a filter may be provided with a frequency at a first, high, sampling rate. The integrator stage may act as a low pass filter, and the down-sampler may decrease the sampling rate of the low pass filtered signal before it is provided to the comb filter stage.

Existing GIG decimation filter implementations follow the topology proposed in the paper "An Economical Class of Digital Filters for Decimation and Interpolation" by E. Hogenauer, published in IEEE Transactions on acoustics, speech and signal processing Vol. ASSP-29, No. 2, April 1981. In this topology, a cascaded integrator stage, down-sampler and a cascaded comb stage are connected in series. In this topology, the cascaded integrator stage comprises a number, N, of integrators connected in series and, the cascaded comb section comprises a number, N, of comb filters connected in series. The number, N, of integrator/comb pairs is also known as the filter order' N. Some implementation issues of the GIG decimation filters have been presented in the paper "A High Throughput Programmable Decimation and Interpolation Filter" by Y. Djadi, T.A. Kwasniewski, and C. Chan, published in The Proceedings of the 5th International Conference on Signal Processing Applications & Technology Vol. II, October 1994.

Aspects and embodiments of the disclosure are defined in the appended claims.

Aspects and embodiments of the disclosure are also described, by way of non-limiting example only, with reference to the accompanying drawings, in which: Figure 1 shows a schematic illustration of a filter; Figure 2 shows an illustration of a timing diagram, indicating the timing of signals in the filter of Figure 1; Figure 3 shows a more detailed schematic view of selected components of the filter of Figure 1; Figure 4 shows an illustration of a timing diagram, indicating the timing of signals relevant to Figure 3; Figure 5 shows a schematic illustration of a filter; Figure 6 shows an illustration of a timing diagram, indicating the timing of signals in the filter of Figure 5; Figure 7 shows a more detailed schematic view of selected components of the filter of Figure 5; and Figure 8 shows an illustration of a timing diagram, indicating the timing of signals relevant to Figure 7.

In the drawings, like reference numerals are used to indicate like elements.

In some filters a first filter stage, such as a low-pass or anti-aliasing filter may be coupled to a second filter stage by a sampling adjustment stage that changes the sample rate of the signal -for example for decimation or interpolation of the signal (up-sampling or down-sampling). This enables the second filter stage to operate at a different, for example lower, sampling frequency than the first filter stage, thereby reducing the complexity and power consumption of this second filter stage.

It will be appreciated by the skilled addressee in the context of the present disclosure that in such sampling adjustment stages a register may be used to change, e.g. to reduce, the sample rate of a signal. For example, a signal with a sample rate, f, may be down-sampled by using a register triggered by an enable-signal having a period which is a multiple, R, of the sample period of the signal to be down-sampled. This may provide a down-sampled signal having a reduced sample rate fsR, where R= fsIfsR.

This may present a problem in that during the first cycle of this down-sampling period, the output of such a register may not be defined. One way to address this problem is to provide a switch in the down-sampler which replaces the register output with the input to the down-sampler for the first cycle of the down-sampling period. The inventors in the present case have however appreciated that may cause its own problems, and that surprisingly it is also possible to avoid the use of such a switch whilst also reducing the number of direct signal paths from the first filter stage to the second filter stage to be reduced, and perhaps eliminated. For example, where a filter comprises a comb filter stage and an integrator filter stage, embodiments of the disclosure may reduce or eliminate direct signal paths from the integrator to the comb stage. Transients in the comb section, as well in the filter output at the end of the down sampling cycle may also be reduced or eliminated.

In the interests of clarity, and to avoid crowding the drawings unnecessarily, a single bit filter is illustrated in the drawings which follow. As will be appreciated in the context of the present disclosure to process multi-bit data words, embodiments of the disclosure may comprise multiple single bit channels arranged in parallel.

Figure 1 illustrates an example of a digital filter. The filter shown in Figure 1 comprises a first filter stage 10, a second filter stage 20, a sampling adjustment stage 15, and an enable-signal provider. The filter configuration illustrated in Figure 1 finds particular application in CIC decimation filters where the first filter stage 10 comprises a an integrator stage, the second filter stage comprises a comb filter, and the sampling adjustment stage 15 comprises a down-sampler. However, as will be appreciated in the context of the present disclosure the first filter stage 10 need not be an integrator, other kinds of filters such as other low-pass filters or anti-aliasing filters may be used as this first filter stage 10. In addition, the second filter stage need not be a comb filter.

Examples of the disclosure may also be used in interpolating filters, so the sampling adjustment stage 15 could be an up-sampling or down-sampling stage. Accordingly, to avoid unnecessary inconsistency or redefinition of language, neutral terminology is used below.

As illustrated in Figure 1, the first filter stage 10 comprises a plurality of filter elements 10-1, 10-2.10-N, arranged in series. The last filter element 10-N in the series is coupled to the sampling adjustment stage 15. The sampling adjustment stage 15 is coupled to the second filter stage 20. The second filter stage 20 also comprises a plurality of filter elements 20-1, 20-2... 20-N, arranged in series. The sampling adjustment stage 15 and the second filter stage are coupled to the enable-signal provider to receive an enable-signal, EFIR, configured to clock samples through the sampling adjustment stage 15 and the second filter stage 20.

The enable-signal provider 25 is configured to provide an enable-signal, EFIR, to the sampling adjustment stage 15, so that the switching frequency of the enable-signal, EFIR, defines the adjusted sample rate of the sampling adjustment stage 15 output. This enable-signal is selected to provide a common sampling rate in the output of the sampling adjustment stage 15 and the second filter stage 20. This sampling rate may be lower than the sampling rate of the first filter stage 10.

The sampling adjustment stage 15 is configured to obtain a series of input signal samples from the first filter stage 10 at the first sample frequency and to adjust their sampling rate based on the enable-signal, EFIR, to provide a series of output signal samples at an adjusted sample rate to the second filter stage.

The second filter stage 20 is configured to obtain the series of signal samples, provided as output from the sampling adjustment stage 15, and to modify the frequency content of these samples according to the transfer function of the second filter stage.

Each filter element 10-1, 10-2.10-N, of the first filter stage 10 illustrated in Figure 1 comprises a signal combiner 12 and a delay element 14. In these filter elements 10-1, 10-2, the delay element 14 is arranged in a pipelined configuration to receive a sample of a combined signal from the signal combiner 12. In this pipelined configuration, the output of each filter element 10-1, 10-2 is provided by the output of its respective delay element 14. The last filter element 10-N of the first filter stage 10 is arranged differently however in that the output of its signal combiner 12 is coupled to provide a signal sample to the input of the sampling adjustment stage 15 without that signal sample being delayed by the delayelement 14. Instead, the output of that signal combiner is connected to both the input of its delay element and to the input of the sampling adjustment stage 15.

Accordingly, in some embodiments the delay element of this last filter element of the first filter stage 10 is not pipelined.

In this configuration, the sampling adjustment stage 15 may therefore be configured to apply a constant delay to signal samples provided by the first filter stage 10 because it need not accommodate for the absence of new data in the first cycle of a down-sampling (or up-sampling) period. This constant delay can correspond to the delay that would otherwise be provided by the last delay element in the first filter stage 10.

Where the sampling adjustment stage 15 is a down-sampling stage, this embodiment of the disclosure therefore can reduce the sampling rate of a series of samples output from the first filter stage 10 whilst also applying a constant delay (e.g. that of the last filter element of the first filter stage 10) to signal samples provided by the first filter stage 10, and to provide the delayed signal samples to the second filter stage 20.

Operation of the apparatus shown in Figure 1 is illustrated by the signal timing diagram shown in Figure 2. As illustrated in Figure 2, every R cycles of the clock signal f the enable-signal EFIR provides a signal pulse to the sampling adjustment stage 15, and to the delay elements of the filter elements in the second filter stage 20. In response to this enable signal, the sampling adjustment stage 15 provides a sample to the second filter stage 20. The enable signal also clocks the filter elements 20-1, 20-2... 20-N, of the second filter stage 20 to move samples through the second filter stage 20.

Figure 3 illustrates one example of an enable-signal provider and a sampling adjustment stage 15 arranged to provide down-sampling. It will be appreciated that the apparatus illustrated in Figure 3 can be used to provide the enable-signal provider and a sampling adjustment stage 15 for use in the apparatus illustrated in Figure 1.

The enable-signal provider illustrated in Figure 3 comprises a counter 30 and a decoder 32. The counter 30 is coupled to receive a clock signal having a frequency, f, which is the same as the sample rate of the signal to be down-sampled. The counter 30 is coupled to provide a count signal, t,, indicating the number of cycles of the clock signal.

The decoder 32 is configured to provide an enable-signal pulse, EFIR, each time the count signal is an integer multiple of the down-sampling factor, R. This enable signal therefore has a frequency that is a factor, R, less than the frequency of the clock signal f. The enable-signal, EFIR, can be coupled out to drive the filter elements of the second filter stage 20 of the apparatus illustrated in Figure 1.

The sampling adjustment stage 15 illustrated in Figure 3 comprises a register. The register comprises a signal sample input for receiving signal samples, an enable-signal input, a clocking input, and a signal sample output. The register is configured to respond to an enable-signal pulse applied to its enable-signal input by storing the signal sample input for the duration of the pulse, and, to set its signal sample output based on this stored sample input on the clock edge of the enable-signal, for example on the falling edge of this signal, for example immediately before this signal drops from HIGH' to LOW'.

It will also be seen that the down sampler apparatus illustrated in Figure 3 may be provided by a single register, which may be considered as an additional, alternative, delay element of the last filter element of the first filter stage 10 that, rather than being arranged to feedback to the signal combiner of that filter element, simply couples the signal from the first filter stage 10 to the second filter stage 20.

In operation, as illustrated in Figure 4, a series of pulses of a clock signal are provided to the counter 30 with a frequency, f. The counter 30 increments a count t0 for each cycle of this signal. The decoder 32 provides a digital high' signal each time the count t0 is an integer multiple of R-1, where R is an integer.

The register of the sampling adjustment stage 15 receives a series of samples, DSCIN, at its data input, D. Each time the enable-signal applied to it's enable input, E, goes high, the register obtains a new sample from the signal DSCIN, and on the falling edge of the enable signal, sets its output, 0, based on the value of that new sample. As illustrated in Figure 4, this has the effect of reducing the sample rate of the signal DSCIN to a new rate fixed by the enable signal. In the embodiment illustrated in Figure 3 this provides a reduction in sample rate (a down-sampling') by a factor R. The apparatus thus far has been described with reference to the processing of a single bit digital signal. When dealing with multi-bit data words, each of the first filter stage 10, the sampling adjustment stage 15, and the second filter stage 20 comprise a plurality of single bit channels arranged in parallel. Embodiments of the disclosure avoid the need to provide a switch in each of these channels in the sampling adjustment stage 15-as will be appreciated in the context of the present disclosure -this may avoid the need to provide a large number of gates each with different transition times. This can cause spurious switching activity to be injected into the second filter stage 20 (e.g. a comb stage of the filter). This may cause errors in the signal output from the second filter stage 20. In examples where the second filter stage 20 comprises a comb filter, due to the nature of comb filters, a direct data path may continue all the way to the filter output and therefore cause output errors. Embodiments of the present disclosure may avoid or mitigate these issues.

Figure 5 illustrates a further example of a digital filter. The filter shown in Figure 5 is adapted to provide a down-sampling factor, R, which is an integer power of 2, where R=2K. The apparatus illustrated in Figure 5 comprises a first filter stage 10, a second filter stage 20', a sampling adjustment stage 15', and an enable-signal provider 25'. In Figure 5 and Figure 1 like reference numerals are used to indicate like elements. The structure, and function, of the apparatus illustrated in Figure 5 is the same as that described above with reference to Figure 1. However, the sampling adjustment stage 15' the enable-signal provider 25' and delay elements in the second filter stage are modified so that enabled registers are replaced by edge-triggered flip-flops, as illustrated in Figures 5 and 7. This may simplify the timing and circuit implementation by the elimination of the decoder and clock gates since the register enable inputs are not needed any more.

As illustrated in Figure 7 the enable-signal provider 25' illustrated in Figure 5 comprises a K-bit counter 40, and an inverting buffer 42. The sampling adjustment stage comprises a delay element 50. The delay element 50 illustrated in Figure 5 comprises an edge triggered flip flop. The output of the counter 40 is coupled to the inverting buffer 42. The output of the inverting buffer 42 is coupled to the clock input of the delay element 50 and to clock inputs of delay elements in the second filter stage 20'.

As with the apparatus illustrated in Figure 3, the K-bit counter 40 illustrated in Figure 5 is coupled to receive a clock signal having a frequency, f, which is the same as the sample rate of the signal to be down-sampled. The K-bit counter 40 is configured to count cycles of the clock signal as a binary coded integer. The most significant bit of this counter is coupled to provide the output of the counter to the inverting buffer to generate the clock signal for delay elements in the sampling adjustment stage 15' and in the second filter stage 20' of the filter illustrated in Figure 5.

In operation, as illustrated in Figure 8, every R cycles of the clock signal, f5, the most significant bit of the K-bit counter 40 toggles from HIGH" to LOW, and the output of the inverting buffer 42, fsR, goes HIGH'. This clocks a sample from the input, DSCIN, of the delay element 50 of the sampling adjustment stage 15' to its output. The signal, fsR, also provides a clock signal to the delay elements of the second filter stage 20' of the filter illustrated in Figure 5.

In some examples of the disclosure the first filter stage comprises a low pass filter, such as an integrator. In these examples each filter element of the first filter stage may comprise an integrator.

Each filter element may have a transfer function, h(z). Where these filter elements are arranged in series in a filter stage of order, N, their combined transfer function may comprise H(z)=[h(z)f. In one example each filter element of the first filter stage comprises an integrator, these filter elements may have a transfer function h(z)=1/(1-t1), so the transfer function of the first filter stage may comprise H(z)=1/(1-z')". This is merely exemplary, and other types of filters having other types of transfer function, may also be used.

As mentioned above, in some examples of the disclosure the second filter stage may comprise a comb filter, and this may have particular advantages. However, the second filter stage may comprise any finite impulse response, FIR, or infinite impulse response, IIR, filter. The second filter stage may comprise a low pass, high pass or band pass filter.

As will be appreciated in the context of the present disclosure, a comb filter may comprise any filter which adds a delayed version of a signal to itself Examples of filter elements for a comb filter each have transfer functions, h(z), comprising h(z)=1-z.

Accordingly a cascade, or series of N such elements may have a transfer function, H(z) =(l-zf'.

In examples where the second filter stage comprises a comb filter, the digital filter may be configured to provide a cascaded integrator comb filter.

The signal combiners described herein may be additive combiners, configured to provide an output based on a linear combination, for example a sum, weighted sum, or difference of at least two input signals. The delay elements described herein may comprise filter taps. Examples of hardware which may be used to provide such delay elements comprise registers, or any other apparatus operable to obtain a sample of a signal, hold that sample for at least one cycle of a clock signal, and output the held sample in response to a trigger signal such an enable-signal as described above. Examples of such hardware may be provided by flip flops, such as edge triggered flip flops. Edge-triggered flip-flops include the R-S flip-flop, the 0-type flip-flop and the JK-type flip-flop.

Although described with reference to particular hardware, it will be appreciated that any register may be used as a delay element, and functionally equivalent elements, which may be provided by software or signal processing architecture may also be used.

In some examples, where a filter element comprises a pipelined delay element, the output of its signal combiner is coupled to an input of its delay element. A signal sample output from the delay element is provided as the output of the filter element. This output can also be coupled back to an input of the signal combiner. This is in contrast to a non-pipelined delay element in which a signal sample output from the signal combiner is output from the filter element, and fed back via the delay element to the input of the signal provider to be combined with a subsequent signal sample.

With reference to the drawings in general, it will be appreciated that schematic functional -10-block diagrams are used to indicate functionality of systems and apparatus described herein. It will be appreciated however that the functionality need not be divided in this way, and should not be taken to imply any particular structure of hardware other than that described and claimed below. The function of one or more of the elements shown in the drawings may be further subdivided, and/or distributed throughout apparatus of the disclosure. In some embodiments the function of one or more elements shown in the drawings may be integrated into a single functional unit.

For the same reason, clock signal connections in Figure 1 and in the first filter stage in Figure 5 are not shown. The delay elements in these stages may be synchronized by the same clock, e.g. a clock signal having a frequency, f, which matches the sample rate of the first filter stage. It is also assumed that the registers in the sampling adjustment stage 15, and in the second filter stage 20 may be operable to store input data when the enable input signal is HIGH' and then transfer the internal state to the output at the active clock edge when the enable signal goes from HIGH' to LOW.

The above embodiments are to be understood as illustrative examples. Further embodiments are envisaged. It is to be understood that any feature described in relation to any one embodiment may be used alone, or in combination with other features described, and may also be used in combination with one or more features of any other of the embodiments, or any combination of any other of the embodiments. Furthermore, equivalents and modifications not described above may also be employed without departing from the scope of the invention, which is defined in the accompanying claims.

In some examples, one or more memory elements can store data and/or program instructions used to implement the operations described herein. Embodiments of the disclosure provide tangible, non-transitory storage media comprising program instructions operable to program a processor to perform any one or more of the methods described and/or claimed herein and/or to provide data processing apparatus as described and/or claimed herein.

The activities and apparatus outlined herein may be implemented with fixed logic such as -11 -assemblies of logic gates or programmable logic such as software and/or computer program instructions executed by a processor. Other kinds of programmable logic include programmable processors, programmable digital logic (e.g., a field programmable gate array (FPGA), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM)), an application specific integrated circuit, ASIC, or any other kind of digital logic, software, code, electronic instructions, flash memory, optical disks, CD-ROMs, DVD ROMs, magnetic or optical cards, other types of machine-readable mediums suitable for storing electronic instructions, or any suitable combination thereof

Claims

-12 -Claims: 1. A digital filter comprising a first filter stage coupled to a second filter stage by a sampling adjustment stage, wherein: the first filter stage comprises a first filter element comprising a first signal combiner and a first delay element arranged in a pipelined configuration to receive a combined signal from the signal combiner, to delay the combined signal, and to provide the delayed combined signal to the first signal combiner and to a second filter element; and the second filter element comprises a second signal combiner and a second delay element, wherein the input of the sampling adjustment stage is coupled between the input of the second delay element and the output of the second signal combiner.
2. The digital filter of claim 1 wherein the sampling adjustment stage is configured to apply a constant delay to signal samples provided by the first filter stage.
3. The digital filter of claim 2 wherein the constant delay corresponds to the delay provided by the second delay element.
4. A digital filter comprising a first filter stage comprising a first filter element and a second filter element coupled to a second filter stage by a sampling adjustment stage configured to apply a constant delay to signal samples provided by the first filter stage, and to provide the delayed signal samples to the second filter stage, wherein the constant delay corresponds to a delay provided by the second filter element.
5. The digital filter of claim 4 wherein the sampling adjustment stage is coupled to receive an output signal sample from the second filter element and said second filter element comprises a second signal combiner and a second delay element arranged to delay the output signal sample by a delay equivalent to the constant delay, and to provide the delayed output signal sample to the signal combiner.
6. A digital filter comprising a first filter stage comprising a first filter element and a second filter element arranged to couple the first filter stage to a second filter stage, -13-wherein the first filter element comprises a first signal combiner and a first delay element and the second filter element comprises: a second delay element, a second signal combiner arranged to combine a signal sample from the first filter element with a delayed signal sample from the second delay element, and a third delay element coupled to provide the combined signal sample to the second filter stage, wherein the second delay element is arranged to delay the combined signal sample received from the second signal combiner.
7. The digital filter of claim 6 wherein the third delay element is provided by a delay element of a sampling adjustment stage of the filter.
8. The digital filter of any preceding claim wherein the first filter stage comprises a low pass filter.
9. The digital filter of claim 8 wherein the low pass filter comprises an integrator.
10. The digital filter of any preceding claim wherein the second filter stage comprises a comb filter.
11. The digital filter of any preceding claim wherein the sampling adjustment stage comprises a down-sampler.
12. The digital filter of any of claims ito 5, or claim 7, or any of claims 8 to 11 as dependent thereon wherein the sampling adjustment stage, and second filter stage are configured to be driven by a common enable signal.
13. The digital filter of any of claims Ito 5, or any of claims 7 to 11 as dependent thereon, wherein the sampling adjustment stage, and second filter stage are configured to be driven by a common clock, and the period of the clock signal corresponds to a delay provided by the third delay element. -14-
14. The digital filter of claim 13 wherein the first filter stage is coupled to the second filter stage solely by the sampling adjustment stage.
15. A cascaded integrator-comb decimation filter comprising the digital filter of any preceding claim.
16. A data processor comprising a filter according to any preceding claim.
17. A programmable processor programmed to provide a filter according to any of claims Ito 15.
18. A computer program product operable to program a processor to provide a filter according to any of claims ito 15.
19. A cascaded integrator-comb decimation filter substantially as described herein with reference to the accompanying drawings.