GB2523108A

GB2523108A - Frame synchronization at low ADC resolution

Info

Publication number: GB2523108A
Application number: GB1402438.4A
Authority: GB
Inventors: Mounir Achir; Walaa Sahyoun
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2014-02-12
Filing date: 2014-02-12
Publication date: 2015-08-19
Also published as: GB201402438D0

Abstract

The invention produces I and Q datastreams which are up-mixed and transmitted (Fig. 2). The I and Q datastreams may be identical. The receiver performs I and Q down-mixing on the signal to produce I and Q (Fig. 3) analogue signals that are sampled, possibly oversampled at 3 samples per symbol period. A 1-bit ADC may be used for sampling. The invention may autocorrelate the I and Q digital signals for frame detection 503-4. If a frame is detected 505-6 cross correlation with a known 508-9 or inverted 511-12 synchronisation sequence may be performed. This allows the demodulation of the (anti)phase I and Q signals. The invention may then perform error checking on the demodulated I and Q signals and select the one with the least errors. The invention may be used with channels operating in terahertz bands and is intended to allow signal demodulation without requiring frequency offset compensation.

Description

Frame synchronization at low ADC resolution

FIELD OF THE INVENTION

The present invention relates to heterodyne terahertz transceivers.

The electromagnetic spectrum is classically considered as separated into two large bands.

The first band includes the usual frequencies (referred to as the "radio waves") used for wireless communications. These radio waves are electromagnetic radiations having frequencies from 3 KHz up to 300 GHz.

The second band starts from around 1 THz, includes the optic radiations and encompasses the infrared, the visible, Ultraviolet, X-Rays and Gamma rays.

The so-called "terahertz band" contains the frequencies ranging from GHz up to 10 THz, and hence includes a part of the radio electromagnetic radiations and a part of the optic electromagnetic radiations. The terahertz band is actually of particular interest and is considered for ultra-high speed wireless communications, principally due to its large available bandwidth. The frontiers of the terahertz band are not clearly defined; different values for the up and the down frequencies are considered in the literature. However, two bands are often used to define the terahertz band: 100 GHz up to 101Hz and 0.3 GHz up to 3 1Hz.

The large available bandwidth of the terahertz band is not its only advantage. The hardware used for terahertz communications (in particular the antennas) can be easily integrated in the current common communication devices the size of which is being reduced.

The integration being facilitated, several applications are possible, from ultra-high speed audio/image/video transfer between devices to intra-machine communications (i.e. wireless communication between two or more components inside one device).

Before bringing the terahertz communication technology to the market, many problems are to be solved. The terahertz technology is not yet mature even if it appears that solutions for Terahertz detection at room temperature exist as it appears from document Kallfass et al, All Active MM/C-Based Wireless Communication at 220 GHz", IEEE Transactions on Terahertz Science and Technology Vol 1, Number2, November 2011 and document Hiwei Xu et al, "D-Band CMOS Transmitter and Receiver for Multi-Giga-Bit/sec Wireless Data Link', 40th European Microwave Conference, September 2010.

Solutions for Terahertz generation (at room temperature) with sufficient power for transmission at distance over the meter are scarce.

Experiments using only Amplitude Modulation were reported.

BACKGROUND OF THE INVENTION

There is still a need for experimental results concerning phase modulation and heterodyne architectures. There is also a need for reliable modular interconnection of hardware devices at Terahertz frequencies.

Moreover, the antenna efficiency reported on silicon integrated antennas is still poor.

In parallel to the effort to develop terahertz transmitters and receivers capable of transmitting and receiving wideband modulated signals, the research community works also on the terahertz electromagnetic propagation modelling.

For the terahertz waves, as for radio waves, knowing the propagation model is important in order to well conceive and dimension the communication system, in particular for the digital part (Modulation and coding scheme) and the antenna design.

Only few models are actually available for the terahertz propagation.

In document Kallfass et al. discussed hereinabove, one of the first models, developed by the HSCA (Harvard-Smithsonian Center for Astrophysics) is used.

The model, which is available under a freeware that can be downloaded from the HSCA website, is called "am" for Atmospheric Model. The "am" model makes it possible to perform radiative transfer computations from microwave to sub-millimeter wavelengths. With this model, one can see that above around 350 GHz, for example, the humidity has no effect and the attenuation is more severe. This "am" model is available for outdoor and for long distance communications.

Recently, some measurements/modelling efforts are also directed to better understanding the behavior/propagation of the terahertz waves on specific scenarios completely different from those that have been considered for building the "am" model.

Document Sebastian Rey at al., "On Propagation Characteristics of Waveguide-like ABS-structures in 60GHz and 300GHz communications", IRMMW THz 2013, Mainz, Germany and document Alexander Fricke et al., "Reflection and transmission properties of plastic materials at THz frequencies", IRMMW 1Hz 2013, Mainz, Germany investigate the behavior of the terahertz waves in indoor and intra-machine communications in order to characterize and determine the way that the terahertz waves propagate in such environment.

The synchronization issue is inevitable in all communication systems.

Most physical transmission medium are inefficient in transmitting baseband signals. Consequently, the digital baseband signal to be transmitted has to be converted into a continuous time waveform and then modulated by a higher frequency carrier signal. The modulated in then transmitted through the physical medium and is processed (sampling, digitization, demodulation, impairments correction/compensation, Error correction or the like).

In wireless communication receivers, coherent demodulation needs a local oscillator having exactly the same carrier frequency as the carrier signal contained in the received signal. Furthermore, accurate sampling clock frequency and phase is needed to allow the demodulator to recover the transmitted digital data.

However, in realty, the receiver is not synchronized with the transmitter and thus does not have exactly the same phase/frequency. This mismatch degrades the communication quality hence some digital signal processing techniques are applied to reduce the effect of this impairment.

Several methods can be used to estimate and compensate the carrier frequency offset. The correction of this offset is highly recommended. The following formula, from document T.D. Chiueh, P.Y. Tsai, "OFDM Baseband Receiver Design for Wireless Communications", WILEY 2007., gives a relation between the SNR, the carrier frequency offset and the degradation of the SNR in dB due to this offset: 10, 2 E = (JEEp) .-where 3.tn(10) J N0' DSWR is the degradation of the SNR (in dB); is the carrier frequency offset in ppm (part per million); is the signal to noise ratio (in dB).

Figures la-lb illustrate two methods for estimating and compensating the carrier frequency offset.

Figure la illustrates a time domain correction in an OFDM communication system. In order to compensate the carrier frequency offset (CFO), a time domain "derotato( is commonly used. The "derotator" is a complex multiplier, which rotates the complex value input by a phase. The estimation of the CFO is carried out in the frequency domain and the correction is carried out in the time domain.

Figure lb illustrates an alternative method, applicable for OFDM systems, where the estimation and the correction are done in the frequency domain. In this case, the correction is carried out by the interpolation and the CFO estimation can be obtained by using, for instance, training sequences. The following equation, known as the maximum likelihood estimation, is commonly used for the estimation of the frequency offset between the transmitter and the receiver local oscillators: 217 = 2irL.phase(;'zm_rzm_r_L) wherein: -217 is an estimation of Af; is the Carrier frequency Offset and causes a rotation of the received complex baseband signal over the time; -Z1 is the i-th index of the one period of the preamble (i.e. the preamble is constructed by concatenating several periods having the same sample values; i.e. a training sequence); -R is the repetition interval; -L is the separation between two adjacent intervals; -T is the sampling period.

The compensation of the carrier frequency offset is done by multiplying the received samples by a complex value having a norm equal to 1 and a phase that depends on Aj. The following formula illustrates this operation: = z(t).ei2ThAJ, wherein: -z(t): is the received data samples; -z1: is the corrected data samples; -Aj: is an estimation of Af; Af is the Carrier frequency Offset.

The use of high speed ADCs implies the use of very few bits in quantization. Having low resolution makes difficult the accurate estimation of the carrier frequency offset and its compensation.

Thus, there is a need for improved frame synchronization using low resolution ADCs in heterodyne transceiver.

The Invention lies within this context.

SUMMARY OF THE INVENTION

According to a first aspect of the invention there is provided a signal processing method, the method comprising: -receiving an analog input signal; -performing I/O demodulation on the analog input signal thereby obtaining an analog in-phase (I) signal and an analog quadrature (0) signal; -digitizing the analog in-phase signal and the analog quadrature signal thereby generating, respectively, a digital in-phase signal and a digital quadrature signal; and -forming a reconstructed digital signal from the digital in-phase signal and the digital quadrature signal wherein each block of data of the reconstructed digital signal is obtained from one of a block of data in the digital in-phase signal and a corresponding block of data in the digital quadrature signal.

A method according to the first aspect provides robust wireless transmission in the presence of carrier frequency offset impairment in heterodyne terahertz transceivers.

With a method according to the first aspect, a shared clock between the transmitter and the receiver is not needed. The transmitter and the receiver may have their own respective local oscillator.

Also, there is no need for performing Carrier Frequency Offset (CFO) correction. In particular, there is no need for compensation or estimation of the carrier frequency offset.

Analog to digital converters (ADCs) with low resolution can be used.

According to embodiments, the digital in-phase signal and the digital quadrature signal are representative of data frames, each frame containing a preamble sequence for detecting the start of the frame and a plurality of blocks of data.

For example, each frame further contains a synchronization sequence enabling determining if the frame needs to be inverted, by performing a cross correlation with a predetermined synchronization sequence.

According to embodiments: -the block of data that is obtained for forming a given frame of the reconstructed digital signal is selected among one of a block of data in a first frame and a corresponding block of data in a second frame based on the number of errors detected therein, and -the first frame corresponds to: * a frame of the digital in-phase signal if a correlation exists between the synchronization sequence of the frame and the predetermined sequence, and to * an inverted frame of the digital in-phase signal if a correlation exists between the synchronization sequence of the frame and an inverted version of the predetermined sequence; and -the second frame corresponds to * a frame of the digital quadrature signal if a correlation exists between the synchronization sequence of the frame and the predetermined sequence and to * an inverted frame of the digital quadrature signal if a correlation exists between the synchronization sequence of the frame and an inverted version of the predetermined sequence.

For example, the block of data selected is the block of data that contains a minimum number of errors.

According to embodiments, the existence of errors is checked using a cyclic redundancy code.

For example, a BPSK demodulation is performed prior to the forming step for generating the in-phase and quadrature bit-stream.

According to a second aspect of the invention there is provided a signal processing method, the method comprising: -performing amplitude or BSPK modulation of a digital sequence thereby obtaining a digital signal, -duplicating the digital signal into a digital in-phase signal and a digital quadrature signal; -performing l/Q modulation on the digital in-phase signal and a digital quadrature signal to produce an analog output signal; and -sending the produced analog output signal.

For example, prior the amplitude or BPSK modulation, a preamble and a synchronization sequence is inserted at each start of frame and a CRC is inserted at the end of each block of data in each frame.

According to a third aspect of the invention there are provided computer programs and computer program products comprising instructions for implementing methods according to the first and/or second aspect(s) of the invention, when loaded and executed on computer means of a programmable apparatus.

According to a fourth aspect of the invention, there is provided a device configured for implementing methods according to the first aspect.

B

According to a fifth aspect of the invention, there is provided a device configured for implementing methods according to the second aspect.

According to a sixth aspect of the invention, there is provided a system comprising devices according to the fourth and fifth aspects.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the invention will become apparent from the following description of non-limiting exemplary embodiments, with reference to the appended drawings, in which, in addition to Figures 1 a and 1 b: -Figure 2 schematically illustrates a transmitter architecture according to embodiments; -Figure 3 schematically illustrates a receiver architecture according to embodiments; -Figure 4 is a flowchart of steps performed during encoding according to embodiments; -Figure 5 is a flowchart of steps performed during decoding according to embodiments; -Figure 6 illustrates a communication device according to embodiments.

DETAILED DESCRIPTION OF THE INVENTION

In what follows, embodiments of the invention are described.

Figure 2 illustrates a transmitter's architecture according to embodiments. For example, the transmitter may work at 220GHz.

The transmitter comprises a local oscillator 201 configured to generate an electrical sinusoidal signal. The signal may have a 110 GHz frequency for example. The transmitter further comprises a frequency doubling stage 202 configured to transform the signal from the local oscillator into a signal having two times the frequency of the signal output from the local oscillator (i.e. 220GHz in the present example). The signal output from the doubling stage is used for generating a signal carrier.

The transmitter further comprises mixers 203 and 208. Mixer 203 mixes the In-Phase component (I) obtained from a baseband modulator 206 (which receives the input bit stream) and the signal obtained at the output of the frequency doubling stage. Mixer 208 mixes the Quadrature component (Q) obtained from the baseband modulator 206 and a shifted signal. The shifted signal is output from a shifting bloc 204 which shifts the signal from the doubling stage by 90°.

The signals from the mixers 203 and 208 are summed by a summation bloc 205, which outputs a signal to a bloc 207 comprising a four stage low noise amplifier.

Figure 3 illustrates a receiver's architecture according to embodiments. For example, the receiver may work at 220GHz.

The receiver comprises a local oscillator 301 configured to generate an electrical sinusoidal signal. The signal may have a 110 GHz frequency.

The receiver further comprises a doubling stage 302 configured to transform the signal from the local oscillator at 110GHz into a signal having two times the frequency output from the local oscillator (i.e. 220GHz in the present

example).

The receiver further comprises mixers 303 and 304. Mixer 303 mixes a signal output from a bloc 306 comprising a four stage low noise amplifier (which receives the input signal, for example a 220 GHz RE signal) with a signal having a frequency equal to 220GHz output from the doubling stage.

Mixer 304 mixes the signal from bloc 306 with a shifted signal. The shifted signal is output from a shifting bloc 204 which shifts the signal from the doubling stage by 90°.

The signals from the mixers 303 and 304 are fed to a baseband demodulator 307, respectively on its In-phase and Quadrature inputs.

Thus, the transmitter has a TeraHertz transmitter module, with an In-Phase and a Quadrature components as inputs, and a digital modulator with a 1 bit digital to analog converter. The receiver node has a TeraHertz receiver and a digital demodulator with a 1 bit analog to digital converter.

The digital modulator applies on the bitstream, coming from the upper layer, a CRC encoding, a synchronization sequence adder, a preamble adder and a BPSK modulation. The In-phase samples of the signal obtained at the output of the BPSK modulator are duplicated to obtain the Quadrature samples. The In-phase and the Quadrature samples are given at the input of the I bit Digital to analog converter (i.e. each bit is converted into one sample).

The receiver has a terahertz receiver module and a digital demodulator with 1 bit analog to digital converter. The analog to digital converter obtains the "I" and "0" signals from the TeraHertz receiver module (having an heterodyne architecture) and applies a sampling equal to at least 3 times the sampling performed by the digital to analog converter of the transmitter. The two bit streams (i.e. corresponding to the "I" and the "Q" signals and called the "I" bit stream and the 0 bit stream) obtained from the output of the analog to digital converter are presented at the input of the digital demodulator. The digital demodulator performs a detection on the "I" bit stream and on the "Q" bit stream. The detection is based on the preamble sequence inserted by the digital modulator. If the detection step is successful then the digital demodulator applies a fine synchronization based on the synchronization sequence inserted by the digital modulator. The fine synchronization is performed on "I" and "0" bit streams by searching the "synchronization sequence" and also on the "inverted synchronization sequence". The "I" and "0" bit streams may be inverted due to the carrier frequency offset. Hence, four fine synchronizations are performed; the first on the I component, the second on the 0 component, the third on the inverted I component and the fourth on the inverted 0 component.. The digital demodulator applies a CRC decoding and a selection based on the CRC result to retrieve a correct bit stream.

Figure 4 is a flowchart illustrating an algorithm 400 performed according to embodiments, for example by the baseband modulator 206 of Figure 2.

The algorithm is performed for each packet to be transmitted. After the initialization step 401, a data bit stream splitting is performed during step 402 by dividing the M bits to be transmitted into N blocks of K bits. Next, during step 403, a Cyclic Redundancy Code is determined for each data block of K bits. Several Cyclic Redundancy Code types may be used, the following table summarizes some CRCs (see for example the Internet link CRC method Generator Polynomial Number of Bits CRC-32 X32+ X26+ X23+ X22+ X16+ X12+ X11+ X10+ x8÷ x7+ 32 x5+ x4+x2+ x+ 1 CRC-24 X24÷ X23+ X14+ X12-'-X8÷1 24 CRC-16 Xla÷Xi5+X2+1 16 Reversed CRC-16 X16+ X14+ X+1 16 CRC-8 X8+X'+X6+X4÷X2+1 8 CRC-4 X4+ X3+ X2+X+1 4 Generator polynomials for common Cyclic Redundancy Codes For each data block, having K bits, to be encoded a", the polynomial: a(x) = ak_i x + ak_i x + . . . + a1 xi + a0 is divided by the generator polynomial "g": g(x) = gri x + g1i x + ... + g xi + go and returns the remainder "d" : d(x) = d1i x + d1i x + ... + di xi + d0. The encoded data block is the concatenation of the data block "a" and the data block d".

Next, during step 404, a preamble insertion is performed for the packet detection at the receiver. The preamble is a known sequence and basically could be the following sequence: [11111000001111 100000...

1111100000 1111100000...

11111000001111100000...

1111100000 1111100000] During step 405, a synchronization sequence insertion is performed in order to determine the exact start of frame at the receiver. The synchronization sequence is a known sequence and basically could be the following sequence: [1011101011 10111010111 The BPSK modulation is performed during step 406 and the Quadrature component is generated from the In-Phase component: samples = -2.x(i) + 1 Qsampies = -2.x(i) + 1 Wherein: -x(i) is the i4h bit of the packet to be transmitted; -l_sample): is the In-Phase sample corresponding to the i-th bit; -Q_sample(i) : is the Quadrature sample corresponding to the i-th bit.

Next, the process goes to the encoding step 407.

Figure 5 is a flowchart illustrating the decoding process 500 applied by a receiver according to embodiments.

Step 501 is an initialization step. Next, during step 502, the I' and Q' samples are obtained from a one bit Analog-to-digital converter. Two parallel autocorrelation functions are separately applied to the In-phase samples and the Quadrature samples according to the following formula: AutoCorr(n) = J'4x(n + k).x(n + k -M), wherein -AutoCorr () is the autocorrelation function; -x(.) represents received samples (quantized with 1 bit); -N is the window wherein the autocorrelation is computed; -M is the period of the preamble sequence. In the preamble defined above the M value could be equal to 10 or a multiple of 10.

Next, during steps 505 and 506 a check is performed in order to determine whether a frame is detected. The check is separately performed on the autocorrelation of the I' samples and the Q' samples. If the verifications carried out during steps 505 and 506 are negative, then the process 500 ends.

If the verifications performed during step 505 is positive, steps 508 and 512 are performed in order to search, within the Q samples, for the synchronization sequence and the inverted synchronization sequence. The inverted synchronization sequence is defined as follows: [0 1000 10 100 0100010 10 0] If the verification carried out during step 506 is positive, steps 509 and 511 are performed in order to search, within the I' samples, for the synchronization sequence and the inverted synchronization sequence.

The search for the synchronization sequence and the inverted synchronization sequence can be done by a bit to bit comparison. The following formula can be used: SS(J) = L=1IxU + i) -Synch(i)I, wherein; -SS(j): is the function used to determine the start of the frame; i.e. if 55(k) = 0 then the synchronization sequence starts at the index k of x; -x(.) represents the received samples; -Synch) is the synchronization sequence (or the inverted synchronization sequence) as for instance defined above (see

bloc 405 description).

Next, during steps 510 and 516, it is checked whether the synchronization sequence (or the inverted synchronization sequence) is determined. In case it is determined, the BPSK demodulation is performed (steps 514 and 516).

A selection is performed during step 518 based on the CRC check in order to select the data blocks having no errors (the samples coming from I and o are identical hence thanks to the CRC bits one is able to select the data blocks from either I or Q samples..

With reference to Figure 6, there is described a transceiver 600 according to embodiments.

The transceiver comprises a processing unit 603 (CPU) which is connected to ROM unit 602 and a RAM unit 601.

The ROM unit contains a software program which, when executed by the CPU (using the RAM unit 601), makes the transceiver carry out a method according to embodiments. The software program can be designed based on the flowcharts of Figures 4, 5 and the present detailed description.

The RAM unit is configured to store data used during the execution by the CPU the software program and for the processing of other tasks performed by the CPU.

The CPU is connected to modules 604, 605 and 606 via a bi-directional address/data bus. For example, the CPU can initialize modules 604, 605 and 606 at system start-up using this connection.

Block 604 includes a block 610 configured to implement an algorithm as described with reference to Figure 4 for encoding data bit. Block 604 also includes a block 609 configured to implement an algorithm as described with reference to Figure 5 for the decoding.

The transceiver further comprises a CPU interface 605 configured to process the data packets received from the Radio packet receiver 608 and the packets to be transmitted to the radio packet transmitter 608.

The data packets are stored in a memory unit 606 before/after encoding/decoding.

Blocks 607 and 608 respectively correspond to the controllers that transmit and receive data samples from, respectively, the RF transmitter 611 and the RF receiver 612. The transmitter and the receiver are respectively described with reference to Figure 2 and Figure 3.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive, the invention being not restricted to the disclosed embodiment. Other variations to the disclosed embodiment can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings] the disclosure and the appended claims.

In the claims, the word comprising" does not exclude other elements or steps, and the indefinite article a" or "an" does not exclude a plurality. A single processor or other unit may fulfil the functions of several items recited in the claims. The mere fact that different features are recited in mutually different dependent claims does not indicate that a combination of these features cannot be advantageously used. Any reference signs in the claims should not be construed as limiting the scope of the invention.

Claims

CLAIMS1. A signal processing method, the method comprising: -receiving an analog input signal; -performing l/Q demodulation on the analog input signal thereby obtaining an analog in-phase (I) signal and an analog quadrature (Q) signal; -digitizing the analog in-phase signal and the analog quadrature signal thereby generating, respectively, a digital in-phase signal and a digital quadrature signal; and -forming a reconstructed digital signal from the digital in-phase signal and the digital quadrature signal wherein each block of data of the reconstructed digital signal is obtained from one of a block of data in the digital in-phase signal and a corresponding block of data in the digital quadrature signal.
2. A method according to claim 1, wherein the digital in-phase signal and the digital quadrature signal are representative of data frames, each frame containing a preamble sequence for detecting the start of the frame and a plurality of blocks of data.
3. A method according to claim 2, wherein each frame further contains a synchronization sequence enabling determining if the frame needs to be inverted, by performing a cross correlation with a predetermined synchronization sequence.
4. A method according to claim 3, wherein: -the block of data that is obtained for forming a given frame of the reconstructed digital signal is selected among one of a block of data in a first frame and a corresponding block of data in a second frame based on the number of errors detected therein, and wherein -the first frame corresponds to: * a frame of the digital in-phase signal if a correlation exists between the synchronization sequence of the frame and the predetermined sequence, and to * an inverted frame of the digital in-phase signal if a correlation exists between the synchronization sequence of the frame and an inverted version of the predetermined sequence; and wherein -the second frame corresponds to * a frame of the digital quadrature signal if a correlation exists between the synchronization sequence of the frame and the predetermined sequence and to * an inverted frame of the digital quadrature signal if a correlation exists between the synchronization sequence of the frame and an inverted version of the predetermined sequence.
5. A method according to claim 4, wherein the block of data selected is the block of data that contains a minimum number of errors.
6. A method according of claim 5, wherein the existence of errors is checked using a cyclic redundancy code.
7. A method according to claim 1, wherein a BPSK demodulation is performed prior to the forming step for generating the in-phase and quadrature bit-stream.
8. A signal processing method, the method comprising: -performing amplitude or BSPK modulation of a digital sequence thereby obtaining a digital signal, -duplicating the digital signal into a digital in-phase signal and a digital quadrature signal; -performing l/Q modulation on the digital in-phase signal and a digital quadrature signal to produce an analog output signal; and -sending the produced analog output signal.
9. A method according to claim 8, wherein, prior the amplitude or BPSK modulation, a preamble and a synchronization sequence is inserted at each start of frame and a CRC is inserted at the end of each block of data in each frame.
10. A signal processing device, the device comprising: -a receiving unit configured to receive an analog input signal; -a processing unit configured to perform l/Q demodulation on the analog input signal thereby obtaining an analog in-phase (I) signal and an analog quadrature (Q) signal, to digitize the analog in-phase signal and the analog quadrature signal thereby generating, respectively, a digital in-phase signal and a digital quadrature signal; and to form a reconstructed digital signal from the digital in-phase signal and the digital quadrature signal wherein each block of data of the reconstructed digital signal is obtained from one of a block of data in the digital in-phase signal and a corresponding block of data in the digital quadrature signal.
11. A device according to claim 10, wherein the digital in-phase signal and the digital quadrature signal are representative of data frames, each frame containing a preamble sequence for detecting the start of the frame and a plurality of blocks of data.
12. A device according to claim 11, wherein each frame further contains a synchronization sequence enabling determining if the frame needs to be inverted, by performing a cross correlation with a predetermined synchronization sequence.
13. A device according to claim 12, wherein: -the block of data that is obtained for forming a given frame of the reconstructed digital signal is selected among one of a block of data in a first frame and a corresponding block of data in a second frame based on the number of errors detected therein, and wherein -the first frame corresponds to: * a frame of the digital in-phase signal if a correlation exists between the synchronization sequence of the frame and the predetermined sequence, and to * an inverted frame of the digital in-phase signal if a correlation exists between the synchronization sequence of the frame and an inverted version of the predetermined sequence; and wherein -the second frame corresponds to * a frame of the digital quadrature signal if a correlation exists between the synchronization sequence of the frame and the predetermined sequence and to * an inverted frame of the digital quadrature signal if a correlation exists between the synchronization sequence of the frame and an inverted version of the predetermined sequence.
14. A device according to claim 13, wherein the block of data selected is the block of data that contains a minimum number of errors.
15. A device according of claim 14, wherein the existence of errors is checked using a cyclic redundancy code.
16. A device according to claim 10, wherein a BPSK demodulation is performed prior to the forming step for generating the in-phase and quadrature bit-stream.
17. A signal processing device, the device comprising: -a processing unit configured to perform amplitude or BSPK modulation of a digital sequence thereby obtaining a digital signal, to duplicate the digital signal into a digital in-phase signal and a digital quadrature signal, to perform IIQ modulation on the digital in-phase signal and a digital quadrature signal to produce an analog output signal; and -a sending unit configured to send the produced analog output signal.
18. A device according to claim 17, wherein, prior the amplitude or BPSK modulation, a preamble and a synchronization sequence is inserted at each start of frame and a CRC is inserted at the end of each block of data in each frame.
19. A signal processing system comprising -a first device according to claim 17 or 18 for sending signals, and -a second device according to any one of claims 10 to 16 for receiving signals fro said first device.
20. A computer program product comprising instructions for implementing a method according to any one of claims 1 to 9 when the program is loaded and executed by a programmable apparatus.
21. A non-transitory information storage means readable by a computer or a microprocessor storing instructions of a computer program, for implementing a method according to any one of claims 1 to 9, when the program is loaded and executed by the computer or microprocessor.
22. A device substantially as hereinbefore described with reference to, and as shown in, Figures 2, 3 and 6 of the accompanying drawings.
23. A method substantially as hereinbefore described with reference to, and as shown in, Figures 4 and 5 of the accompanying drawings.