GB2521162A - Plasma-deposited polymer-like carbon dielectric having a high breakdown field strength and low leakage current - Google Patents

Abstract

A polymer like carbon dielectric (PLCD) is deposited on a substrate by plasma enhanced chemical vapour deposition (PECVD) at a temperature of < 200°C. The dielectric is derived from a gas mixture of hydrogen and a hydrocarbon, preferably acetylene, and preferably another gas. The dielectric is preferably an encapsulating, gate dielectric of an organic thin film transistor (OTFT). An exemplary device comprises a glass substrate 3, aluminium, patterned gate electrode 5 (thermal evaporate through a shadow mask), 450 nm thick, PLCD 7 (formed from 100 sccm H2 and 20 sccm C2H4 at 900 mTorr (120 Pa) using 13.56 MHz radio frequency source at 40 W), patterned source 9S and drain electrodes 9D (formed by thermal evaporation and modified by PFBT), defining active channels 10, and a semi-conducting layer 11 (formed by drop casting TIPS-pentacene and PS).

Description

PLASMA-DEPOSITED POLYMER-LIKE CARBON DIELECTRIC HAVING

&liie&.flREAKDOWN FIELD STRENGTH AND LOW LEAKAGE

CURRENT

The present invention relates to a polymer-like carbon dielectilc (PLGD) having a ow leakage current and high breakdown field strength, that is g-own at ow temperature b means of plasma-enhanced chemical vapour deposition (PECVD), and the use of such dielectric in structures, such as in solution-processed organic thin-flm trdnsistors (OTFTs) as the gate dielectric or as a physical barrer for chemical protection from the environment.

OTFTs have attracted considerable attention owing to their potential application in low-cost, large-area and flexible electronics, such as radio frequency identification (RFID) tags, sensors, and backplanes for electrophoretic and organic light-emitting diode (OLED) displays.

Significant efforts have been made to develop orgaric semiconductor materials which exhibit high carrier mobility and are also chemicafly and physically stable, with the reported device performance of OTFTs already far beyond that of amorphous silicon devices. In addition, there has been intense research into the development of suitable gate dielectric materials, being another critical component for OTFIs.

Commonly used gate dielectric materials for OTFTs include silicon nitride (SiN) and slicor oxide (SiO,), stemming from tneir high stability and electrical insulating characteristics. These dielectrics are commonly deposited by PECVD, However, high substrate temperatures of up to 300 °C arétiSuálly i dtéd f achieving films of th hihCSt quallt$ These too hip fc-lowwts: S thSt3teS SUth as P!*S:Sfle., die extpemEJy dangerous silne gas uSEd in these diClectrics repn its a very $erkCus flføt hiZard, n!qufrtng expensive Infrastructures for handling the silarte gas, which are u vited to low-cost production fad Ilties; It is thus an a3rn of the present invention to: provTde: PLC that are grown by PECVD, and can be used In the manufcture of so$ütion processed or evaporated OTFTS, in particular as gate and/or barrier dIelectrics which allows for application with lower-cost, flexible and/or heatserislt1ve substnt suchas plastIcs materlaS In one aspect the present invejition prGvides a method of depositing a lmer-!i carbon dled* (pD), the method çq prising the çp of provldng a gas n$ictin of hydrogen and at leflt one hydrocarbon gas, and ieo&dhg a laer of Ltb by plasma-enhanced cheSi yapor depo*I at a temperature of less than 2OO °C.

In another asld the pres invention: provides a polymer-like carbort dletettrit (PLCDr3 film fabritated frornagas mixture ofhyro H and at least one drO$tO* gas by plastia'-eflhahted theflhltal Etpbf dEpOSitiCfl at a temperature of less than: ZOO °C.

in a further aspeCt! the; present invention provides a structure; Incorporating the Sbotdëcribed dielectric, optionally ar organic thin-film transistoç: optlonafly fabricated on plastics, flexibte arid/or heabsensltfre substrates.

In a stifl further aspect the present invention provides an organic thin film transistor, comprising: a substrate; a gate electrode deposited on the substrate, a gate thelectnc depos ted on the gate dectrode, wherein the gate di&ectric is the above-described PLCD; source and drain electrodes deposited on the gate dielectric and defining an active channel therebetween; and a semi-conducting layer deposited over the exposed gate dielectric at the active channel.

In a yet further aspect the present invention provides an organic thin film transistor, comprising: a substrate; a gate electrode deposited on the substrate; a gate dielectric deposited on the gate electrode; source arid drain electrodes deposited on the gate dielectric and defining an active channel therebetween; a semi-conducting layer deposited over the exposed gate d'e'ectric at the active channel, and a barrier dielectric which encapsulates Ihe transistor to provide a physical barrier to environmental factors, such as moisture and oxygen, wherein the barrier dielectric is Lhe above-described PLCD, The present invention provides low-vozage (<5 V) OTFTs with a mobility of about 1 2 cm2/(Vs) and extremely low gate leakage current (<10 2 A), using an established PEOID deposition technology. The eco-friendly, carbon-based PLCD shows a very smooth and low trap density surface due to the high nydrogen content present in the films (up to 50%)" and the high-pressure and low-power deposition corditions, which allow for low ion-damage to the growth surface, thereby achieving low plasma modification to the lattice, Additionally, the films are chemically, physically and mechanically stable More importantly, the low-temperature processed dielectric provides strong insulating characteristics and compatibility with -3.-.

most organic solvents, aUowing for excellent process compatibility with, for example, the production of TIPS-Pentacene based OTFTs, and aflows for processing at temperatures of not more than ioo oct which is suitable for processing on cheap flexible substrates.

Preferred embodiments of the present invention will now be described herein below by way of example only with reference to the accompanying drawings, in which: Figure 1 illustrates schematically the bottom-gate bottom-contact (BGBC) device structure of an OTFT in accordance with a first embodiment of the present invention; Figure 2 illustrates crystallization of the semiconductor layer across the active channel of the device structure of Figure 1; Figure 3 illustrates an atomic force micrograph (AFM) image of the surface of the PLCD film of one device structure of Rgure 1, Figure 4 illustrates a glancing-angle X-ray diffraction trace of the PLCD film of one device structure of Figure 1; Figure 5 illustrates a transmission electron micrograph of the PLED film of Figure 1; Figure 6 illustrates a Fourier transform infrared (FTJR) absorption spectrum from the PLCD film of one device structure of Figure 1; FIgure 7 1llUSfrté Ieaitge current derity of the PLO nirn of one dewte sttttLttt(Al/P1XD/A4) Of F14flE I, Wlthc the Sëtflltdfldik ct lay; Figure 8 WuSt*tes ieä*age tUfrent dePa Of the PLcD flit of: e;ght 1è structues (:AIIPLQWA9) of Flguçe 1, without the semlonductor layer; Figure 9 hlust siàkage cutrent density as function ofthe electrk field applied to the PLCD film of one devite structure (ALflSCO/Ac) of Figure 1, without the seMiconductor layeç where repeated 20 times ovàr a 90 Sin ute Mterval; FIgure 10 illustrates the dielectric constant k and loss of the PLO film of the dEMbe bf Figure 1 as f(ffi[ Of 1flSUtèd fre4Uéflty figure ii lfluflrates transfer c$acfls o the mm of us device Figure 12 fflustràtes transfer charac ristics of the Pitt. film of five device 1; structures of Figure 1; F14Uh 13 Illustrates output thatacteristics of tilt PLCD film of one devIce: SttutttreOfFlqurel; ! " sJ'fl!cfflY an QTPT I!!. aW4u! with, 0f lre p'et mn1tb0n and R9üre 1$ Illustrates schematicalhr an OTF1: In accordance with a thIrd embodiment of the present InvenUon Figure 1 Hustrates the bottom-gate bottom-contact (BGBC) device structure of an OTFT in accordance with a first embodiment of the present invention.

The device structure comprises a substrate 3, patterned gate electrodes 5 deposited on the substrate 3, a gate dietectric 7 of a polymer-like carbon dielectric (PLCD) fllm, in this embodiment an amorphous carbon, deposited on the gate electrodes 5, patterned source and drain electrodes 9 S, D) deposited on the gate dielectric 7 and defining active channels 10 tlierebetween, anc a sem-conducting layer 11 deposited over tne exposed gate dielectric 7 at the active channels 10 and the source and drain electrodes 9.

The present invention will now be described with reference to the following non-limiting Example.

Example

In this embodiment the substrate 3 is a glass substrate. In other embodiments the substrate 3 could, for example, be a plastics or heat-sensitive substrate, and could be flexible.

In this embodiment the substrate 3 was cleaned in an ultrasonic bath at 50 0C with detergent solution (20 minutes), deionized water (10 minutes), acetone (20 minutes) and isopropanol (20 minutes), respectively.

Subsequertly, the gate electrodes 5 were deposited on the substrate 3, in this embodiment by thermal evaporation and through a shadow mask.

In this embodiment the gate electrodes 5 are formed of aluminum, and have a thickness of 40 nm.

Subsequently, the PLCD film of the gate dielectric 7 was deposited on the gate electrodes 5.

In this embodiment the PLCD film forming the gate dielectric 7 was depositea from hydrogen (100 seem) and acetylene (20 sccrn) gases at a pressure of 900 mTorr, using a plasma enhanced chemical vapour deposition (PEOJD) system, here a Model 1000N PECVD system from Surrey NanoSystems (Newhaven, UK), using a 13.56 MHz radio frequency (if) source at an rf power of 40 W for plasma exatation to the substrate (lower) electrode.

In this embodiment a low substrate self-bias of 20 V was used) together with the relatively high process pressure of 900 mTorr, in order to reduce the ion mean free path and minimise damage by ion bombardment at the PLcD film of the gate dielectric 7.

In this embodiment the PLCD film of the gate dielectric 7 has a thickness of 450 nm. The thickness of this film is controlled by the duration time of the deposition.

In this embodiment tile PLCD film of the gate dielectric 7 provides sufficiently-strong solvent orthogonality to allow for deposition of the later-deposited solution processed semiconducting layer 11.

In this embodiment the substrate 3 was supported on a substrate table which was maintained at room temperature by means of a water-cooling arcuit Ths cooling, together with the use of a ow if power, maintained the device structure at room temperature Subsequently, a film forming the source (5) and drain (D) electrodes 9 was deposited on the PLCD film of the gate dielectric 7, in this embodiment by thermal evaporation, and through a shadow mask to define the active channels 10 between the electrodes 9.

In this embodiment the film forming the source and drain electrodes 9 has a thickness of 60 nm, and the active channels 10 have a width of 1200 jm and a length of 60 pm.

The source and drani electrodes 9 weie then modifled to reduce the contact barrier between the electrodes 9 and the acWe layer to be subsequertly deposited, in this embodiment by immersing in a 5x103 mol'L1 solution of perfluorobenzenethiol (PFBT) (Aldrich, UK, used as received) in ethanol for 2 minutes, and rinsing with ethanol Subsequently, the semiconducting layer 11 was deposited, in this embodiment by drop-casting from a solution made by mixing 6,13-bis(triisopropylsflylethynyl)-pertacene (TIPS-pentacene) and polystyrene (PS) at 10 gL4 concentraton of solids in chloroberzene (3 1 rato by volume). The drop-casting process was carried out with a micro-syringe.

The resulting device structure was then annealed, in this embodiment at t for 30 minutes, and in a nitrogen environment. Figure 2 illustrates crystallization of the semiconductor layer 11 across the active channel 10.

Electrical properties of the device structure were characterized using a Keithley 4200 system from Keithley Instruments (Bracknell, UK).

Capacitance measurements were performed with a WKE 65008 impedance analyzer form Wayne Kerr Europe (Herner, Germany). Surface roughness was measured using a Nanoscope Dir'ension 3100 atomic lorce microscope from Veeco (Plainvile, USA). Glancing angle X-ray diffraction (GAXRD) was performed using a PANalytical X'pert Pro instrument from PANalytical (Almelo, The Netherlands) Tiansmission electron microscopy (TEM) was performed by growing the PLCD film on a mica substrate, followed by lift-off using water. Fourier transform infrared spectroscopy was performed using a Protégé 460 system from Nicolet Technologies (Cambridge, UK). The eakage current density and dielectric constant tests were performed immediately after patterning the source and drain electrodes 9. All rr,easurements were perforned at room temperature and in air Atomic force micrograph (AEM) analysis of the PLCD film of the gate delectric 7 is illustrated in Figure 4 The AFM image reveals a root-mean-square (RMS) roughness of 03 nm and peak-to-peak roughness of 2.56 nm across a 500 nm square size scan areaS This represents a very smooth surface, which enables a good semiconductor-insulator interface.

Figure 5 illustrates the glancing angle X-ray diffraction (GAXRD) trace from the PLCD film of the gate dielectric 7, which reveals no distinct peaks, providing an indication that the PLCD film is amorphous.

Figure 6 iHustrates the electron beam diffraction pattern obtained by transmission electron microscopy (TEM) of the PLCD ifim of the gate dielectric 7, which reveals no evidence of sharp spots or ring structures, again providing an indication that the PLCD film is amorphous.

Figure 7 illustrates a Fourier transform infrared (FTIR) absorption spectrum from the PLC.D film of the device structure, indicating the more prominent bands associated with the chemical bonding of the dielectric. The spectrum shows significant amounts of sp3 hybridised carbon atoms that are covalently bonded to hydrogen (stretching bands from 3000-2750cm 1), and very low amounts of sp2 carbonhydrogen bonds (stretching 3250cm 1), which indicates a bonding configuration typical of a highly insulating film.

In this embodiment the dielectrc 7 is estimated to have aoJt 10''16 paramagnetic defects per cubic centimeteç which is a scale of defects five orders of magnitude ower than existing carbon structures, for example, in non-hydrogenated carbon structures which is about 10A21 paramagnetic defects. In preferred embodiments the dielectric 7 is estimated to have less than 1O"lB paramagnetic defects per cubic centimeteç optionally less than 1017 paramagnetic defects per cubic centimeteç more optionally less than i0i6 paramagnetic defects per cubic centimeter.

Leakage current density and dieiectric constant measurements were performed on device structure, in order further to test the insulating characteristics of the PLCD film.

-10 -AS illustrated in Figure the breakdown strength S. the PLCD film of gate dlelet:it, 7 15 hIgher than 44 Mvfcm (± 200 V), afld the leakage turn nt density tah be kept at a low FEel (<10' Ntflit) before breakdown, Which IS thttb1 With Other PECVD dleletttlc mateilals fabricated using high terflpertth'e pQfl4 ff14 re:8 ill*trates the uniformity or the p' film of the gate dielectrIc 7, as meas, frq eight devIce, on ate s:smple.

Figure 9 illustrates the stability of the PLC:D film of the?gate dielectric: 7, as measured from one device when swltthed tweflty times over a: 90 n*iute fritervaj, FIgure 10 illustrates the dielectric constant and the dMèctrlà loss tthe PLC'D film of the gate dIet tr. 7 as a function of measurement freqtency ?fl% k?value is about 32 in a low frequent: range which Is suited to; carder ti"ñsØort bfrJ''5' i h1ghk ielett'it: will ":" en the trap dhSIt Of stStes': at ti st,,'#qreisfrk tntefati by the ftirin;'ed dipole dlSotdEr Furthermore, the Lqj ij P1*O4 at high qp; 106 Ht Figures 11 to iS Illustrate reasured electrical cha,,, ,istfrs, of the 4iv,,, :sfruthj The transfer curve in Figure ii illustrates transistor characteristics with a high onfoff ratio (1O a small Subthteshold fSWlfl9 ($S (170 mV/:decade) and he:' liØibIé hysteresIS. Tti& negligible hysteresis ocSrs as a result of a trap-free °tt,,: Pçp Is a facet of the bulk of the dielectric" being trap free; No swäqe treat,,, fl was applied to the dHeiit *1'S at any stage in the fabrication process and the trapfree charai,','ePlstlP of the dleledrt thus results ftqrnthe deposltltwr process.

me t t cure in Figure ii Indicates good hole injea on from the drain eiecUe 9 to tlw hlgttest occupied molecular orbital (P40MG) level of the semkondtittorlayer ii, since no S-shape is observed at small voltages.

Figwe 12 Wan: ta the uniformity df the gate leakage, as mesajrS from five devices On one satn*le Wt$e the gfl. Is kage rsm$nstØw, * about IrA.

The field-effEct moblflty of the semiconductor was e4ra4ted from the satorauan rerne according to Equátiin (E, jtC,W $ I: WhtE I itthE Sathilited draih thit, VGg IS thE Oltd 14 S te threshold vP!, L is the liQthtf the *4tNe ChSthél IC), W Is thE width 0 the ac*ive channel W and Ca I thegat:e $1c cap rl$ per unit area.

The mobWty p was found to: be 1.2 cm2/(:Ms) with a threshold voltage oft- 1.3 V. Importantlyj the operattng v&tae ofthe device S down to 5 V; low pther consumptloti being an important parameter for the use of OTFTs ht may ap iitauôns1 The key of reaftzlhg low-yOliP opetãtipn 1$ tO. deptas e skS teJol4 swing 55 The ctassIaJ subthreshold swing $5 epr ssiOn: developed fcc a met -oxiderser Iccndutór fleld.'effed transistor (MC PET) Is described by Equation (:2 ss = ml kbi (1+ q C0 (2) where kb is the Boltzmann coefficient, q is the electron charge, I is the absolute temperature, C is the gate dielectric capacitance per unit area, and Cb is the effective channel capacitance, which is a sum of the depletion capacitance Ccep and capacitance related to the charging of the semiconductor-dielectric interface traps C. Although Equation (2) was originally developed for inversion-mode MOSFETs, it is also a good approximation for accumulation-mode devices, and thus

suitable for OTFTs.

According to Equation (2), ow opetating voltage can be achieved by either increasing the gate dielectric capacitance per unit area C or decreasing the effective channel capacitance CCh To date, significant efforts have been devoted by others to increasing the gate dielectnc capacitance per urit area C, by using ultra-thin films or high-dielectric-constant (high-k) films.

The present inventors have instead developed an OTET with a low operating voltage by not relying on a large gate dielectric capacitance CG, but decreasing the effective channel capacitance Ch. In this way, there is significantly improved processing flexibility, since neither the thickness nor a high-k value of the PLCD film of the gate dielectric 7 are required.

In this embodimeit, the gate dielectric capacitance C, is found to be only 6S5 nF/cm2 (k=3.2), which is much smaller compared with existing device structures (600 nF/cm21 and 330 nF/cm220). Furthermore, a low operating voltage down to 5 V is also achieved, with a ow subthreshoid swing SS of mV/decade. Such a low subthreshold swing in combination with a low gate dielectric capacitance CG indicates a low value of effective channel capacitance Ch, namely, few semiconductofrdielectric interface traps and bulk traps in the active channel 10.

Accordingly, the present inventors have, for the first time, demonstrated the room temperature fabrication of a gate dielectric 7 for a BGBC device architecture using an industry-staidard PECVD process, which yields good transistor behaviour, rarely, low dielectric capacitance, low operating voltage, low 55 and low gate dielectric capacitance, thereby enabling use in industrial applications. The room-temperature and large-area deposition capabilities of this dielectric material, together with its highperformance insulating and ideal trap-free surface characteristics, render the structure suitable for commercial production The developed BGBC device architecture with low temperature processing (S 100 °C) allows for the development of low voltage organic integrated circuits on cheap plastic substrates.

Figure 14 illustrates schematically an OTFT in accordance with a second embodiment of the present invention.

In this embodiment the device structure is fabricated as per the first-described embodiment, dnd additiondlly includes a bamer structure 101 which comprises a dielectric barrier layer 103 of a polymer-like carbon dielectric (PLCD), fabricated in the same manner as the first-described embodiment, which encapsulates the transistor to protect agahist the ingress of environmental factors, such as moisture and oxygen, from the ambient environment.

In this embodiment the structure 101 comprises at east one additional buffer or planarization layer 105, here first and second buffer or planarization layers 105, which sandwich the barrier layer 103.

In this embodiment the at least one buffer or planarization layer 105 is formed of a polymer, such as parylene.

In an alternative embodiment a plurality of barrier layers 103 could be incorporated, sandwiched between a plurality of buffer or planarization ayers 105 Figure 15 illustrates schematically an OTFT in accordance with a th'rd embodiment of the present invention.

in this embodiment the device structure comprises an OTF here having a metal oxide gate dielectric fabricated at low temperature, optionahy at room temperature, and additionally includes a barrier structure 101 which encapsulates the transistor to protect against the ingress of environmental factors, such as moisture or oxygen, from the ambient environment.

In this embodiment the barrier structure 101 comprises a plurality of dielectric barrier layers 103 of a polymer-like carbon dielectric (PLCD) fabricated in the same manner as the first-described embodiment, and a puraUty of buffer or panarization iayers 105 which sandwich the barrier ayers 103.

In this embodiment the buffer or planarization ayers 105 are formed of a poymeç such as paryene.

Finafly, it wifl be understood that the present invention has been described in its preferred embodiments and can be modified in many different ways without deparung from the scope of the nventwn as defined by the appended daims.

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Claims (9)

1. A method of depositing a polymer-like carbon dielectric (PLcD), the method comprising the steps of providing a gas mixture of hydrogen and at least one hydrocarbon gas, and depositing the PLCD by plasma-enhanced chemical vapor deposition at a temperature of less than 200 CC.

2 The method of claim 1, wheren the dielectric has a thckness of from nm to 1000 nm.

1. The method of claim 2, wherein the dielectric has a surface roughness of less than 1O% of the thickness of the dielectric, optionally less than 5% of the thickness of the dielectric.

4.. The method of any of claims 1 to 3, wherein the dielectric has a root-mean-square surface roughness of less than 1 rim, optionally less than 0.5 rim.

5. The method of any of claims 1 to 4, wherein the hydrogen and the at least one hydrocarbon gas are provided in a volume ratio of from gg:ltoso:so.

6.. The method of any of claims 1 to 5, wherein the hydrocarbon gas is acetylene

7. The method of any of claims I to 6, wherein the gas mixture further comprises at least one further gas, optionally helium, argon or -19 -nitrogen.

8. The method of any of claims I to 7, wherein the dielectric is deposited using a power of from 0.1 to 10 W/cm2.

9. The method of any of cliams I to 8, wherein the dielectric is deposited using a selfbias of less than 50 V. The method of any of daims 1 to 9, wherein the dielectric rs deposited at a pressure of at east 100 mTorr, optionafly at east 500 mTorr, optionafly at least 750 mTorr 11. The method of any of claims 1 to 10, wherein the dielectric is subjected to no surface treatment.12 The mettiod of any of claims 1 to 11, wherein the depositoi is at a temperature of less than 100 °C, optionally at room temperature! 13. The method of any of claims 1 to 12, wherein the dielectric has a breakdown strength greater than 1 MV/cm, optionally greater than 2 MV/cm, optionally greater than 4 MV/cm.14. The method of any of claims 1 to 13, wherein the dielectric has a dielectric loss of less than 0.1 at frequencies up to 106 Hz.The method of any of claims 1 to 14, wherein the dielectric is incorporated in a structure, optionally a solution-processed organic thin-film transistor, optionally fabricated on a plastics, flexible and/or -20 -heat-sensitive substrate.16. The method of claim 15, wherein the dielectric is a gate dielectric of an organic thin-film transistor.17. The method of claim 15, wherein the dielectric is a dielectric barrier layer of an organic thin-fiim transistor which encapsulates the transistor to provide a moisture barrier, optionally a gate dielectric of the transistor is a metal oxide.18. The method of claim 1], further comprising the step of providing a buffer or planarization layer adjacent the barrier layer, optionally providing first and second buffer or planarization layers between which the barrier layer is sandwiched.19. The method of claim 18, wherein the transistor comprises a plurality of dielectric barrier layers sandwiched between a plurality of buffer or planarization layers.20. A polymer-like carbon dielectric (PLCD) film fabricated from a gas mixture of hydrogen and at least one hydrocarbon gas by plasma-enhanced chemical vapor deposition at a temperature of less than °C.21. The film of claim 20, wherein the film has a thickness of from 10 nm to 1000 nm.22. The film of claim 21, wherein the film has a surface roughness of less -21 -thn LO of the thkkness of the film,. op&naliy less than 534 of the thb*nesstthe film.23. Theffilm Of any of claims ao to 22, wherein the film has a root-mean-square surface roughness of less than 1 nm, optionally less than 03 nm.24:, TIle film of any ofctajrs 20 to 23, whereIn tI* hydrpgen *ii the at least one lwdrocrbqn ga are prided in volume raUo of from g9; to 5;5Q.*1 a t: film of any el éiatms O to 24, wherein the hydi'ocatho, gas is 26. Of any of claims zo to 25r wherein the gas mi9ure further offlrlsCs at least os futthr gas option lI helium. aigovi or rrp9eh.27. The fIlm, any of cLaims 20 to 26, wherein; the; ffltn IS deposked using a power of from 0.1 to 10 W/cm2.28. the film ofany ofdiims 20 to, 27, wherein the film is dèposltid using aseif-blasfnfiessthan5OV.* me nir"o any of' tiants 20 tO 28, Whertfl the film Is tleptsited at a pressw* or at least: QP rnibrt PtiQt1&IY at least 500 mTorr option$y at least 750 mTort The film of any of claims 2b to 2 wherein the film issubjectedto no surfice treatment.31 The filmtt of any ofdaims 20 to 30, whetelrt the film is fabricated at a temperature of lessthan 100 °C', optionally at room temperature.3Z The film of any *1 claimS' 20 tO 3t, wbe?elPthEi'ft,l,Pl h F strength greater than 2 MV/cm, o*tionally greater than 2 MV/cm,, optionally greater than 4 MV/tnt fl The film of S cfl daiS 20 to 3Z' wheretn the, fin has, a dIelectric loss of lessthan (Li at frequendes up to itit 34 A structure Incorporating thefllm of any of d&ms20 to 33, optionally S&uUoEi-piotEssed S'ganlt thfl-fiFm tfaflSiSt optionsiy fabricated on plastkS, flexible ahd/Or he"t-sri"'sltwe'stibstRtt 3$ The, structure of claim $, wherein tJ,,e fH!,, is a gate, J4:,I, of a organic ttiln4ilm'Sns&or t The: structtire of claIm 34, whereIn the:fiirn: Is a dielectric barrier, layer of an organic thin-film transistor which encapsulates the translstorte provide an environmental barrler,suth as fo-moisture and oxygen1 3?. Th'*tthO'e Of claim 36, fUthê? cbn,ØflSiilg a b"" 0? plartatf2auofl' Layer adjace,,it the barrier Iayejj 0ptjØraUy first and second bU,,Wør pianarlzatton layers between which Ø barrier layer! sanøwiS,,øi 23r 38. The structure of claim 37, wherein the transistor comprises a plurality of dielectric barrier layers sandwiched between a plurahty of buffer or planarization layers.39. An organic thin film transistor, comprising: a substrate; a gate electrode deposited on the substrate; a gate dielectric deposited on the gate electrode, wherein the gate dielectric is the PLCD of any of claims 20 to 38; source and drain electrodes deposited on the gate dielectric and defining an active channel therebetween; and a semfrconducting layer deposited over the exposed gate dielectric at the active channel.An organic thin film transistoç comprising a substrate, a gate electrode deposited on the substrate, a gate dielectric deposited on the gate electrode, source and drain electrodes deposited on the gate dielectric and defining an active channel therebetween; a se-u-conducting layer deposted over the exposed gate dielectric at the active channel; and a barrier dielectric which encapsulates the transistor to provide an environmental barrier, such as for moisture and oxygen, wherein the barrier dielectric is the PLCD of any of claims 20 to 38 41 The transistor of claim 40, wherein the gate dielectric of the transistor is a metal oxide.42. The transistor of any of claims 39 to 41, wherein the source and drain electrodes are deposited by thermal evaporation or solution processed.43. The transistor of any of claims 39 to 42, wherein the semiconducting layer comprises a pentacenebased layer, optionally comprising 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) and polystyrene (PS).44. The transistor of any of claims 39 to 43, wherein the semiconducting layer is deposited at a temperature of less than 200 °C, optionally less than 100 °C optionally at room temperature.45. The transistor of any of claims 39 to 44, wherein, subsequent to deposition of the semiconducting layer, the structure is annealed at a temperature of at least 100 °C.46, The transistor of claim 45, wherein the structure is annealed for at least 10 minutes.47. The transistor of any of claims 39 to 46, wherein the transistor has an on/off ratio of at least io.48. The transistor of any of claims 39 to 47, wherein the transistor has a subthreshold swing (55) of less than 200 mV/decade and substantially no hysteresis.49 The transistor of any of claims 39 to 48 wherein the transistor has;an opsrating voftage of less thafl*about sy;