GB2518716A - Serial data bus - Google Patents

Abstract

A controller for a two-wire serial bus comprises phase modulator to convert n bits of data into a phase position for a first edge of a signal to be transmitted on the bus (i.e. raising or falling) and a phase demodulator to decode n-bits of data in a second opposite edge of a signal received from the bus. For example, when the controller is a master, it drives the rising edge, while if it is a slave it drives the falling edge. A break code is used for synchronization. The controller has a bus driver comprising first and second push-pull arrangements and configured to convert a received signal into power delivery to the controller. The controller provides galvanic isolation via the use of transformers. The controller can be used for clock distribution. Serial buses comprise inter integrated circuit, I2C, serial peripheral interface, SPI, RS-485, Controller Area Network, CAN, and Profibus (RTM).

Description

Serial data bus

Field of the Invention

The present invention relates to a serial data bus.

Background

For industrial electronic systems, there are many interface options for chip-to-chip data communications, such as Inter-tntegrated Circuit (t2C), Serial Peripheral Interface (SF1), RS-485, Controller Area Network (CAN), Profibus etc. However, most of these buses do not provide any galvanic isolation and so additional digital isolators are required. Furthermore existing chip-to-chip isolated datalinks suffer one or more drawbacks.

First, many existing isolation systems are comp'ex and costly. For exampk, a micro i transformer isolator requires, for the SF1, four transformer channels (three for data and one for power transfer) and also two integrated circuits (ICs), one on each side of the isolation barrier co-packaged with the magnetic components. A capacitive isolator has a similar level of complexity as a micro transformer and has the added drawback of an inability to transfer power. In existing isolator systems, each slave node requires its own isolator IC.

Secondly, reliability can be an issue, partic&arly in four-or five-wire systems (when power distribution wires are included) even without differential signalling.

Thirdly, performance can be an issue. Existing systems are generally limited to less than 20 Mbps on SF1 interfaces due to skew between SCLK and SDAT. Many systems, such as 12C, are very low speed.

Finally, each system can suffer usability problems. For examp'e, there maybe no power supply to a device on the other side of the isolation barrier. There may be no provision for low-phase-noise clock distribution for precision analogue-to-digital converters (ADCs) on the isolated side. There may be no high-level protocols for common real-time requirement. There may be no security and so tapping the network reveals all information un-encrypted.

Summary

According to a first aspect of the present invention there is provided a serial bus controller having first and second terminals for coupling to a two-wire serial bus. The controller comprises a bus driver coupled to the terminals, the bus driver configured so as to be capable of converting a signal received from the bus into power for the controller. The controller comprises a phase demodulator or detector coupled to the terminals which is configured to decode phase position (herein also referred to as "timing") of a rising or falling edge of a signal received from the bus into n bits of data, where n is a positive integer (preferably n is 3 or 4, but can be 1, 2,5 or 6). The jo controller comprises a phase modulator configured to convert n bits of data into a phase position for a rising or fafling edge of a signal to be transmitted on the bus. The controller comprises a circuit configured to receive the phase position from the phase modulator and to provide control signals to the bus driver to cause transmission of the signal.

The controller can be used as a master or stave for a serial data bus which also provides dectrical isolation (using a transformer) and which can a'so be used for power delivery and clock distribution.

The bus driver may comprise a first push-pull arrangement comprising first and second transistors arranged in series between first and second rails, wherein output of the first transistor is connected via a first node to input of the second transistor and wherein the first terminal is connected to the first node and a second push-pull arrangement comprising third and fourth transistors arranged in series between the first and second rails, wherein output of the third transistor is connected via a second node to input of the fourth transistor and wherein the second serial bus interface terminal is connected to the second node.

TI-ic transistors may comprisc powcr transistors. The transistors may comprisc PETs.

For example, the first and second transistors comprise a PFET and NFET respectively and the third and fourth transistors may comprise a PFET and NFET respectively.

The serial bus controfler may further comprise an oscillator. The oscillator may be multiphase oscillator. The oscillator may be coupled to the phase demodulator and the phase modulator. The multiphase oscillator may comprise a rotary travelling-wave oscillator. The multiphase oscillator may comprise a low-noise ring-oscillator.

The oscillator may be free running. The serial bus controller may comprise a circuit for phase lock oop locking the oscillator with a clock signal received from the bus, e.g. the rising edge (also referred to as the "positive" edge).

The serial bus controller maybe operable as a master and may be configured to drive the rising edge of the signal. The serial bus controller maybe operable as a slave and may be configured to drive the falling edge of the signal.

Jo The rising and falling edges are preferably rising and fafling edged of the same pulse.

The bus driver may be configured for differential bus signalling. The serial bus controller may further comprise a converter coupled to the first and second terminals for converting a differential signal into a single-ended signal.

The serial bus controfler may be configured to operate in and/or co-operate with first, second, third and fourth bus states. Tn the first bus state, a master transmits data to slave(s) and, optionally, transmits power to slave(s). In the second bus state, a master prepares to receive data from a slave. In the third bus state, a slave transmits data to the master and, optionally, transmits power to master. In the fourth bus state, a slave prepares to receive data from master.

According to a second aspect of the present invention there is provided an integrated circuit comprising a serial bus controller.

The integrated circuit may be a microcontroller.

According to a third aspect of the present invention there is provided a serial bus system comprising at least two intcgratcd circuits. The first and sccond tcrminals of a first one of the at least two integrated circuits are coupled to the first and second serial bus interface terminals of a second one of the at east two integrated circuits.

According to a fourth aspect of the present invention there is provided a serial bus system comprising at least two integrated circuits and a transformer comprising at least two coils. The first and second terminals of a first one of the at two integrated circuits are coupled to first and second terminals of a first coil of the transformer and the first and second serial bns interface terminals of a second one of the at two integrated circuits are coupled to first and second terminals of a second coil of the transformer.

According to a sixth aspect of the present invention there is provided a method of communication using a two-wire bus. The method comprises encoding n bits of data in a first edge of a signal transmitted on the bus using phase modulation or phase detection, where n is a positive integer and decoding n-bits of data in a second, opposite edge of a signal received on the bus using phase demodulation.

o The second edge lies in a window of time. The method may further comprise converting the signal during the window into power.

According to one or more aspects of the present invention there is provided a method of driving single transformer for contention-free bi-directional data transfer for n-bits per edge with simultaneous 2-way power coupling, a method of exploiting parasitic leakage inductance as an integra' circuit component (which may permit us of air-core inductors), a method of managing the magnetisation currents in the transformer to discourage or prevent interference with data transmission, a method of two-way synchronous rectification for power transfer, a method of accommodating transmission-line effects in a network, a method in protocol for timing information, flash-programming and/or a method for extracting low phase-noise clock from master clock edge which itself is being phase-modulated.

Brief Descriptions of the Drawings

Certain embodiments of the present invention will now be described, by way of examp'e, with reference to Figures 2 to 13 of the accompanying drawings, in which: Figure 1 illustrates a prior art serial data bus system; Figure 2 illustrates a serial data bus system; Figure 3 illustrates transformer parasitic effects; Figure 4 is a block diagram of master and slave nodes in a serial data bus system; Figure 5 illustrates a data encoding; Figure 6 shows a first operating state of maser and slave nodes shown in Figure 4; o Figure 7 shows a second operating state of maser and slave nodes shown in Figure 4; Figure 8 shows a third operating state of maser and slave nodes shown in Figure 4; Figure 9 shows a fourth operating state of maser and slave nodes shown in Figure 4; Figure 10 illustrates a simulation of the a serial data bus; Figure 11 is a Nock diagram of an encoding/decoding circuit; Figure 12 illustrate addressing slave nodes; and Figure 13 illustrates uses of the serial data bus system.

Detailed Description of Certain Embodiments

Devices and networks embodying an architecture (herein referred to as "IsoMesh") which can provide a simple solution for isolated data, power and precision clock using a two-wire network for reth-time applications. Although the IsoMesh architecture is intended to be used mainly in is&ated, asymmetrical (i.e. master/sbve) systems, it can be employed in symmetrical (i.e. master/master) systems.

Figure 1 illustrates a standard SF1 system. The SF1 system illustrates a common case employing a doubly-isolated hali'-bridge high-voltage MOSFET driver.

Figure 2 illustrates an example of an IsoMesh system. As shown in Figure 2, in the TsoMcsh systcm, clcctronic componcnts can bc movcd into a hard IP block on processor devices and a single, purely passive micro-transformer can be used to couple power, two-way data and a precision clock reference to both MOSET drivers.

The IsoMesh system can be simpler to implement and can save costs by using fewer components. For example, the standard SF1 arrangement shown in Figure 1 includes 10 die, name'y i.e. four isolators, two DCDC, two microcontrolkrs and two ciystal oscillators), eight transformers, namely six is&ators, two DCDC and a five-wire bus (which also indudes power). This arrangement can cost about $4. By contrast, the IsoMesh system shown in Figure 2 indudes two die, namely two microcontrollers, one transformer and a two-wire bus (which also provides power). This arrangement can cost about S 0.50 including die area @ $o.lo/mm2).

The architecture makes use of all the possible functions of a single transformer at the same time (i.e. hi-directional signal transmission, hi-directional power conversion, energy storage and electrical isolation). Circuits and timings are arranged to make best use of the transformer's equivalent circuit (i.e. coupling coefficient K, leakage jo inductance, primary inductance, secondary Tnductance).

The system can be seen as a switch mode power supply with integrated data transmission means or a data transmission system with integral switch-mode power conversion means.

The system can have one or more advantages. For example, it can provide isolation, it can provide fast data speed, use (on'y) two wires for power, data and precision clock distribution (it does not matter which way the two wires are connected, provide integrated power distribution and voltage step-up/step-down, provide differential signalling, provide thw phase-noise clock distribution and can be simple to implement (e.g. use of a single transformer plus an electronics IF block incorporated into the ICs) It can operate in two operating modes, name asymmetrical (master/slave for short-range, low cost as a possible alternative to 12C, SF1 etc.) and symmetrical Qong-range, master/master to possibly replace CAN / Fieldbus). It can achieve over 500 Mbps using an RTWO-based implementation and 100 Mbps using a ring oscillator design.

The protocols described herein can make it secure and easy to use for developers and end users.

Undcrlvina urinciplcs of oucration Power and data can be transmitted through a transformer. Rectifiers can be used to extract power from a signa' waveform and phase moduthtion can be used to transfer data.

There is a trade-off between frequency and power transmission: at higher frequencies, the data rate increases but the "parasitic" leakage inductance tends to limit high power throughput. Also, with the large size MOSFETs used for power driving, the gate capacitance CV2f power becomes unmanageable.

The TsoMesh architecture can help to keep the carrier frequency low, but retain a high data rate by using encoding multiple bits per edge.

Referring to Figure 3, the architecture is based on managing transformer parasitics and implementing timing systems which transparently encode and decode phase information.

As shown in Figure 3, managing the transformer's coupled and leakage inductance energy can help to achieve performance. The transformer can be an extremely high-fidelity, low noise component at low cost. Simple turns-ratios can be applied to change system power levels between devices Block diagram Figure 4 is a schematic block diagram of an TsoMesh system which includes a master node (herein simply referred to as the "master") and a slave node (herein simply referred to as the "slave") connected by a two-wire bus via a transformer. The master and slave node are similar, the only difference being the phase-locking of the slave's oscillator.

Push-Pull, individually-enabled PFET and NFET connect the bus to the local supply rails. This is an inherently bi-directional power coupling mechanism. However, normally the slave will use decoupling capacitors to store power synchronously rectified from the secondary-side of the bus.

The logic blocks can be implemented in HDL standard cell.

Muhiphase oscillator is typically a rotary travefling-wave oscillator (RTWO) or a tow-noise ring-oscillator.

The time->digita and digital->time blocks are shown in detail in Figure ii. They allow direct digital phase encoding and decoding.

The back-back inverters are relatively weak CMOS devices (-2ornA) which help to bias the bus during the otherwise high-impedance signal (edge) reception states. After the emptying of the leakage-inductance-energy, they ensure that the recovery transition does not oscillate.

The transformer's operation will be detailed later.

The bus can be extended with or without transformer isolation. It is possible to add provisions in firmware to allow for auto-detection of reversed bus wiring.

Operation will be described with reference to Figure 6, 7, 8 and 9. Tn Figures 6, 7, 8 and 9, single-ended equivalent circuits are used for ease of explanation.

Date encodinR For multi-bit phase encoding, a two-bit code plus break code arrangement will be used

as an example.

The arrangement employs continuous AC power and data bus.

The master device drives a positive edge on the bus. Phase position of this edge gives one or more bits of information to a slave. A master node has low on-resistance output and is able to supply power through this signal'.

Slave(s) measure the time of the master positive edge to recover the data bits. A slave then switches on a low-on-resistance driver to extract the power from the master.

Slave(s) synchronously rectif5j their power from the bus.

A slave device provides a negative edge of the bus to send phase-encoded data to mastcr. Thc mastcr recovers data bits from the slavc in same way as thc slave recovers bits from the master.

As shown in Figure 5, the arrangement can provide two-bits per edge encoding. The data rate in a two-bit per edge system is four times the bus frequency.

A master and slave can be connected directly or through a transformer to provide signal isolation.

The number of bits per edge can be increased depending on stability of the master and slave oscillators, plus any expected non-synchronous noise on the system. Tn practice, it can range from 1 to 6 bits. Each bit doubles the stability requirements. The phase step-time is TSTEP. As well as the norma' range of data phase-positions, there can be other positions reserved for status and link-control. Figure 5 shows a "break" command as a unique phase position.

A time->digital converter with resolution ITOD is able to accurat&y measure the phase jo and determine the TSTEP count and, therefore, recover possib'y many data bits per edge.

The Master starts packet with a "Break" code so packet to packet timings have the same phasing and, therefore, a reliable (and averagaNe) digita' timing result.

Data is encoded as the small difference in time in units of TSTEP from the average running accumulator of the times between edges of the same type.

Bus operation The bus clocks continuously at a rate FCLTC with the master driving the positive edge [A=÷, B=-for differential system], then the slave drives the negative edge [A=-, B=+ for differentia' system]. During initialisation, however, the master drives both positive and negative edges until the slave it powered-up and ready.

Data is encoded by the phase of these edges. Power is conveyed during the non-transition time periods using synchronous rectification.

The slave receives all of its timing information from the master and is relatively "dumb" in its awarcncss of any protocols which arc handlcd at thc mastcr cnd.

Noise immunity The signalling edge-polarity for each data direction is fixed, i.e. the master does positive edges and a slave does negative. Since the encoding scheme measures time relative to previous edges of the same polarity, there is a very high rejection of common-mode' modulation. in a differential signaling system which afready has high immunity, even -10- higher rejection can be achieved through use of simp'e ferrite bead to prevent common-mode to differential-mode conversion.

SinaBinR States Management of high-impedance modes of the Master and Slave to avoid contention, pius management of magnetisation and leakage-inductance-stored energy are employed. It can be broken down into 4 states of the bus.

Operation in the four states will now be described with reference to Figures 6 to 9.

State A: Master Drive Phase Data (and power transfer) (about 40% of cycle) Referring to Figure 6, slave having detected the rising-edge from master, immediate'y turns on PFET to begin extracting power. Magnetisation current begins at a peak -ye cii rrent from last half-cycle then ramps to peak +Ve current over this time. Through-current starts at zero and ramps positive at a rate proportional to i/L leak and proportional to the primary and secondary DC supply voltage difference State B: Master prepares to receive (Leakage energy reset time) (about 10% of cycle) Referring to Figure 7, the master "lets-go" of the transformer (switches off the PFET] in preparation to receive data from a slave. The slave automatically catches the transformer since it is still connected on the slave side. Through-current continues initially due to L_leak energy collapsing. Pulls current via output diode, SMPS-style-L_leak current quickly drops to zero with a full negative supply bias. 12L energy reabsorbed into -2.5V. Once primary current has fallen to zero, master can receive a slave signal since Vp will follow Vs. It is preferred not to be the state B for long since magnetisation current is sucking charge from +2.5VJso.

State C: Slave Drive Phase Data (and power transfer) (about4o% of cycle) Referring to Figure 8, the master having detected the falling-edge from slave, immediately turns on NFETto begin transmitting power. Magnetisation current begins at a peak ÷\Te current from last half-cycle then ramps to peak _\Te current over this time. Through-current starts at zero and ramps negative at a rate proportional to i/Lleak and proportional to the primary and secondary DC supply voltage difference.

State D: Slave(s) prepared to receive (leakage energy reset time) (about io% of cycle) Referring to Figure 9, slave "lets-go" of the transformer (switches off the Q4 NFET) in -11 -preparation to receive data from the master. The master automatically catches the transformer since it is still connected on the master side. Through-current continues initially due to Leak energy collapsing. Pulls current via output diode, SMPS-style.

Lleak current quickly drops to zero with 2,5-l-o.7V of reverse bias. 12L energy reabsorbed into -2.5VJso. Once secondary current has fallen to zero, slave(s) can all receive master edge signal since Vs will follow Vp.

Lleak sets an effective "RcoupleDCDC" which is the effective DC->DC coupling resistance for power coupling from primary to secondary. It gives the voltage drop per Jo amp draw on the slave supply R coup'e DCDC = L leak / (0.5 * tON).

At all times the magnetisation current in the transformer is maintained: one side or the other is always "holding on" to the transformer.

During leakage-reset time, the drive polarity at the transformer can reverse for a short time but ogic in the master and slaves make the receivers blind' to input transitions at these time periods.

Initialisation During startup, the Master device provides continuous +Ve and -ye clock. Nodes become powered-up through the ESD protection diodes initially and hold off from signalling back to master -until master tells them to do so.

Waveforms example simulation Figure 10 illustrates simulation of a discrete-device implementation at low frequency and low power throughput. It is based on 2.5 MHz for 10 Mbps datalink assuming 2 bits per edge. This can be achieved with very modest components.

Figurc 12 illustratcs in morc dctail an arrangcmcnt in which multipic slavc nodcs arc con nected to the master and the type of receiver used by the master. The master's data receiver circuit is a low-impedance, current-activated circuit to work with multiple slaves.

Non-addressed slaves will not send their drivers -Ve until they see the master flip its output -Ve following reception of the -Ve pulse from the addressed slave. They cannot let go of the transformer since that would dump the magnetisation current.

-12 -For the addressed slave, the -ye output is enough to flip the master.

Clock distribution The system provides high-quality clock distribution. This aspect has not been addressed previously in a low-end networking system.

With a differential signal path and strong, full-swing signals continuous clock edges, the possibility of incorporating a low phase noise clock distribution system is straightforward. Low phase noise clock available for lhigh ENOB ADC converters jo operating over isolated data links.

Choice of PLL architecture (Digital (time->diaital) or analoaue (chane pump+cao)) Analog PLL (No Time->Digital) In a minimalistic implementation, a slave node could use a classic PLL (phase-locked loop) (using charge pump and filter capacitor) to lock to the average phase of the master's edges. A simple phase detector can extract one bit per edge from the master.

To signal back to the master a slave at a minimum uses an on/off phase delay block to send back one bit per edge.

Digital systems For most cases, a fully digital approach is better. A time->digital conversion and digital-time conversion can be easily implemented. An implementation uses a multiphase ring oscillator, +latches (or flip-flops) for the time-digital part and multiplexors and a flop working from the multiphase oscillator for the digital->time part. There are some considerations to metastability, but these issues are well known from flash ADC thermometer decoding.

The digital system can be PLL locked or free running, as will not be explained in more dctail. 3°

Free running stave oscillator The concept works even with a free-running (no feedback) oscillator in the slave since accurate times given by the master are recorded in the ocal timebase counts by the Time->Digital converter and these numbers are divided numerically and fed to the Digital->Time converter for output timings. Since the timebase is the same, the slave -13 -outputs timings are automatically correct and a further advantage of this approach is that the data rate can change dynamically: there are no fixed baud rates as such.

Phase-locked diaital PLL Whenever a local low-phase-noise clock is needed for other applications, the local ring oscillator should be phase-locked to the master dock. True phase locking involves tuning the local oscillator until a fixed target count is achieved from the time->digital converter when measuring the time between start bits. This target value can be pail of the protoco' to allow for frequency changing.

Tf the count is too high, the local oscillator is sthwed. If count is below target, the oscillator is pushed higher. This uses a classic digital PLL tuning / locking algorithm where phase and frequency components are handled separately and ock is very fast.

The simplest method to phase ock is on the measured time between packet start bits since packet repeat intervah are designed begin at zero phase modulation. But for, say, a 20-pulse packet, the effective "reference clock" frequency wifl be 1/20th of the master clock rate. For best phase-noise performance it is actually possible to use every edge of the master even though they are being phase modulated and achieve a full frequency input to the digital PLL to achieve a frill speed "reference dock" as follows.

tt is known that the phase modulations of the master edge are multiples of TSTEP and not random jitter. Therefore, once the integer TSTEP count is determined (i.e. the data bits have been determined), the remainder (the fractional phase error) gives the phase error which should be used by the digital PLL to push/pull the oscillator. When phase locked to the master's clock, low phase noise can be expected from a well designed ring oscillator. Even better phase noise is possible using an RTWO.

Differential systems are preferred and this helps in distributing the low-phase noise clock, but in thc circuits (Pigurc 6, 7, 8 and 9, and Figurc 12) which cxplain opcration, single-ended topology is shown for simplicity using +Ve/-Ve supplies.

Packets Packets can be of variable length to suit encoding needs.

A hardware feature of the packet is a "Break" position indicating null data. This is useful for variable-length packet management. The master starts a packet with a break bit, but the slave can also transmit a Break character to signal that it has no more useful data to send back to the master. This can be useful for a round-robin scheme where master can skip to the next device.

A protocol can used to support a data rate change.

On high noise systems there could also be a dynamic adjustment of the number data bits per edge (down to i) depending on the CRC error rate and in extreme case a programmed data-ignore' time could be implemented to allow a slave to ignore its Jo input data for a preset amount of time. This time could be a very large dV/dT or dT/dT event which was known to be upcoming.

DC maanetisation level adjustment Where a time->digital converter is used to resolve the data, it can be arranged that multiple phase positions which yield the same data bit values, if for example the time-> digital conversion is extracted modulo-5 then phase excursions either side of the normal range by +/-n x (5xTSTEP) can be used to adjust the DC level of the bus but (by increasing or decreasing the positive polarity drive time) but still give the desired transmitted bit code to the slave. This scheme can remove the need for transformer coupling capacitors which can be a simpler method of eliminating DC current build-up from imbalanced magnetisation currents.

Potential protocol Many limitations of current network protocols can be addressed. These would relieve the end user of the tedious job of implementing these features for themselves as is usually the case.

The following are features which can be implemented: 1. Security/ Flash uploading Secure protocol based on XXTEA (or similar) can be defined. Each node has its own key code. This can prevent eavesdropping and hacking. Define a flash reprogramming protocol written in C which uses XXTEA protocol. OEM can encode a new flash upload file which only works on the given device and is secure.

-15 - 2. Inverted wiring detection and adjustment Given the advantage of a two-wire system, it is possible to "go the extra mile" and make it unimportant which way around those two wires are connected. This allows connectors be non-polarised. Thus, there is no need to colour-code the wires and/or there is no need to keep track of the winding directions of the transformer(s).

During initialisation, the master drives both edges to power up the slaves and sends a set pattern 0, 1, 0, 1. Any device getting the wrong data sets a bit internally to swap the po'arity of input and output thereafter.

3. Global real-time synchronisation maintained between devices Implement as a full frequency counter free running apart from periodic forced synch.

This would allow multiple independent devices to drive PWM waveforms synchronously because they could both know when the PWM period starts from the global time counter. Adding a bit at 100 ms intervals synchronous to when the loca' mains power-grid crosses zero volls allows for 5oHz/6oHz synchronisation of devices which might be switching smart-grid applications.

Implement by adding 4 bits to the packet protocoL Packet protocol is variable length so only have the overhead when need to send synch information.

00 = 1 ms synch 01 = 100 ms synch = 1 second synch 11 = g'obal reset of counter to full given value (64 bits follows) Global counter remains synchronised between these events whichjust ensure that de-synchronisation events do not sustain for very long.

4. Flexible Packet type / length / CRC The packet type should be adjustable for each stave independently. There is little, if any, sense in trying to define a universal packet with a fixed format: it is either too simple for a complex device or too comp'ex for a simple device which wants minimum latency. A minimalist packet might have no addressing (for cases where only one slave 5 attached) and/or no CRC (maybe just a parity bit). A compkx packet can have 8-bit addressing, 40-bit CRC, it can use XXTEA encryption and/or it can encapsulate another packet type. The only protocol which is fixed is the addressing protocol. Once a slave knows that it is/is not addressed the rest of the packet dependent on the slave.

5. Auto-address allocation after initialisation A search algorithm can be used to find connected devices. Each device can be provided with a unique ID number which may be 40 bits or more. The devices are mapped to shorthand address bits. This means addressing can use only the number of address bits needed, no more.

Jo 6. TcP/IPvO Tt is possible to use a protocol to define how a processor in a master node maps TCP/IP addresses onto the local (i.e. IsoMesh) network. The master can act as a proxy allowing even basic slave nodes to be Internet addressable.

7. Plug/Play, Redundancy / Re-routing/ Best-effort resends Tt is possible to define protoco's for restarting network, fault detection and re-routing.

A low-level re-try protocol after CRC error and acknowledge when packet got through would save of programming by the end user.

8.JTAG mode It is possible to create a.JTAG port over the protocol where the.JTAG port is exported from the hard 1P block and runs without any additional software, i.e. runs the IsoMesh from a state machine.

9. Debug /Breakpoints/Memory inspection This can be part of the JTAG emulation 10. Hopping mode A hopping modc, similar to "SSH" for linux can bc uscd whcrc onc node higher up in the hierarchy can take over a lower-level node and drive its connected slaves. This would let a single point of connection to the network reprogram or inspect devices not on the immediate connection.

11. SF1/PC emulation It is possible to carry existing SF1 or 12C signals at lower data rate (by oversampling them)for backward compatibility. -17-

12. Uni-directional mode (half-duplex) Some nodes do not need much data read from them. Tn these cases, both edges coud be generated by the master and give data on each edge. Half-duplex is the most likely method of master->master communication where neither master needs to distribute a clock and where both masters are running the main protocol software stack.

13. Link to FreeRTOS to work at administrator level FreeRTOS integration can be useful, e.g. scheduling events between different slaves at o times controfled by the global timer synch system.

Power transmission / Current limitina IsoMesh provides two-way power transmission. Whichever side of the isolation barrier has the highest voltage relative to the turns-ratio will transmit power to the other side at a rate dependent on the effective DCDC-resistance which can be very low for ferrite-torroid transformers.

For a complex mesh of multiply-interconnected devices, the power network impedance will drop. It is possible to implement current limiting into the power-extraction system.

This can help to provide power supply redundancy, as well as data path redundancy.

Voltage regulation For slaves which need a precise supply voltage, it is more efficient to use a low-dropout linear regulator on the secondary side rather than doing switched-mode power supply (SMPS) type topology provided the DCDC resistance figure is low enough.

SMPS topology can be implemented solely from the master side since it is in control of how much current is delivered to the slave (tON) and it can also take a high-quality sampic of thc slave's supply voltage (as shown in Figure 10: waveform "accurate analog of Vs at Vp") through the transformer if desired.

Transmission-line effects The system operates at lower-than characteristic impedance of the transmission fine.

The master drives the transmission line directly while the slaves communicate via a transformer. High edge rate on the bus initially sees a high impedance due to the leakage inductances of transformers. Reflections appear on the lines, mainly from the -18 -slaves since the end can be characteristically terminated. Eventually reflections fade and are dissipated by loss mechanisms.

To mitigate the effect of reflections on accurate edge positioning, a frequency and stave node separation can be chosen (dynamicafly) to position reflections mainly 1/4 clock cycle away from the data edges. This can be maintained where TSTEP is a multiple of the round-trip propagation delay from slave to master or slave to slave.

Non-isolated slaves jo Slaves can be tapped directly (without transformer) to the master bus using small inductor. They will synchronous'y rectify their own power from the bus. Similarly, multiple slaves can be directly attached to the secondary side of a single transformer.

Data rates can be considerably higher ExamDle aDplications Figure 13 illustrates 12 some applications/arrangements/uses.

The non-contact device could be a rotary coupler. This can allow slip rings to be omitted from control robots and sensor systems as power and data can communicated over a short air gap.

Implementation of isoMesh system An tsoMesh system can be implemented using a real-time microcontroller for attaching directly to power MOSFET having a 32-bit micro core, multiple IsoMesh interface ports for example one 1.8 V and one 12V (for providing power winging tap only), PWM -high speed + fractional cycle PWI\'I (ring oscillator taps), ADC (12 bit; <iRs) and/or ADC with PGA for multiplying the Vsense signal from Rsense. The microcontroller may include or have an interface to a temperature sensor which allows use of copper PCB tracc as Rscnsc. OK if know what thc tcmpcraturc is. On-chip voltagc rcfcrcncc Slaves that cannot cope with a particular data rate can still synchronously demodulate the power and wait until the data rate is dropped.

Estimated speeds and chip area for hard IF Estimated speed and chip area assume that each process has 1 k«=2 NFET and 2.5 ku PFET on-resistance per micron of width, that the master port is able to power 3 W total and that a standard ring-oscillator is used.

Process Data Rate Area(drivers) Area (logic) Area (total) 0.35 pm 3 V 50Mbps 0.7 mm2 0.3 mm2 1mm2 0.25 pm 2.5V So Mbps 0.5 mm2 0.2 mm2 0.7 mm2 0.18 pm i.8\T 150 Mbps 0.3 mm2 0.1 mm2 0.4 mm2 nm 1V 250 Mbps 0.2 mm2 o.o mm2 0.25 mm2

Example calculation

For 0.18 pm i.8V; 150 Mbps, 2 bits, 2 edges 37.5MHZ frequency = 27 ns period -9 ns>< 2 for power. 4.5 ns X 2 for phase data 4.5 ns / 4 phase positions = 1.125 ns phase step Time->Digital resolution = about 100 ps Master to drive 3 watts = 1.7A. Want 0.1 V drop max from P and N FET R = 58 rnuI total. 30 m(2 for N and Peach 33,000 pm width = 0.023 mm2 PFET = 0.06 mm2 X2 (two drivers) = 0.2 mm2 total Dissipation at 37MHz CV2f (oopF total all drivers) = 50 mW _o Rotaiy oscillator version 3X the above speeds based on picosecond class time->digital converter technology.

Figure 14 shows a further improvement to generate a +ioV supply with just an additional tap on the transformer.

It will be appreciated that many modifications may be made to the embodiments hereinbefore described. Such modifications may involve equivalent and other features which are already known in the design, manufacture and use of serial buses, parts thereof and which may be used instead of or in addition to features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment.

Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel features or any novel combination of features disclosed herein either expflcitly or implicitly or any generalization thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.

The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims (6)

1. Claims 1. A serial bus controfler comprising: first and second termina's for coupling to a two-wire seria' bus; a bus driver coupled to the terminals, the bus driver configured so as to be capable of converting a signal received on the bus into power for the controller; a phase demodulator or detector coupled to the terminals which is configured to decode phase position of a rising or falling edge of a signal received from the bus into n bits of data, where n is a positive integer; a phase modulator configured to convert n bits of data into a phase position for a rising or falling edge of a signal to be transmitted on the bus; and a circuit configured to receive the phase position from the phase modulator and to provide control signals to the bus driver to cause transmission of the signal.
2. 2. A serial bus controfler according to claim 1, wherein the bus driver comprises: a first push-pull arrangement comprising first and second transistors arranged in series between first and second rails, wherein output of the first transistor is connected via a first node to input of the second transistor and wherein the first terminal is connected to the first node; and a second push-pull arrangement comprising third and fourth transistors arranged in series between the first and second rails, wherein output of the third transistor is connected via a second node to input of the fourth transistor and wherein the second serial bus interface terminal is connected to the second node.
3. 3. A serial bus controller according to claim 2, wherein the first and second transistors comprise a PFET and NFET respectively and the third and fourth transistors comprise a PFET and NFET respectively.
4. 4. A scrial bus controller according to any prcccding claim, furthcr comprising a multiphase oscillator coupled to the phase demodulator and the phase modulator.
5. 5. A serial bus controfler according to claim 4, wherein the multiphase oscillator comprises a rotary travelling-wave oscillator.s
6. 6. A serial bus controller according to claim 4, wherein the multiphase oscillator comprises a low-noise ring-oscillator. -22-7. A serial bus controller according to any one of claims 4 to 6, wherein the oscillator is free running.8. A serial bus controller according to any one of claims 4 to 6, further comprising a circuit for phase lock loop ocking the oscillator with a clock signal received from the bus.9. A serial bus controller according to any preceding claim which is operable as a master and which is configured to drive the rising edge of the signal.10. A serial bus controfler operable according to any preceding claim which is which is operable as a slave and which is configured to drive the falling edge of the signal.ii. A serial bus controller according to any preceding claim, wherein the bus driver is configured for differential bus signalling.12. A serial bus controfler according to any preceding daim, further comprising: a converter coup'ed to the first and second terminals for converting a differential signal into a sing'e-ended signal.13. A serial bus controller according to any preceding claim, configured to operate in and/or co-operate with first, second, third and fourth bus states, wherein: in the first bus state, a master transmits data to slave(s) and, optionally, transmits power to slave(s); in the second bus state, a master prepares to receive data from a slave; in the third bus state, a slave transmits data to the master and, optionally, transmits power to master; and in the fourth bus state, a slave prepares to receive data from master.14. A serial bus according to any preceding claim wherein n = 3 or 4.15. An integrated circuit comprising a serial bus controfler according to any preceding claim.16. An integrated circuit according to claim 15 which is a microcontroller.-23 - 17. A serial bus system comprising: at kast two integrated circuits according to claim 15 or 16; wherein the first and second terminals of a first one of the at two integrated circuits are coupled to the first and second serial bus interface terminals of a second one of the at two integrated circuits.iS. A serial bus system comprising: at least two integrated circuits according to claim 15 or i; and a transformer comprising at least two coils; wherein the first and second terminals of a first one of the at least two integrated circuits are coupled to first and second terminals of a first coil of the transformer and the first and second serial bus interface terminals of a second one of the at least two integrated circuits are coupled to first and second terminals of a second coil of the transformer.19. A method of communication using a two-wire bus comprising: encoding n bits of data in a first edge of a signal transmifted on the bus using phase modulation, where n is a positive integer; and decoding n-bits of data in a second, opposite edge of a signal received on the bus using phase demodulation or phase detection.20. A method according to claim 19, wherein the second edge lies in a window of time and the method further comprises: converting the signal during the window into power.