GB2515793A - Signal processing apparatus - Google Patents
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- GB2515793A GB2515793A GB1311996.1A GB201311996A GB2515793A GB 2515793 A GB2515793 A GB 2515793A GB 201311996 A GB201311996 A GB 201311996A GB 2515793 A GB2515793 A GB 2515793A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/4806—Computations with complex numbers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/4806—Computations with complex numbers
- G06F7/4812—Complex multiplication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
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- Pure & Applied Mathematics (AREA)
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- General Engineering & Computer Science (AREA)
- Data Mining & Analysis (AREA)
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Abstract
A signal processing apparatus 22 comprises: a complex arithmetic unit 24 configured to perform a complex arithmetic function on a complex value input and to output a result; and a swap unit 26, 28 configured to perform a swap operation to swap the real and imaginary components of a complex value input and to output a result, where the swap unit can be disabled or enabled in order to configure the apparatus to perform a first function (Figure 3) or a second function (Figure 4) respectively. The apparatus may be used for Fast Fourier Transform (FFT) calculations. The swap unit may comprise multiplexors.
Description
SIGNAL PROCESSING APPARATUS
Technical Field
The present invention relates to signal processing apparatus.
Background to the Invention
Digital Signal Processing is a key component in many of today's high technology products. such as digital communications equipment and sensor array processors. The performance required from Digital Signal Processors (DSPs) continues to increase while constraints on power and cost remain tight. These requirements are often met by the use of Single Instruction, Multiple Data (SIMD) processors, which process multiple data values in parallel.
DSP devices are typically required to perform matrix math operations, complex arithmetic operations and Fast Fourier Transform (FFT) calculations. These operations can be efficiently performed using a SEVID processor, with multiple processor units performing the same operation on different data values in parallel. The instruction stream and control logic are shared by the processor units resulting in an efficient system, but the data bandwidth remains proportional to the number of data values being processed. When the data values are processed with different constant values, such as FFT coefficients or t1ter coefficients, the bandwidth required to supply the constant values is also proportional to the number of data values being processed in parallel. It is therefore desirable to use the same constant value in multiple processor units, The ability to reuse the constant value also aids in reducing the storage requirement for the constant values.
DSP circuitry has been developed that multiplies a first constant complex value, C. by the negative imaginary unit, -i, to produce a second constant value C.(-i). This allows two pressor units to multiply two data values by different coefficients, C and C.(-i), based on a single constant value. C. However, the existing circuitry uses thgic that adds a significant delay, which reduces performance and increases power consumption.
Summary of Tnvention
According to a first aspect of the present invention there is provided signal processing apparatus comprising: a complex arithmetic unit configured to perform a complex arithmetic function on a complex value input to the complex arithmetic unit and to output a result of the complex arithmetic function; and a swap unit configured to perform a swap operation to swap real and imaginary components of a complex value input to the swap unit and to output a result of the swap operation. wherein: the swap unit can be disabled to configure the signal processing apparatus to perform a first function on a complex value input to the signal processing apparatus; and the swap unit can be enabled to configure the signal processing apparatus to perform a second function on a complex value input to the signal processing apparatus.
The signal processing apparatus of the present invention enables separate processor units in a SIMD device to share a common complex coefficient and multiply independent data values by different complex coefficients. Sharing a common complex coefficient reduces silicon area and therefore reduces the cost of the DSP component.
The swap unit may be configured to receive an input complex value and to output the result of the swap operation to the complex arithmetic unit.
Alternatively, the swap unit may be configured to receive as its input the result of the complex arithmetic function performed by the complex arithmetic unit.
The signal processing apparatus may include more than one swap unit.
The comp'ex arithmetic unit may be configured to perform a complex multipheation operation.
The signal processing apparatus may further comprise a controller arranged to issue control signals to enable or disable the swap unit.
The controller may be configured to issue control signals every instruction cycle of the apparatus, thereby permitting the function performed by the signal processing apparatus to change every instruction cycle.
The swap unit may comprise two multiplexors sharing the same inputs and control signal.
The signal processing apparatus may further comprise memory means for storing data words, connected to input and output data paths of the signal processing apparatus.
The signal processing apparatus may further comprise memory means for temporarily storing data words between arithmetic units of the complex arithmetic unit to form a pipeline.
The signal processing apparatus may further comprise memory means for temporarily storing control signals such that a delay is introduced in a control signal path of a swap unit to match a delay in a data path of that swap unit.
The memory means may be implemented as a register file or an addressable memoly.
The signal processing apparatus may be implemented as one of: a circuit; an integrated circuit; a field programmable gate array (FPGA); an application specific integrated circuit (AS IC); a processor; or a digital signal processor (DSP).
Brief Description of the Drawings
Embodiments of the invention will now be described, strictly by way of example only, with reference to the accompanying drawings, of which: Figure 1 is a schematic illustration of a design using processor units containing an embodiment of the present invention, as well as a memory. a register file and a controller; Figure 2 is a schematic illustration of an apparatus according to an embodiment of the present invention compnsing logic to multiply two complex values, circuitry to swap the real and imaginaiy components of the input complex values, and circuitry to swap the real and imaginary components of the output complex value; Figure 3 is a schematic illustration of the apparatus shown in Figure 2, showing arithmetic logic units which form the logic to multiply the two complex values, when the circuitry to swap the real and imaginary components is disabled; Figure 4 is a schematic illustration of the apparatus shown in Figure 2, showing arithmetic logic units which form the logic to multiply the two complex values, when the circuitry to swap the real and imaginary components is enabled; and Figure 5 is a schematic illustration of an apparatus according to an embodiment of the present invention comprising logic to multiply two complex values, and circuitry at the inputs and output, in which multiplexors are used to swap the real and imaginary components of the comp'ex values.
Description of the Embodiments
Referring first to Figure I. a design incorporating apparatus according to an embodiment of the present invention is shown generally at 10, and comprises first and second processor units i2, i4, each having a plurality of arithmetic units to perform complex multiplication, and circuitry to swap the real and imaginary components of complex values. The first and second processor units 12, 14 are associated with a controller 16, a memory 18 and a register file 20.
The first and second processor units 12, 14 are used to multiply two complex values.
Both of the processor units 12, 14 read the same complex constant value C from the memory 18. Each processor unit 12, 14 reads a separate complex data value from the register file 20. Thus, for example, the first processor unit 12 may read a first complex data value A from the memory 18, whilst the second processor unit 14 reads a second complex data value B from the memory 18. Each processor unit 12. 14 receives separate control signals from the controller 16.
When the control signals are in a first state each processor unit 12, 14 calculates and outputs the complex product of its own respective complex data value (A or B) and the common complex constant value C. Thus, when the control signals are in the first state, the first processor unit 12 calculates and outputs the complex product A.C, whilst the second processor unit 14 calculates and outputs the complex product B.C.
When the control signals are in a second state each processor unit 12, 14 calculates and outputs the complex product of its own respective complex data value (A or B), the common complex constant value C and the negative imaginary unit, -i. Thus, when the control signals are in the second state, the first processor unit 12 calculates and outputs the product -i.A.C, whilst the second processor unit 14 calculates and outputs the product -i,B.C. Each processor unit 12, 14 writes the result of its complex multiplication to the register file 20.
The circuitry of the processor units 12, 14 is initially arranged with appropriate interconnections to implement a first arithmetic function, for example a complex multiplication operation. The processor units 12. 14 receive control signals from the controller 16, which may be a microcode controller or any other suitable controller. The control signals issued by the controller 16 can cause the circuitry of each processor unit 12, 14 to independently swap the real and imaginary components of the complex input values and complex output value. This has the effect of altering the function of the processor unit 12, 14 such that the circuitiy is arranged to implement a second, different, arithmetic function, such as a complex muhiplication with a complex phase shift. In this way, the same complex constant value read from the memory 18 can be used to perform the complex multiplication of an input complex data value with two different complex constant values, thereby reducing the number of complex constant values that must be stored in memory 18, and reducing the number of read operations to read complex constant values from memory 18.
When it is desired to implement the first arithmetic function, the controller 16 provides control signals to disable the swap of the real and imaginary components of the complex values that were enabled to implement the second arithmetic function, thereby causing the circuitry of the processor units 12, 14 to be arranged to imp'ement the first arithmetic function.
It is also possible, where the real and imaginary components of complex values can be swapped independently in the processor units 12, 14, for the controller 16 to provide alternative control signals to swap the real and imaginary components of certain of the complex values to perform further different arithmetic functions.
The register file 20 is provided for storage of data words, and connects to the input and output data paths of the processor units 12, 14. For example, the register file 20 may be configured to supply two complex values from two complex registers to the two processor units 12, 14, and it may also be configured to store two complex values from two processor units to two additional complex registers. Values that are output and stored in the register file 20 may be used as inputs to processor units 12, 14 on subsequent cycles.
The processor units 12, 14 may include internal registers for temporary storage of data words between arithmetic units of the processor unit so as to form a pipeline. For example. an arithmetic unit that receives inputs from the register file 20 may store the resulting value in an internal register. On the next cycle another arithmetic unit of the processor unit may receive the value from the internal register and store the output to the register file 20.
The processor units 12, 14 may, additionally or alternatively, include internal registers for temporary storage of control signals so that a delay can be introduced into a control signal path of circuitry of the processor unit 12, 14 to match a delay in a data path of that circuitry of the processor unit I 2, 14.
Examples of circuitry implementing a processor unit of the type shown at 12 and 14 in Figure I, having a plurality of arithmetic units to perform complex multiplication, and circuitry to swap the real and imaginary components of complex values, will now be illustrated by reference to Figures 2 to 5.
Figure 2 is an exemplary signal processing apparatus that is initially configured to perform a complex multiply operation on two complex values, B and C. The complex multiply is a significant operation for most DSP algorithms, including the Fast Fourier Transform (FF1). It can be implemented using various arrangements of multipliers and other arithmetic components, The apparatus, shown generally at 22. comprises a network including a complex arithmetic unit 24, which in this example is configured as a complex multiplier. and three swap units 26, 28, 30 used to swap the real and imaginary components of complex signals according to the state of a control signaL A controller 16 is configured to provide control signals to the swap units to alter the arithmetic function of the network 22.
The network 22 of the complex arithmetic unit 24 and swap units 26, 28, 30 shown in Figure 2 is initially configured to perfoirn the complex multiplication of complex inputs B and C, and provide the product B.C at the complex output P. P=B.C (1) However, the network 22 can perform the complex multiplication of B, C and the complex negative imaginary unit, -i, to provide the product -i.B.C at the complex output, labelled Q for clarity in Figure 4, by use of control signals from the controller 16, which are used to enable the swap units 26, 28, 30.
Q = -i.B.C (2) The controller 16 maybe configured to issue control signals once per instruction cycle, which permits the arithmetic function performed by the apparatus 22 to be altered on a per-instruction basis.
In the following equations the complex value B consists of the real component Br and the imaginary component Bi, The notation (B.C)r indicates the real component of the complex product of B and C. In the arrangement illustrated in Figure 2, the complex arithmetic unit 24 represents a processor unit implementing the function defined by equation (1): Pr = Br.Cr -Bi.Ci = (B.C)r (3) Pi = Br.Ci + Bi.Cr = (B.C)i (4) Thus, the complex arithmetic unit 24 may be regarded as being made up of a plurality of interconnected arithmetic units which are operative to perform the complex multiplication BC, as illustrated schematically in Figure 3.
It will be appreciated that the arrangement of arithmetic units used to implement the complex multiplier 24 does not affect the operation of the network 22.
An arrangement of arithmetic units operative to perform complex multiplication is shown, by way of example only, at 24 in Figure 3. The value of each signal is shown at the input and output of each arithmetic unit, and the value of Pr and Pi is shown to match the function of the network 22 described by equations (3) and (4).
The three swap units 26, 28, 30 may be enabled individually to change the function of the network 22. A second ffinction of the arrangement illustrated in Figure 2 will now be described, but it should be understood that the function described here is not the only alternative function. Those skilled in the art will readily be able to adapt the example network 22, in the light of this disclosure, to perfom specialised tasks.
To implement the product -i.B.C defined by equation (2), all three of the swap units 26, 28, 30 are enabled using control signals issued by the controller 16, as illustrated in Figure 4. It will be noted that the operation of the complex multiplier 24 does not change, as the arithmetic units making up the complex arithmetic unit 24 have not changed. Instead, enabling the swap units 26, 28, 30 alters the functionality of the network 22, and causes the real and imaginary components of the complex values input to the complex arithmetic unit 24 to change, thereby altering the real and imaginary components of the complex value output by the complex arithmetic unit 24 to change as well.
The value of each signal is shown at the input and output of each arithmetic unit in Figure 4. The operation of the complex multiplier 24 with the swap units 26, 28, 30 enaNed can be shown, with reference to equations (3) and (4) and Figure 4, as: Qr = Br.Ci + Bi.Cr = Pi (5) Qi = Bi.Ci -Br.Cr = -Pr (6) The complex values P and Q can be described as the sum of their real and imaginary components, as shown in equations (5) and (6): P = Pr + i.Pi (7) Q=Qr+LQi (8) By substituting the results of equations (5) and (6) in equation (8), and by comparison with equations (1) and (7). it can be seen that the result of the network with the swap units enabled is -i.B.C, as defined in equation (2): Q = Qr + i.Qi = Pi -i.Pr = -i.(Pr + i.Pi) = -i.P = -i.B.C (7) Thus, with the swap units disabled the network 22 implements the product B.C as defined by equation (I), and with the swap units enabled the same network 22 implements the product -i.B.C as defined by equation (2).
An example of how the real and imaginaly components of a complex value may be swapped is given in Figure 5, in which the swap unit 26 of Figure 2 is made up of multiplexors 34, 36, which take a common control signal as an input, and swap the real and imaginary components Br and Bi before they are passed to the input of the complex arithmetic unit 24.
It should be understood that the design illustrated in Figure 5 is merely one example of a way of swapping the real and imaginary components of a complex value, and that various ways to swap data signals exist. Therefore the invention is not limited to any particular way of swapping the real and imaginary components of a complex value.
It will be appreciated that the present invention enables separate processor units in a SIMD device to share a common complex coefficient and multiply independent data values by different complex coefficients. Sharing a common complex coefficient reduces silicon area and therefore reduces the cost of the DSP component.
The additional modes of operation are selected by enabling one or more swap units to swap the real and imaginary components of a complex value. This increases the flexibility of the hanlware and reduces the bandwidth and storage requirements for constant complex values. The method used to enable swap units may include control signals generated by a microcode controller, or any suitable circuitry and any suitable control signals.
The invention has been described in this specification in terms of complex arithmetic units and swap units that swap the real and imaginary components of complex values. It will be appreciated that the invention may be implemented in many different ways, for example using Application Specific Integrated Circuits (ASICs), Field Programmable Gate Auays (FPGAs), bespoke Integrated Circuits (ICs) or Digital Signal Processors (DSPs), or even using discrete components such as transistors, capacitors and the like.
The invention may also be implemented as software running on a suitably configured processor.
Moreover, although the invention has been described and illustrated in the context of an apparatus for perfomiing a complex multiplication, it will be appreciated that the principles of the invention may be applied to any complex arithmetic function, and thus the invention is not limited to complex multiplication.
Claims (14)
- CLAIMS1. Signal processing apparatus comprising: a complex arithmetic unit configured to perform a complex arithmetic function on a complex value input to the complex arithmetic unit and to output a result of the complex arithmetic function; and a swap unit configured to perforni a swap operation to swap real and imaginary components of a complex value input to the swap unit and to output a result of the swap operation. wherein; the swap unit can be disabled to configure the signal processing apparatus to perform a first function on a complex value input to the signal processing apparatus; and the swap unit can be enaHed to configure the signal processing apparatus to perform a second function on a complex value input to the signal processing apparatus.
- 2. Signal processing apparatus according to claim I wherein the swap unit is configured to receive an input complex value and to output the result of the swap operation to the complex arithmetic unit.
- 3. Signal processing apparatus according to claim 1 wherein the swap unit is configured to receive as its input the result of the complex arithmetic function performed by the complex arithmetic unit.
- 4. Signal processing apparatus according to any one of the preceding claims including more than one swap unit.
- 5. Signal processing apparatus according to any one of the preceding claims wherein the complex arithmetic unit is configured to perform a complex multiplication operation.
- 6. Signal processing apparatus according to any one of the preceding claims further comprising a controller arranged to issue control signals to enable or disable the swap unit.
- 7. Signal processing apparatus according to claim 6 wherein the controller is configured to issue control signals every instruction cycle of the apparatus, thereby permitting the function performed by the signal processing apparatus to change every instruction cycle.
- 8. Signal processing apparatus according to any one of the preceding claims wherein the swap unit compr ses two multiplexors sharing the same inputs and control signal.
- 9. Signal processing apparatus according to any one of the preceding claims further comprising memory means for storing data words, connected to the input and output data paths of the signal processing apparatus.
- 10. Signal processing apparatus according to any one of the preceding claims fur her comprising memory means for temporarily storing data words between arithmetic units of the complex arithmetic unit to form a pipeline.
- 11. Signal processing apparatus according to any one of the preceding claims further comprising memory means for temporarily storing control signals such that a delay is introduced in a control signal path of a swap unit to match a delay in a data path of that swap unit.
- 12. Signal processing apparatus according to claim 10 or claim 11 wherein the memory means is implemented as a register file.
- 13. Signal processing apparatus according to claim 10 or claim 11 wherein the memory means is implemented as an addressable memory.
- 14. Signal processing apparatus according to any one of the preceding claims, wherein the apparatus is implemented as one of: a circuit; an integrated circuit; a field programmable gate array (FPGA); an application specific integrated circuit (ASIC); a processor; or a digital signal processor (DSP).AMENDMENTS TO CLAIMS HAVE BEEN 19LED AS FOLLOWSCLAIMS1. Signal processing apparatus comprising: a complex arithmetic unit configured to perform a complex arithmetic function on a complex value input to the complex arithmetic unit and to output a result of the complex arithmetic function; and a swap unit configured to perform a swap operation to swap real and imaginary components of a complex value input to the swap unit and to output a result of the swap operation, wherein; the swap unit can be disabled to configure the signal processing apparatus to perform a first function on a complex value input to the signal processing apparatus; and the swap unit can be enabled to configure the signal processing apparatus to perform a second function on a complex value input to the signal processing apparatus, the signal processing apparatus further comprising a controller alTanged to issue control signals to enable or disable the swap unit, wherein the controller is configured to issue control signals every instruction cycle of the apparatus, thereby permitting the function performed by the r signal processing apparatus to change every instruction cycle. ci)r 2. Signal processing apparatus according to claim I wherein the swap unit is configured to receive an input complex value and to output the result of the swap operation to the complex arithmetic unit.3. Signal processing apparatus according to claim I wherein the swap unit is configured to receive as its input the result of the complex arithmetic function performed by the complex arithmetic unit.4. Signal processing apparatus according to any one of the preceding claims including more than one swap unit.5. Signal processing apparatus according to any one of the preceding claims wherein the complex arithmetic unit is configured to perform a complex multiplication operation.6. Signal processing apparatus according to any one of the preceding claims wherein the swap unit comprises two multiplexors sharing the same inputs and control signal.7. Signal processing apparatus according to any one of the preceding claims further comprising memory means for storing data words, connected to the input and output data paths of the signal processing apparatus.8. Signal processing apparatus according to any one of the preceding claims further comprising memory means for temporarily storing data words between arithmetic units of the complex arithmetic unit to form a pipeline.9. Signal processing apparatus according to any one of the preceding claims further comprising memory means for temporarily storing control signals such that a delay is introduced in a control signal path of a swap unit to match a delay in a data path of that swap unit.10. Signal processing apparatus according to claim 9 or claim 10 wherein the memory r means is implemented as a register file. ci)r II. Signal processing apparatus according to claim 9 or claim 10 wherein the memory means is implemented as an addressable memory.12. Signal processing apparatus according In any one of the preceding claims, wherein the apparatus is implemented as one ol: a circuit; an integrated circuit; a held programmable gate anay (FPGA); an application specific integrated circuit (ASIC); a processor; or a digital signal processor (DSP).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1311996.1A GB2515793A (en) | 2013-07-04 | 2013-07-04 | Signal processing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1311996.1A GB2515793A (en) | 2013-07-04 | 2013-07-04 | Signal processing apparatus |
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| GB201311996D0 GB201311996D0 (en) | 2013-08-21 |
| GB2515793A true GB2515793A (en) | 2015-01-07 |
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| GB1311996.1A Pending GB2515793A (en) | 2013-07-04 | 2013-07-04 | Signal processing apparatus |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0080266A2 (en) * | 1981-11-24 | 1983-06-01 | Itt Industries, Inc. | Discrete fourier transform circuit |
| US5669010A (en) * | 1992-05-18 | 1997-09-16 | Silicon Engines | Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units |
| US20060224651A1 (en) * | 2005-03-31 | 2006-10-05 | Texas Instruments Incorporated | Combined IFFT and FFT system |
| US20070192394A1 (en) * | 2005-12-30 | 2007-08-16 | Oki Techno Centre (Singapore) Pte Ltd | Processor and method for performing a fast fourier transform and/or an inverse fast fourier transform of a complex input signal |
| US20090013021A1 (en) * | 2007-07-06 | 2009-01-08 | Mediatek Inc. | Variable length fft system and method |
-
2013
- 2013-07-04 GB GB1311996.1A patent/GB2515793A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0080266A2 (en) * | 1981-11-24 | 1983-06-01 | Itt Industries, Inc. | Discrete fourier transform circuit |
| US5669010A (en) * | 1992-05-18 | 1997-09-16 | Silicon Engines | Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units |
| US20060224651A1 (en) * | 2005-03-31 | 2006-10-05 | Texas Instruments Incorporated | Combined IFFT and FFT system |
| US20070192394A1 (en) * | 2005-12-30 | 2007-08-16 | Oki Techno Centre (Singapore) Pte Ltd | Processor and method for performing a fast fourier transform and/or an inverse fast fourier transform of a complex input signal |
| US20090013021A1 (en) * | 2007-07-06 | 2009-01-08 | Mediatek Inc. | Variable length fft system and method |
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| GB201311996D0 (en) | 2013-08-21 |
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