GB2515770A

GB2515770A - Tuning network

Info

Publication number: GB2515770A
Application number: GB201311869A
Authority: GB
Inventors: Jouni Kristian Kaukovuori; Teijo Henrikki Lehtinen
Original assignee: Broadcom Corp
Current assignee: Broadcom International Ltd; Broadcom Corp
Priority date: 2013-07-02
Filing date: 2013-07-02
Publication date: 2015-01-07
Anticipated expiration: 2033-07-02
Also published as: GB201311869D0; GB2515770B

Abstract

A resistor tuning network comprises a resistor ladder including a plurality of resistor rungs each comprising a first resistance R and a second resistance 2R. The second resistance of each resistor rung in the plurality is connected to a switching arrangement. A respective switching arrangement is controllable to connect the respective second resistance to either a positive side Î±Vs of a differential signal or the negative side Î±Vs of the differential signal. The tuning network may be used in a duplexer for a radio frequency transceiver.

Description

TuninQ network

Technical Field

The present invention relates to a tuning network. In particular, but not exclusively, the present invention relates to a resistor tuning network comprising a resistor ladder.

Background

Nowadays, multiband transceivers require several off-chip RF filters and duplexers to bc able to support multiple frequency bands. Although hybrid transformer teclmiques have already been used in telephony systems for some 60 years now, integrated duplexers have been proposed relatively recently. With integrated duplexers, power amplifier (PA) coupling to low noise amplifier (LNA) input can be minimized.

Figure la shows a prior art duplexer topology from a paper entitled "An On-Chip Wideband and Low-Loss Duplexer for 3G/4G CMOS Radios" by Mikhemar et al. published in the 2010 Symposium on VLST Circuits/Technical Digest of Technical Papers. The duplexer topology of Figure la uses a single-ended PA with a single hybrid transformer. If the impedance formed by the tuneable resistor Rbal and tuneable capacitor Cbal replicates the antenna impedance, and the transformer is properly designed, then the PA signal magnetic fluxes cancel in the hybrid transformer, and the PA signal does not appear differentially in the LNA input. However, due to the capacitance between the hybrid transformer primary and secondary windings, the common mode PA signal may be high at the LNA input.

Figure lb shows a prior art duplexer topology from a paper entitled "A Tunable Differential Duplcxer in 9Onm CMOS" by Abdelhalem ct al. published in the 2012 IEEE Radio Frequency Integrated Circuits Symposium. The duplexer topology of Figure lb uses a differential PA with two hybrid transformers. Here, both the differential and common-mode PA signals are cancelled, but requires an additional balun at the antenna port which adds to losses and cost.

A challenge is to achieve good PA to LNA isolation; achieving better than 50dB (decibels) isolation may require a resistor tuning (or trimming') network which has better than 0.25 0 (Ohms) accuracy.

Achieving 0.25 0 tuning accuracy with normal serial and parallel resistor connections leads to a large resistor network. For example, Figure 2 shows a plot of possible resistor values when 100 0 resistors are connected such that there are 1 to 15 series connections (100 -1500 0) and 1 to 25 parallel connections (i.e. a 15 x 25 matrix). Although the number of resistances is fairly large, the minimum resistance step (i.e. the smallest gap' between achievable resistance values) in a tuning area of interest (such as 100 -33 0) is still large. In the example plot of resistance steps shown in Figure 3, the minimum resistance step is 20 which is too large for many applications such as duplexer applications.

An alternative prior art method to achieve a small resistance step is to use a voltage controlled variable resistor. Such analogue variable resistors are often too nonlinear for high power TX signals. Furthermore, providing an appropriate analogue control voltage is challenging.

Sunnnary According to a first aspect of the present invention, there is provided a resistor tuning network comprising a resistor ladder, wherein the resistor ladder comprises a plurality of resistor rungs each comprising a first resistance and a second resistance, and wherein the second resistance of each resistor rung in the plurality is connected to a switching arrangement, a respective switching arrangement being controllable to connect the respective second resistance to either a positive side of a differential signal or the negative side of the differential signal.

According to a second aspect of the present invention, there is provided a method of operating a resistor tuning network, the resistor tuning network comprising a resistor ladder, the resistor ladder comprising a plurality of resistor rungs each comprising a first resistance and a second resistance, the second resistance of each resistor rung in the plurality being connected to a switching arrangement, the method comprising; applying one or more control signals to each of the switching arrangements to control connection of the respective second resistance to either a positive side of a differential signal or the negative side of the differential signal.

According to a third aspect of the present invention, there is provided apparatus substantially in accordance with any of the examples as described herein with reference to and illustrated by the accompanying drawings.

Further features and advantages of the invention will become apparent from the following description of preferred embodiments of the invention, given by way of example only, which is made with reference to the accompanying drawings.

Brief Description of the Drawings

Figure la shows a duplexer topology according to the prior art; Figure lb shows a duplexer topology according to the prior art; Figure 2 shows a plot of resistor values according to the prior art; Figure 3 shows a plot of resistance step values according to the prior art; Figure 4 shows a resistor tuning network according to embodiments; Figure 5 shows a plot of tuning network resistance values according to embodiments; Figure 6 shows a plot of resistance step values corresponding to the tuning network resistance values of Figure 5 according to embodiments; Figure 7 shows a table of maximum and minimum resistance for the tuning network of embodiments; Figure 8 shows resistor tuning networks according to embodiments; Figure 9 shows a resistor tuning network according to embodiments; Figure 10 shows a plot of tuning network resistance values according to embodiments; Figure 11 shows a plot of resistance step values corresponding to the tuning network resistance values of Figure 10 according to embodiments; and Figure 12 shows a resistor tuning network according to embodiments.

Detailed Description

Embodiments described below relate to resistor tuning networks comprising an RI2R resistor ladder. The resistor ladder of the resistor tuning networks of embodiments is described as a RI2R resistor ladder purely for explanatory purposes and it should be understood that embodiments should not be limited to including a R/2R resistor ladder. Embodiments comprise any type ofresistor ladder with first and second resistance values, for example one of value Rand another of value 1 8R or the like. In some embodiments, the first and second resistance values are different, but in other embodiments could be the same resistances.

Figure 4 shows a resistor tuning network according to embodiments. The resistor tuning network comprises an R!2R resistor ladder. The R'2R resistor ladder comprises a plurality of R'2R resistor rungs each comprising an R resistance and a 2R resistance. The 2R resistance of each R/2R resistor rung in the plurality is connected to a switching arrangement, a respective switching arrangement being controllable to connect the respective 2R resistance to either a positive side of a differential signal or the negative side of the differential signal. The switching arrangements) could for example be implemented as one or more transistors.

Embodiments provide tuning networks (for example embodied as electronic circuits) with extremely fine resistor step and small/compact die area.

In embodiments, an input of the R12R resistor ladder is provided with a signal voltage Vs and the negative and positive sides of the differentia' signal are generated on the basis of replicas of the signal voltage Vs.

In embodiments, the positive side of the differential signal is generated by multiplying a replica of the signal voltage Vs by an attenuation parameter a and the negative side of the differential signal is generated by multiplying a replica of the signal voltage Vs by minus the attenuation parameter a.

The attenuation parameter may for example comprise a value between 0 and 1.

The attenuation parameter may for example comprise one of the following values: 0.25, 0.5, 0.66, and 0.75.

In embodiments, the attenuation from the signal amplitude Vs is relatively low, so that the attenuation may depend on the load Rin, and thus vary according to the switching arrangements. In embodiments, the attenuation parameter varies at least in dependence on the switching arrangements.

In some embodiments, the 2R resistance of each Ri'2R resistor rung is connected to the respective switching arrangement on the opposite side of the 2R resistance to the R resistance of the respective rung.

In embodiments, the switching arrangement of each R/2R resistor rung is controllable to connect the respective 2R rcsistance to cithcr the positivc sidc of the differential signal or the negative side of the differential signal via application of one or more control signals to the respective switching arrangement.

As can be seen from Figure 4, in embodiments, instead of connecting the 2R nodes of each rung in the R!2R ladder to ground as in known R/2R ladders, there is a connection to a signalvoltage Vs replica such that the replica of the signalvoltage is attenuated by an amount determined by an attenuation parameter a. In embodiments, for each rung of the R12R ladder of cmbodiments, there are two connections having different sign, i.e. aVs and -ctVs. By connecting the R2 resistance of each rung via respective switching arrangements controlled with control signals CO, Cl, .. Cn to either czVs or -aVs, an extremely small resistance step can be achieved.

Resistance values of the tuning network Rn of embodiments were analyzed with different attenuation parameter a values according to embodiments. For example, with a = R11 varies between 2tR and R13. Fignre 5 shows a plot of ideal tuning network resistance values Rn, when R100 and the ladder has 10 rungs (i.e. 10-bit tuning is used) according to embodiments. Figure 6 shows a plot of resistance step values corresponding to the R values of Figure 5 according to embodiments.

As can be seen from Figures 5 and 6, even with a 10 rung ladder (i.e. 10-bit tuning), the resistance step is as low as 0.2 Q. By using a larger attenuation parameter a value, the maximum-resistance value of the tuning network Ru' is increased and the minimum resistance value of the tuning network R11 is reduced as is shown in the table of Figure 7. For example, with a = 1⁄4 R, and a ten rung ladder according to embodiments, ideal tuning provides resistance values between 28.5 and 200 0.

However, the resistance step is increased thus requiring more control bits. Here, the overall resistor count is roughly twice the number of tuning bits. Typically, 8-12 bit tuning is adequate to achieve resistance steps as low as 0.5 or 0.25 0 according to embodiments.

In embodiments, the resistor tuning network comprises first and second differential inductors arranged to generate the positive side of the differential signal and the negative side of the differential signal respectively. The positive and negative sides of the differential signal may comprise attenuated differential signals ctvs and -aVs, which in embodiments can for example be taken from differential inductors.

In embodiments where the positive and negative sides of the differential signal comprise attenuated differential signals aVs and -ctVs, the overall voltage swing over the first rung of the ladder (with path CO active such that the switching arrangement connects the first rung 2R resistance to aVs) is (1-a)Vs, such that with larger a values, the voltage swing is reduced.

In embodiments where the positive and negative sides of the differential signal comprise attenuated differential signals ctVs and -aVs, the overall voltage swing over the first rung of the ladder (with U active such that the switching arrangement connects the first rung 2R resistance to -aVs) is (1+ct)Vs and Vs can be over IOV with power levels of-{-23dBm.

In embodiments, the 2R resistance of at least one R/2R resistor rung in the plurality comprises first and second 2R resistance elements connected in parallel, the first 2R resistance element comprises first and second resistance portions, the second 2R resistance element comprises first and second resistance portions, and the switching arrangement of the at least one R/2R resistor rung is connected between the first and second resistance portions of the first 2R resistance element and between the first and second resistance portions of the second 2R resistance element.

Embodiments which tolerate relatively large voltage swing involve first splitting a rung of the ladder into two 2R resistance parts (a first 2R resistance part 800 and a second 2R resistance part 802) as shown in the upper resistor tuning network of Figure 8. In embodiments, the rung with the two 2R resistance parts comprises the first run in the ladder, or any other rung in the ladder, or multiple rungs in the ladder.

Then, as shown in the lower resistor tuning network of Figure 8, the first 2R resistance part 800 is split into two portions 800a and 800b and the second 2R resistance part 802 is split into two portions 802a and 802b. The switching anangement of the first rung is connected between the resistor portions 800a, 800b, 802a, 802b of the first and second 2R resistance part 800, 802 such that the overall connection resistance is 2R but at the node between the resistors, the signal is nulled, i.e. at virtual ground. Then, the voltage swing over the switch U is relatively small. According to the simulations with a 10 rung (or 10-bit) ladder, the maximum voltage swing over the first node of the ladder is approximately 0.75 In ffirther embodiments, a similar principle could be used in the second or further rungs, either alternatively or in addition to the first rung.

In embodiments, the resistor tuning network comprises a shunt resistor R'r connected in parallel with the R!2R resistor ladder as shown in the resistor tuning network of Figure 9. In such embodiments, part of the current flows through the shunt resistor R-r and only part goes into R/2R circuit network thus decreasing the amount of current flowing via the switching arrangements. Such embodiments relax switch transistor sizing optimisation.

Figure 10 shows a plot of tuning network resistance values R according to embodiments. Figure 11 shows a plot of resistance step values corresponding to the tuning network resistance R values of Figure 10 according to embodiments. The different traces in Figures 10 and 11 correspond to different shunt resistor R'r values (2000, 4000, 8000, no shunt resistor) when the nominal resistance value of the R/2R ladder network is 1000 and the attenuation parameter a is 3/4.

As can be seen from Figures 10 and 11, with a lower shunt resistor Rrvalue, the resistance tuning range is decreased and the resistance step size is smaller. For example, with an Rr value of 2000, the maximum R is roughly 660. Then, by increasing the impedance level of both the R/2R network and Rrby 1.5, the same tuning area and step accuracy is achieved as when a = 1⁄4 and R'rarc removed. Furthermore, the same tuning range and step size is achieved when a = 1 and Ri = R, but the whole network impedance is doubled. However, since the resistance level is higher, the effect of switch on-resistance is made smaller. Thus, the performance of the overall network can be optimized by choosing appropriate values for a and Rr.

In embodiments, the effect of switch on-resistance and its effect to ladder (non)lincarity is ameliorated and/or neutralized by adding dummy always active (or always on) switches in series with the R resistance of one or more rungs of the R!2R ladder. An example of a circuit for such embodiments is shown in Figure 12 where the first, second and nth rungs comprise always on switches in series with the R resistance, denoted by SI, S2 and Sn respectively.

Embodiments comprise at least one always on switch connected in series between the R resistance of at least a first Rt2R resistor rung in the plurality and the R resistance of at least a second R'2R resistor rung in the plurality, the at least first R12R resistor rung being located next to the at least second RI2R resistor rung in the RI2R resistor ladder.

In embodiments, the on-resistance of the at least one always on switch is approximately half of the on-resistance of the switching arrangement of the at least first R/2R resistor rung and/or the switching arrangement of the at least second R/2R resistor rung.

In any embodiments, the resistors R and 2R of a resistor rung n can also be comprised of a series resistor Rsn and a parallel resistor Rpn, and the resistor values of each n rungs can be intentionally or not intentionally different.

Embodiments comprise a duplexer comprising one or more resistor tuning networks of embodiments described herein. The resistor tuning network of embodiments described herein may for example be comprised in the integrated duplexers of Figures laor lb. Embodiments comprise an antenna tuner comprising one or more resistor tuning networks of embodiments described herein.

Embodiments comprise a radio-frequency semiconductor integrated circuit (RFIC) comprising one or more resistor tuning networks of embodiments described hcrcin Embodiments comprise a chipsct comprising one or more rcsistor tuning networks of embodiments described herein Embodiments comprise a radio frequency (RF) transceiver comprising one or more resistor tuning networks of embodiments described herein.

Embodiments comprise a device comprising one or more resistor tuning networks of embodiments described herein. The device may comprise a user equipment such as a mobile (or cellular') phone.

Embodiments comprise a method of manufacturing a resistor tuning network of embodiments described herein Embodiments comprise a method of operating a resistor tuning network, the resistor tuning network comprising an R/2R resistor ladder, the R/2R resistor ladder comprising a plurality of R/2R resistor rungs each comprising an R resistance and a 2R resistance, the 2R resistance of each R!2R resistor rung in the plurality being connected to a switching arrangement, the method comprising; applying one or more control signals to each of the switching arrangements to control connection of the respective 2R resistance to either a positive side of a differential signal or the negative side of the differential signal.

The above embodiments are to be understood as illustrative examples of the invention. Further embodiments of the invention arc envisaged.

For example, embodiments comprise a resistor tuning network comprising a resistor ladder, wherein the resistor ladder comprises a plurality of resistor rungs each comprising a first resistance and a second resistance, and wherein the second resistance of each resistor rung in the plurality is connected to a switching arrangement, a respective switching arrangement being controllable to connect the respective second resistance to either a positive side of a differential signal or the negative side of the differential signaL For example, embodiments comprise a resistor tuning network comprising a resistor ladder, wherein the resistor ladder comprises a plurality of resistor rungs each comprising a first resistance and a second resistance, and wherein the second rcsistancc of one or more resistor rungs in thc plurality is conncctcd to a switching arrangement, a respective switching arrangement being controllable to connect the respective second resistance to either a positive side of a differential signal or the negative side of the differential signal. Hence, in some embodiments, some, but not each of the resistor rungs comprise a switching arrangement which controllably connects the respective second resistance to either a positive side of a differential signal or the negative side of the differential signal.

The term embodiment herein should be taken to mean an example and the term embodiments herein should be taken to mean some examples, such that description of an embodiment or embodiments refers to some embodiments, but not necessarily all embodiments.

It is to be understood that any feature described in relation to any one embodiment may be used alone, or in combination with other features described, and may also be used in combination with one or more features of any other of the embodiments, or any combination of any other of the embodiments. Furthermore, equivalents and modifications not described above may also be enipioyed without departing from the scope of the invention, which is defined in the accompanying claims.

Claims

Claims 1. A resistor tuning network comprising a resistor ladder, wherein the resistor ladder comprises a plurality of resistor rungs each comprising a first rcsistancc and a sccond rcsistancc, and wherein the second resistance of each resistor rung in the plurality is connected to a switching arrangement, a respective switching arrangement being controllable to conncct thc rcspcctivc sccond rcsistancc to cithcr a positivc sidc of a diffcrcntial signal or the negative side of the differential signal.
2. A resistor tuning network according to claim 1, wherein an input of the resistor ladder is provided with a signal voltage, whcrcin thc negativc and positive sidcs of thc differential signal arc gcncratcd on thc basis of replicas of thc signal voltage.
3. A resistor tuning network according to claim 2, wherein the positive side of the differential signal is generated by multiplying a replica of the signal voltage by an attenuation parameter and the negative side of the differential signal is generated by multiplying a replica of the supply voltage by minus the attenuation parameter.
4. A rcsistor tuning network according to any prcccding claim, wherein the switching arrangement of each resistor rung is controllable to connect the respective second resistance to either the positive side of the differential signal or the negative side of the differential signal via application of one or more control signals to the respective switching arrangement.
5. A resistor tuning network according to any preceding claim, wherein the second resistance of each resistor rung is connected to the respective switching arrangement on the opposite side of the second resistance to the first resistance of the respective rung.
6. A resistor tuning network according to any of claims I to 4, wherein the second resistance of at least one resistor rung in the plurality comprises two second resistance elements connected in parallel, wherein one of the two second resistance elements comprises first and second resistance portions, wherein the other of the two second resistance elements comprises first and second resistance portions, and whcrein the switching arrangcment of the at least one resistor rung is connected between the first and second resistance portions of the one of the two second resistance clemcnts and between the first and second resistance portions of the other of the two second resistance elements.
7. A resistor tuning network according to any preceding claim, comprising a shunt resistor connected in parallel with the resistor ladder.
8. A resistor tuning network according to any preceding claim, comprising at least one always on switch connected in series between the first resistance of at least a first resistor rung in the plurality and the first resistance of at least a second resistor rung in the plurality, the at least first resistor rung being located next to the at least second resistor rung in thc resistor ladder.
9. A resistor tuning network according to claim 8, wherein the on-resistance of the at least one always on switch is approximately half of the on-resistance of the switching arrangement of the at least first resistor rung andlor the switching arrangement of the at least second resistor rung.
10. A resistor tuning network according to any preceding claim, wherein the resistor tuning network comprises first and second differential inductors arranged to generate the positive side of the differential signal and the negative side of the differential signal respectively.
11. A resistor tuning network according to any of claims 3 to 10, wherein the attenuation paramctcr compriscs a valuc bctwccn 0 and 1.
12. A resistor tuning network according to any of claims 3 to 11, comprising a resistive divider configured to provide the attenuation parameter.
13. A resistor tuning network according to any of claims 3 to 11, wherein the attenuation parameter varies at least in dependence on the switching arrangements.
14. A resistor tuning network according to according to any preceding claim, wherein the first resistance is different to the second resistance.
15. A resistor tuning network according to according to any prcccding claim, whcrein thc rcsistor ladder comprises an R/2R rcsistor laddcr, thc first rcsistance comprising a resistance of value R, the second resistance comprising a resistance of value 2R.
16. A duplexer comprising one or more resistor tuning networks according to any of claims Ito 15.
17. An antenna tuner comprising one or more resistor tuning networks according to any of claims I to 15.
18. A radio-frequency semiconductor integrated circuit (RFIC) comprising onc or more resistor tuning nctworks according to any of claims ito 15.
19. A chipset comprising one or more resistor tuning networks according to any of claims Ito 15.
20. A radio frequency (RF) transceiver comprising one or more resistor tuning networks according to any of claims Ito 15.
21. A device comprising one or more resistor tuning networks according to anyofclaims ito 15.
22. A method of manufacturing a resistor tuning network according to any of claims Ito 15.
23. A method of operating a resistor tuning network, the resistor tuning network comprising a resistor ladder, the resistor ladder comprising a plurality of resistor rungs each comprising a first resistance and a second resistance, the second rcsistancc of each resistor rung in thc plurality bcing connected to a switching arrangement, the method comprising; applying one or more control signals to each of the switching arrangements to control connection of the respective second resistance to either a positive side of a differential signal or the negative side of the differential signal.
24. Apparatus substantially in accordance with any of the examples as described herein with reference to and illustrated by the accompanying drawings.