GB2513383A

GB2513383A - Divider stage for modular programmable frequency divider

Info

Publication number: GB2513383A
Application number: GB1307485.1A
Authority: GB
Inventors: Albrecht Johannes Schiff
Original assignee: Toumaz Microsystems Ltd
Current assignee: Toumaz Microsystems Ltd
Priority date: 2013-04-25
Filing date: 2013-04-25
Publication date: 2014-10-29
Also published as: GB201307485D0

Abstract

A frequency divider stage, for use in a frequency dividing chain (figure 2) with feedback from subsequent stages, divides by two in all division cycles if the programming input P is a 0. When P is a 1 the stage divides by three for one division cycle after the carry input Mod in from a subsequent stage has been asserted, and divides by two in the other division cycles. A multiplexer 202 selects one of the Q and Qbar outputs of the input toggling flip-flop 201. Division by three is effected by toggling the multiplexer output after the carry input Mod in has been asserted so that a transition in the multiplexer output is delayed (B2, figure 6) by one cycle of the input clock.Â Only one flip-flop 201 is driven by the clock input, which allows a reduction in flip-flop and driver power consumption.Â The frequency divider may be used in a phase-locked loop.Â

Description

Divider Stage for Modular Programmable Frequency Divider

Field of the invention

The present invention relates to a divider stage for a modular programmable frequency divider. More particularly, the invention relates to a divider stage for a frequency divider incorporating a plurality of cascaded divider stages.

B ac kcj round Frequency dividers in a Phase Locked Loop (PLL) often have programmable divide ratios in order to allow the PLL to be locked to different frequencies. The most common type of programmable frequency divider consists of several divider stages, each of which can perform either division by 2 or division by 3 on a clock input, depending on the value of control inputs. Division by 2 creates an output signal with one rising edge for every two rising edges of the input signal, and division by 3 creates an output signal with one rising edge for every three rising edges of the input signal.

An example of a divider stage is shown in Figure 1. The divider stage takes a clock input from either the previous stage or the clock input to the frequency divider, and outputs a signal which is then passed to the next stage, or the output of the modular frequency divider. When the programming input P of a stage is set to 0 the stage divides by two, and when the programming input P is set to 1 the stage divides by three once when Mod in" for the stage is set to 1 at the rising edge of the output for the stage. Mod out" is set to (Mod in) AND (NOT Output) or equivalently (Output) NOR (NOT Mod in), and is passed to the previous stage's Mod in". The signal transferred from Mod out" to the Mod in" of the previous stage is referred to as the "carry signal".

Several such stages can be arranged into a modular divider as shown in Figure 2. The divider of Figure 2 includes three cascaded stages, each of which behaves in the same way as that shown in Figure 1. Figure 3 is a graph showing the voltages present at various points in the divider where the programming inputs P1 and P3 of the first and last stages are set to 1, and the programming input P2 of the middle stage is set to 0.

Although it is not apparent from Figure 3, the falling edge of the carry signal from the next stage AG occurs slightly after the rising edge of the output to the first stage A2 after which the first divider stage is required to divide by three. Therefore the input carry signal to the first stage A6 will always be high at the rising edge of the output to the first stage A2 when the first stage divides by three, as required.

With a three stage divider, the input signal can be divided by any integer value between 2° and 2-1 (8 and 15). The total division ratio X (i.e. output frequency = input frequency / X) is 23+N, where N is the divider number. The divider number is the binary number obtained by taking the bit sequence defined by the programming inputs P of the divider stages, with the final divider stage being the most significant bit and the first divider stage being the least significant bit. In terms of the divider 100 of Figure 2, the divider number is 4P3 + 2P2 + P1 = 101 (binary) = 5 (decimal), and so the division ratio of the divider in Figure 2 is 13. In general, a divider composed of K individual stages with respective programming inputs P1 (first) to PK (final), each of which divides by 2 or 3, has a divider number N and division ratio X given by: N=:rr, X=2K+N, and a minimum and maximum division ratio X given by: 2K «=x«=2K+ 1 To understand how the three stage frequency divider works, it is important to note that the carry bit at each stage is high immediately before the rising edge of the output signal of the final stage. The input carry bit to the first and second stages (Mod In) can therefore be thought of as a marker indicating the approaching rising edge of the final stage output. If the programming input P of a stage is set to 0, the stage performs frequency division by 2 on the output of the previous stage (or the input to the modular divider, in the case of the first stage). Division by 2 creates an output signal with one rising edge for every two rising edges of the input signal. If the programming input P of a stage is set to 1, the stage performs frequency division by 3 once, and then performs frequency division by two, i.e. the divider stage outputs one rising edge for the first three rising edges of the input to the stage after the input carry signal (Mod in) is set to 1, and then outputs one rising edge for every two rising edges of the input to the stage thereafter (until the input carry signal is next set to 1).

As an example, consider the operation of the divider of Figure 2 when it is set to divide by 13. Referring to Figure 4, assume that the period of the input clock signal Al is 1.

The aim is to generate a signal at the output of the final stage having a period 13 (i.e. 13 times the period of the input clock signal). When the programming input P of a stage is set to 0, the output signal for the stage has one rising edge for every two rising edges of the input signal to the stage (a divide by two" operation, e.g. A2 to A3).

Therefore, the period between each pair of adjacent rising edges of the output is the period between a rising edge and the second following rising edge of the input to the stage. When the programming input P of a divider stage is set to 1, the divider stage outputs one rising edge for the first three rising edges of the input to the stage, and then outputs one rising edge for every two rising edges of the input to the stage thereafter (a "divide by three" operation, followed by "divide by two" operations, e.g. Al to A2), i.e. the first stage output A2 can either have periods between adjacent rising edges 2,2,2,2,2,2.... (divide by two) or 3,2,2,2,2,2.... (divide by three followed by divide by two). All of the stages reset at the rising edge of the output to the final stage A4, i.e. stages with the programming input P set to 1 perform a division by 3 immediately following the rising edge of the final output A4. The reset is triggered by the carry signal.

When the target final output A4 period is 13, the output of the first stage A2 must be have periods between adjacent rising edges of the form 3,2,2,2,2..., otherwise any combination of the first stage output A2 cannot result in an odd number. Therefore the programming input P1 of the first stage must be set to 1. The periods between adjacent rising edges in the output for the second stage A3 can therefore either be 5,4,4... (division by two) or 7,4,4... (division by three followed by division by two). Since the target period is 13, the output must be 5,4,4..., and so the programming input P2 for the second stage must be set to 0.

The output of the final stage A4 requires a period of 13. This can be clearly obtained by combining the first three periods between adjacent rising edges of the output of the second stage A3, since 5+4+4=13, and so the programming input P3 to the final stage mustbesettol.

In the divider stage of Figure 1, the input from the previous stage is required to drive two flip-flops. Each flip-flop adds a load to the input signal which is dependent on the frequency of the signal. Therefore, in a divider operating on a high frequency signal, the load on the input can be very high. This requires the use of high power inputs, and/or prevents the use of other components which would add load to the input, such as capacitors for reducing noise. In high frequency dividers, the flip-flops are also required to have very fast response times (significantly less than one clock cycle), and such flip-flops generally require more power than slower flip-flops.

Summary

According to an aspect of the present invention, there is provided a frequency divider stage for use in a frequency divider comprising a plurality of cascaded frequency divider stages. The frequency divider stage is programmable to perform one of a divide by two and a divide by three operation. The frequency divider stage comprises a D-type flip flop with a clock input, GIk, a main input, D, a non-inverted output, 0, and an inverted output, 0. The D-type flip-flop has 0 coupled to D, and CIk configured to receive one of an input to the frequency divider or an output of a preceding frequency divider stage. The frequency divider stage further comprises a multiplexer (202) coupled to both 0 and 0 and being able to switch one of 0 and 0 onto an output of the multiplexer. The frequency divider stage further comprises a controller with a first input for receiving a programming signal and a second input for receiving a carry signal from a subsequent frequency divider stage. The controller is configured, when the programming signal is set to a first state, to cause the multiplexer to continuously provide at its output one of 0 and 0 and, when the programming signal is set to a second state, to switch the output of the multiplexer between 0 and 0 in dependence upon the carry signal.

The controller may be configured, when the programming signal is set to the second state, to cause the multiplexer to switch the output a predetermined period of time, Tmod, after an edge of the carry signal. Tmod may be selected so as to cause the output to switch during an edge of 0.

The controller may comprise a further flip-flop having an output coupled to a switching input of said multiplexer. The further flip-flop may be a D type flip flop having a clock input, C1k0, a main input, D0, and an inverted output, 00. The D type flip hop s Q coupled to D0, and C1k0 configured to receive an input from a combination of the programming signal and the carry signal.

According to a further aspect of the invention, there is provided a frequency divider comprising at least one frequency divider stage according to the first aspect.

According to a further aspect, there is provided a phase locked loop comprising a frequency divider according to the previous aspect.

Brief Description of the Drawings

Figure 1 is a circuit diagram of a divider stage of a modular divider according to the

prior art;

Figure 2 illustrates schematically a modular divider comprising a series of cascaded divider stages; Figure 3 shows the voltages present at various points on the divider of Figure 2 when using the divider stage of Figure 1; Figure 4 is a graph showing the operation of the modular divider of Figure 2; Figure 5 is a circuit diagram of a divider stage according to an exemplary embodiment; and Figure 6 shows the voltages present at various points in the divider of Figure 2 when using the divider stage of Figure 5.

Description

To reduce the power consumption and capacitive load of each divider stage of a frequency divider, a divider stage is proposed in which a second flip-flop is not connected to the input clock signal, and so the capacitive load on the input clock signal is effectively halved. As the input signal is a high frequency signal, this approach can significantly lower the power consumption of the signal generator. In the case where the signal generator is a voltage controlled oscillator (VCO), this allows higher frequency, lower power consumption, and/or greater noise reduction by the addition of higher 0 capacitors. An embodiment of such a stage is shown in Figure 5. A graph of the voltages present at various points of a multi-stage divider 100 according to Figure 2 incorporating the stage of Figure 5 as the first 101 and second 102 stages is shown in Figure 6. The final stage 103 is a conventional divider stage (e.g. according to Figure 1) for reasons that are explained below.

The concept behind the divider stage 200 of Figure 5 is that the divider stage is only required to divide by 3 once after the input carry signal is set to 1. This division can be achieved by switching between the Q and Q outputs of a 2-divider 201 at the point where the active output is switching from 0 to 1 (shown by the dashed line in Figure 6).

As the outputs of the flip-flop take a finite time to switch from 0 to 1, there will be a period of time when both 0 and 0 are below the threshold voltage for the circuit (i.e. the voltage at which a wire is considered to be at logic state 1). During this time both Q and 0 will be at logic state 0. This can be seen in graph 81 of Figure 6. If the output is changed from 0 to 0 while Q is transitioning from 0 to 1 (and a from 1 to 0), then the output will remain at 0 through the transition, and the resulting waveform will be the same as if a divide by three operation had been performed. The same applies if the output is changed from 0 to 0 while 0 is transitioning from 0 to 1. The change in output may not be made while the currently active output is transitioning from 1 to 0 unless further processing is used to remove the spike" caused by the short period where both 0 and 0 are below the threshold voltage (and therefore the output must be 0). In order to illustrate the concept behind the embodiment, a flip-flop with a high switching time has been used in the first frequency divider stage so that the slope of the edges in the signal can be clearly seen. In a real application, this switching time could be reduced significantly, provided there is still a short period where both 0 and 0 are 0. If the switching characteristics are such that there is a period where both 0 and O are 1 (instead of a period where both are 0), then the above logic applies with 1 and 0 switched, and the change in output should be made on the falling edge of the active output.

The switch between the 0 and 0 outputs is performed by a multiplexer (MUX, 202).

The multiplexer receives a control signal on its sel" input, 0 and 0 are each connected to one of the Ii and 12 inputs of the multiplexer, and the output of the multiplexer is set to Ii or 12 depending on the control signal. For example, if the control signal is set to 0, the output equals Ii, and if the control signal is set to 1, the output equals 12. In order to smooth out the final signal, the output from the multiplexer B2 may be passed through an inverter, which will result in a clean digital signal A2.

The control signal provided to the multiplexer is generated by a control circuit (203).

This control circuit takes Mod in" received from the subsequent stage (see Figure 1) and the programming input P as its inputs. The multiplexer is required to switch the output of the stage from 0 to 0 (or vice versa) a certain period of time after the rising edge of the carry signal (shown as Tmod in Figure 6). This delay is constant and can be determined by simulation or simple measurement of the circuit. The control circuit is configured to cause the multiplexer to switch between the 0 and 0 outputs at the time Tmod after the rising edge of the carry signal.

By way of example, the control circuit may be implemented as a D-type flip-flop 204. In order to distinguish the terminals of the control flip-flop from the division flip-flop 201, the terminals of the control flip-flip will be given a subscript C. This is for the purposes of clarity only, and does not necessarily reflect any difference in the structure of the f lip-lops. The control flip-flip takes the carry bit as its clock input, and has its 00 output coupled to its D0 input (as shown in Figure 5). Either 0 or 0 may be used as the control signal for the multiplexer, and the multiplexer is configured to provide 0 when the output of the control circuit is 1, and 0 when the output is 0 (or vice versa). The flip-flop and multiplexer can be chosen to ensure that the delay between the carry bit changing and the output switching is the same as the required Tmod, which allows the use of a flip-flop which is slow compared to the flip-flop which performs the division.

Optionally, additional components may be used to delay the signal in addition to the delay inherent in the flip-flop and multiplexer, allowing greater freedom in the choice of flip-flop.

Other control circuits are possible, for example the combination (Mod in) AND P may be used as the clock input to a T-type flip-flop with the T input set high, or the control circuit may be implemented in a microprocessor.

A frequency divider employing the above approach may be implemented in a variety of ways. For example, the frequency divider may be implemented as a single integrated circuit comprising multiple frequency divider stages according to the above approach.

As a further example, each frequency divider stage may be implemented on a single integrated circuit, and the frequency divider may be constructed from multiple such integrated circuits. As a yet further example, each frequency divider stage may be constructed from multiple components (e.g. integrated circuits containing logic gates, or individual transistors). In any case, as the control circuit is triggered by an edge of the carry signal, a frequency divider stage according to the above embodiments may not be suitable for use as the final stage in a modular frequency divider, as the carry signal coming into the final stage is constant. Therefore, in a frequency divider implementing the above approach, the final stage may use an alternative design such as that of Figure 1. As the final stage is generally the lowest frequency stage, it is also the stage with the lowest power consumption, and so a frequency divider implementing the above approach will still require considerably less power than prior art modular programmable frequency dividers.

Triggering the control circuit on the carry signal ensures that the modular nature of the frequency divider is maintained. Because the input is only required to drive a single flip-flop, and the carry signal is generally lower frequency than the input, the power consumption of the divider stage presented above is greatly reduced in comparison to

prior art divider stages.

Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. In particular, any logic expression or use of a flip-flop should be taken to include all equivalent logic expressions and any circuit which performs in the same manner as the flip-flop described. For example, an edge triggered JK flip-flop where J=NOT K is equivalent to a D flip-flop, and circuits making use of this should be considered to be within the scope of the above disclosure. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS: 1. A frequency divider stage for use in a frequency divider comprising a plurality of cascaded frequency divider stages, the frequency divider stage being programmable to perform one of a divide by two and a divide by three operation and comprising: a D-type flip flop (201) having a clock input, CIk, a main input, D, a non-inverted output, 0, and an inverted output, 0, the D-type flip-flop having 0 coupled to D, and having CIk configured to receive one of an input to the frequency divider or an output of a preceding frequency divider stage; a multiplexer (202) coupled to both 0 and 0 and being able to switch one of 0 and 0 onto an output of the multiplexer; and a controller (203) having a first input for receiving a programming signal and a second input for receiving a carry signal from a subsequent frequency divider stage, the controller being configured, when the programming signal is set to a first state, to cause the multiplexer to continuously provide at its output one of 0 and Q and, when the programming signal is set to a second state, to switch the output of the multiplexer between 0 and 0 in dependence upon the carry signal.
2. A frequency divider stage according to claim 1, wherein the controller is configured, when the programming signal is set to said second state, to cause the multiplexer to switch the output a predetermined period of time, Imod, after an edge of the carry signal.
3. A frequency divider stage according to claim 2, wherein Tmod is selected so as to cause the output to switch during an edge of 0.
4. A frequency divider stage according to any preceding claim, wherein the controller comprises a further flip-flop (204) having an output coupled to a switching input of said multiplexer.
5. A frequency divider stage according to claim 4, wherein the further flip-flop (204) is a D type flip flop (204) having a clock input, CIk, a main input, D0, and an inverted output, Q0, the D type flip flop having Q0 coupled to D0, and having C1k0 configured to receive an input from a combination of the programming signal and the carry signal.
6. A frequency divider comprising at least one frequency divider stage according to any one of the preceding claims.
7. A phase locked loop comprising a frequency divider according to claim 6.