GB2511446A - Memory sharing by processors - Google Patents
Memory sharing by processors Download PDFInfo
- Publication number
- GB2511446A GB2511446A GB1408707.6A GB201408707A GB2511446A GB 2511446 A GB2511446 A GB 2511446A GB 201408707 A GB201408707 A GB 201408707A GB 2511446 A GB2511446 A GB 2511446A
- Authority
- GB
- United Kingdom
- Prior art keywords
- processor
- interfaces
- request
- processors
- evaluation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000011156 evaluation Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Abstract
It is proposed a method implemented by a logic of a computer memory control unit, wherein the control unit comprises at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N ⥠2 non-cooperative processors via the second interfaces, and the logic is operatively coupled to said first and second interfaces. The method comprises receiving (S10), via said second interfaces, a request to access data of the main physical memory from a first processor of the set, evaluating (S20) if a second processor has previously accessed the data requested by the first processor, and deferring (S30) the request from the first processor when the evaluation (S20) is positive, or, granting (S40) the request from the first processor when the evaluation is negative.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP11194116 | 2011-12-16 | ||
PCT/IB2012/056562 WO2013088283A2 (en) | 2011-12-16 | 2012-11-20 | Memory sharing by processors |
Publications (3)
Publication Number | Publication Date |
---|---|
GB201408707D0 GB201408707D0 (en) | 2014-07-02 |
GB2511446A true GB2511446A (en) | 2014-09-03 |
GB2511446B GB2511446B (en) | 2016-08-10 |
Family
ID=47520195
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1408707.6A Active GB2511446B (en) | 2011-12-16 | 2012-11-20 | Memory sharing by processors |
Country Status (6)
Country | Link |
---|---|
US (1) | US9183150B2 (en) |
JP (1) | JP6083714B2 (en) |
CN (1) | CN103999063B (en) |
DE (1) | DE112012004926B4 (en) |
GB (1) | GB2511446B (en) |
WO (1) | WO2013088283A2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170192886A1 (en) * | 2014-07-31 | 2017-07-06 | Hewlett Packard Enterprise Development Lp | Cache management for nonvolatile main memory |
US9781225B1 (en) * | 2014-12-09 | 2017-10-03 | Parallel Machines Ltd. | Systems and methods for cache streams |
US9535606B2 (en) | 2014-12-22 | 2017-01-03 | Intel Corporation | Virtual serial presence detect for pooled memory |
CN105868134B (en) * | 2016-04-14 | 2018-12-28 | 烽火通信科技股份有限公司 | More mouthfuls of DDR controllers of high-performance and its implementation |
CN106484521A (en) * | 2016-10-21 | 2017-03-08 | 郑州云海信息技术有限公司 | A kind of data request processing method and device |
US11409673B2 (en) * | 2019-02-14 | 2022-08-09 | Intel Corporation | Triggered operations for collective communication |
US11409655B2 (en) * | 2019-03-01 | 2022-08-09 | Canon Kabushiki Kaisha | Interface apparatus, data processing apparatus, cache control method, and medium |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6418515B1 (en) * | 1998-04-22 | 2002-07-09 | Kabushiki Kaisha Toshiba | Cache flush unit |
US6438660B1 (en) * | 1997-12-09 | 2002-08-20 | Intel Corporation | Method and apparatus for collapsing writebacks to a memory for resource efficiency |
US6829683B1 (en) * | 2000-07-20 | 2004-12-07 | Silicon Graphics, Inc. | System and method for transferring ownership of data in a distributed shared memory system |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5950228A (en) | 1997-02-03 | 1999-09-07 | Digital Equipment Corporation | Variable-grained memory sharing for clusters of symmetric multi-processors using private and shared state tables |
US6397306B2 (en) | 1998-10-23 | 2002-05-28 | Alcatel Internetworking, Inc. | Per memory atomic access for distributed memory multiprocessor architecture |
US6636950B1 (en) | 1998-12-17 | 2003-10-21 | Massachusetts Institute Of Technology | Computer architecture for shared memory access |
US7233998B2 (en) | 2001-03-22 | 2007-06-19 | Sony Computer Entertainment Inc. | Computer architecture and software cells for broadband networks |
US7380085B2 (en) * | 2001-11-14 | 2008-05-27 | Intel Corporation | Memory adapted to provide dedicated and or shared memory to multiple processors and method therefor |
US7032079B1 (en) | 2002-12-13 | 2006-04-18 | Unisys Corporation | System and method for accelerating read requests within a multiprocessor system |
KR20050061123A (en) * | 2003-12-18 | 2005-06-22 | 삼성전자주식회사 | Data control circuit in the double data rate synchronous dram controller |
US20060112226A1 (en) * | 2004-11-19 | 2006-05-25 | Hady Frank T | Heterogeneous processors sharing a common cache |
US7386687B2 (en) | 2005-01-07 | 2008-06-10 | Sony Computer Entertainment Inc. | Methods and apparatus for managing a shared memory in a multi-processor system |
JP5021978B2 (en) * | 2006-08-11 | 2012-09-12 | エヌイーシーコンピュータテクノ株式会社 | Multiprocessor system and operation method thereof |
JP2008176612A (en) * | 2007-01-19 | 2008-07-31 | Nec Electronics Corp | Multiprocessor system |
US8386750B2 (en) * | 2008-10-31 | 2013-02-26 | Cray Inc. | Multiprocessor system having processors with different address widths and method for operating the same |
WO2011060366A2 (en) | 2009-11-13 | 2011-05-19 | Anderson Richard S | Distributed symmetric multiprocessing computing architecture |
-
2012
- 2012-11-20 WO PCT/IB2012/056562 patent/WO2013088283A2/en active Application Filing
- 2012-11-20 CN CN201280062000.3A patent/CN103999063B/en not_active Expired - Fee Related
- 2012-11-20 GB GB1408707.6A patent/GB2511446B/en active Active
- 2012-11-20 DE DE112012004926.8T patent/DE112012004926B4/en active Active
- 2012-11-20 JP JP2014546677A patent/JP6083714B2/en not_active Expired - Fee Related
- 2012-12-07 US US13/707,801 patent/US9183150B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6438660B1 (en) * | 1997-12-09 | 2002-08-20 | Intel Corporation | Method and apparatus for collapsing writebacks to a memory for resource efficiency |
US6418515B1 (en) * | 1998-04-22 | 2002-07-09 | Kabushiki Kaisha Toshiba | Cache flush unit |
US6829683B1 (en) * | 2000-07-20 | 2004-12-07 | Silicon Graphics, Inc. | System and method for transferring ownership of data in a distributed shared memory system |
Also Published As
Publication number | Publication date |
---|---|
JP2015504205A (en) | 2015-02-05 |
CN103999063B (en) | 2016-10-05 |
GB201408707D0 (en) | 2014-07-02 |
WO2013088283A3 (en) | 2013-11-07 |
JP6083714B2 (en) | 2017-02-22 |
DE112012004926T5 (en) | 2014-08-14 |
WO2013088283A2 (en) | 2013-06-20 |
US20130159632A1 (en) | 2013-06-20 |
DE112012004926B4 (en) | 2023-12-07 |
GB2511446B (en) | 2016-08-10 |
CN103999063A (en) | 2014-08-20 |
US9183150B2 (en) | 2015-11-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
746 | Register noted 'licences of right' (sect. 46/1977) |
Effective date: 20160929 |