GB2508162A - Reconfigurable predicate logic computer architectures - Google Patents

Abstract

A predicate logic processor executes predicate logic instructions. These instructions may include multi-valued logic, controlled not, Fredkin gate and dual rail operations. The processor may use a field programmable gate array with predicate logic to process data. The array may be reconfigured during operation using a control unit or in response to a particular instruction. Alternatively, the processor may have a reconfigurable arithmetic and logic unit in its data path. This may be reconfigured based on the instruction in the instruction register. The processor may have an accumulator, another data register and an instruction register. All the registers may be 16-bit registers. The processor may have a register, which operates with a base other than binary, such as quaternary. The processor may be used in artificial intelligence applications.

Description

Variable Predicate Logic Computer Architectures This invention relates to novel computer (processor) architectures for artificial intelligence and other applications.

Today artificial intelligence data processing methods are the main tool in cybernetic systems, signal and video processing, large amount data processing, etc. The main logic of these artificial intelligence systems is the predicate one. Predicate logic is the superior one regarding several practically used logical systems. In known digital computing machines, it is emulated only in a programmable way. Meanwhile, the predicate logic is a higher-order one, and it is a natural logic of intelligence, mathematics, etc. in comparison with the Boolean one. Another issue is that our modern society is overloaded by digital information flows. We can expect that this tendency will continue in the future, too. These digital information flows are processed by conventional computers (processors) using mainly Boolean logic.

Many mobile and distributed applications need more faster computing and flexible hardware devices, and the use of heterogeneous multi-processor architectures. The Field Programmable Gate Arrays (FPGA5) combined with the microprocessors are known as an effective mean to improve the flexibility issues of processors, but, based on the Boolean logic, they only emulate the artificial intelligence operations.

A predicate logic processor (PLP) is known which predicate logic unit (FLU) performs operations over predicates instead of single bits. See, e.g., G. Kouzaev and A. Kostadinov, "Predicate gates, components and a processor for spatial logic", Journal of Circuits, Systems, and Computers, Vol.19, No. 7, pp.1517 -1541, World Scientific Publishing Company, 2010. A predicate is a logical sentence to which a pair of wires is assigned and jointly processed. This micro-parallelism allows to speed-up performing the operations of artificial intelligence. Unfortunately, these operations are time and resource consuming realized on the von Neumann or another architecture principle.

The proposed invention consists of three designs.

The first of them is on a new predicate FPGA integrated with a modified predicate logic processor (predicate logic processor variant). It is assigned for partially reconfigurable predicate data processing.

The second design is for the same purpose, but some essential changes are made in comparison with the known processors and proposed above. The controlling predicate logic processor develops the data stream and instruction stream as a predicated flow to control a fine-grain predicate FPGA without using a control unit. It decreases the power consumption and the time delay in partially reconfiguration of a predicate FPGA. This design technique provides run-time partial reconfiguration of a fine-gran predicate FPGA.

The third design is based on the fact that the predicate logic is the superior logic regarding some particulars using the two-wire signaling. Among them are the Boolean logic, 4-valued (multi-valued) logic spatially mapped on two-wire set, pseudo-quantum logic modeled by two-wire set, reversible logic where one wire is for input signal, dual-rail (differential) logic and its variants for increased security applications. See, e.g., D. Sokolov, J. Murphy, A. Bystrov and A. Yakovlev, "Improving the security of dual-rail circuits", Proceedings of Cryptographic Hardware and Embedded Systems -CHES 2004: 6th International Workshop, Cambridge, MA, USA, August 11-13, pp. 282-297, 2004.

The proposed design allows to change the logic style according to the type of data on-the-fly, i.e. relates to variable logic processors.

The invention will now be described solely by way of example and with reference to the accompanying drawings in which: Figure 1 shows a block diagram illustrating the first architecture of the invented variable predicate logic computer, Figure 2 shows a block diagram illustrating the second architecture of the invented variable predicate logic computer, Figure 3 shows a block diagram illustrating the third architecture of the invented variable predicate logic computer, Figure 3a shows a block diagram illustrating the architecture of the third variable predicate logic processor (VPLP) datapath, Figure 3b shows a block diagram illustrating the architecture of the third VPLF control unit, Figure 3c shows a diagram illustrating the inputs, outputs and electronic circuit of the program counter which is a part of Figure 3b, Figure 3d shows a diagram illustrating the inputs, outputs and electronic circuit of the reset circuit which is a part of Figure 3.

Figure 1 illustrates the first variable predicate logic computer architecture 1 which consists of a predicate logic processor variant 2 and a specially designed predicate field programmable gate array (PERGA) 5 performing operations with the predicated signals and partially reconfigured by the control unit 4. Similarly to the conventional FPGA, it allows a higher potential in achieving increased performance for a range of artificial intelligence and other applications. The elementary reconfigurable logic block (ERLB) of the PFPGA performs several predicate logic operations. It consists of predicate logic gates, a multiplexer and a flip-flop. The multiplexer has a 3-bit select line. With these three bits, it is possible to configure the ERLB as predicate NOT, predicate OR and predicate AND logic functions. A flip4lop is added to create sequential circuits. Memories 3 and 6 are used to store the corresponding digital information.

Figure 2 shows the second variable predicate logic computer architecture 7 consists of object-oriented predicate logic processor (OOPLP) 8 and partially reconfigurable during run-time fine-grain PERGA 10. OOPLP 8 generates data and instruction signals unified into a single flow called the super predicate one. The fine-grain PFPGA is configured by the above-mentioned instruction flow. The elementary reconfigurable logic block is the same as one used in the first variable predicate logic computer architecture 1. The only difference is that flip-flop is not implemented. The goals of this invention are to increase the reconfiguration speed and decrease the power consumption of the first variable predicate logic computer architecture 1.

The first goal is reached by the use of a fine-grain PERGA which exclude the excessive memory elements from the PFPGA cells. The power consumption and time-delay are decreased by direct control of the FFPGA by instructions unified with the predicate data as it is known from the rekursiv or object-oriented processors. See, e.g., D. Harland, "Rekursiv: Object-oriented Computer Architecture (Ellis Horwood Series in Computers and Their Applications)", Ellis Horwood, 1988. By this manner, the control unit is excluded, and the power consumption is reduced. The decreased power consumption, the low configuration time, and increased speed are advantages of this new architecture.

Memories 9 and 11 are again used to store the corresponding digital information.

Figure 3 illustrates the third variable predicate logic computer architecture (VPLCA) 12 realized according to this invention. This VPLCA has been designed using VHDL (Very High Speed Integrated Circuit Hardware Description Language). Variable predicate logic processor workable prototype has been implemented and tested on FPGA board and corresponding CAD (Computer-Aided Design) tool. The designed processor has a low-power consumption and good performance. Different VPLF architectures are realized.

They are optimized for low-power consumption as well as for higher performance.

In the proposed variable predicate logic processor, the variable predicate arithmetic logic unit works in seven different logic regimes. Among them are Boolean logic, multi-valued (multiple-valued) logic, pseudo-quantum logic, reversible logic, dual-rail (differential) logic and its modifications using single spacer (all-zeroes state) or dual spacers (all-zeroes and all-ones states). There are implemented instructions which are typical operations for the above-mentioned logic types.

The variable predicate logic computer architecture 12 includes a reset circuit 22, datapath 23, control unit 24, and memory 25. Reset circuit 22, datapath 23 and control unit 24 are basic building blocks of the variable predicate logic processor.

Another part of the variable predicate logic computer architecture 12 is the interface. The interface includes signal lines 13 through 21.

Signal lines 13 and 14 interface clock and reset signals to the various components of VPLCA 12.

Signal lines 15 and 17 are used as an input and output of the converted multi-valued numbers to variable predicate logic computer architecture 12. See, e.g., V. Patel and K. Gurumurthy, "Arithmetic Operations in Multi-Valued Logic", International Journal of VLSI Design & Communication Systems, pp.21 -32, Academy & Industry Research Collaboration Center (AIRCC), 2010.

The rest signal lines couple the VPLP to the memory. The signal lines 19 and 20 are utilized to perform read and write memory operations. The signal lines 21 are the address bus of the variable predicate logic processor. The signal lines 16 and 18 are the data bus of the VPLP.

Figure 3a illustrates variable predicate logic processor datapath 23. The datapath 23 is responsible for the manipulation of data and it is consists of storage units such as register B 34, accumulator A 36, multi-valued register 38, and combinational units such as data multiplexer 35, variable predicate arithmetic logic unit (VPALU) 37.

Data multiplexer 35 selects data either from the memory 33 or from the multi-valued signal lines 15 and sends the selected input data to the VPALU 37. This data multiplexer 35 has a select line which is number 32.

Variable predicate arithmetic logic unit 37 performs arithmetic and logical operations. The invention extends these operations with operations applicable to several different types of logics. The corresponding instructions have been implemented. Table 1 shows the VPLP instruction set.

Table 1

Command (Instruction) Semantic Arithmetic and load instructions INCA Increment the content of the accumulator A DECA Decrement the content of the accumulator A INCB Increment the content of the register B DECB Decrement the content of the register B LDB Load constant into register B LBA Load the register B with the content of the accumulator A LAB Load the accumulator A with the content of the register B Multi-valued logic instructions INM Load the accumulator A with the converted quaternary to binary number OUTM Load the multi-valued register with the processed binary number Pseudo-quantum logic instructions CN B Controlled-NOT (CNOT) operation SWB Swap operation Reversible logic instruction FGO Fredkin gate operation Dual-rail (differential) logic instructions DOR Dual-rail OR operation DAND Dual-rail AND operation Dual-rail (differential) logic instructions using single spacer (all-zeroes state) TNOT Dual-rail NOT operation TOR Dual-rail OR operation TAND Dual-rail AND operation Dual-rail (differential) logic instructions using dual spacers (all-zeroes and all-ones states) SNOT Dual-rail NOT operation SOR Dual-rail OR operation SAND Dual-rail AND operation Additional information about VPLP instruction set is followed on the next lines.

INCA -VFALLJ 37 increments by one the accumulator A 36. The result is stored into accumulator A 36.

DECA -VPALU 37 decrements by one the accumulator A 36 content. The result is stored into accumulator A 36.

INCB -The variable predicate logic controller 47 sets a logic one on the datapath 23 signal line number 27. As a result, the content of register B 34 is incremented by one.

DECB -The variable predicate logic controller 47 sets a logic one on the datapath 23 signal line number 26. As a result, the content of register B 34 is decremented by one.

[DB -The content of the program counter 49 is incremented by one. From the next memory cell (each memory cell is 16-bits wide) is fetched the 16-bit operand. With VPALU 37 pass-through operation the operand is transferred into the register B 34.

[BA -The 16-bit operand is initially stored in the accumulator A 36. With VPA[U 37 pass-through operation the operand is transferred into the register B 34.

[AB -The register B 34 contains initially the 16-bit operand. With VPA[U 37 pass-through operation the operand is transferred into the accumulator A 36.

INM -The 16-bit value (converted quaternary to binary number) is placed on VP[CA 12 signal lines 15. With VPA[IJ 37 pass-through operation the operand is loaded into the accumulator A 36.

OIJTM -The 16-bit operand is initially stored in the accumulator A 36. With the datapath 23 load signal line 31 the operand is transferred into the multi-valued register 38.

CNB -The register B 34 holds two 8-bit operands. The result according controlled-NOT (CNOT) truth table is kept again in the register B 34.

SWB -The register B 34 holds two 8-bit operands. The result according SWAP truth table is kept again in the register B 34.

FGO -The first 8-bit operand is stored in the most significant byte of accumulator A 36 and the second two 8-bit operands -in register B 34. The result according Fredkin gate truth table is kept again in the same registers (one 8-bit result in the most significant byte of accumulator A 36 and two 8-bit results in register B 34).

DOR -The two 8-bit dual-rail operands are loaded into accumulator A 36 and register B 34. The result of dual-rail OR logic operation is kept again in the same registers.

DAND -The two 8-bit dual-rail operands are loaded into accumulator A 36 and register B 34. The result of dual-rail AND logic operation is kept again in the same registers.

TNOT, TOR and TAND instructions perform dual-rail NOT, OR and AND logic operations.

The operand and the result for TNOT instruction are located in accumulator A 36 only. The operands and the results for TOR and TAND instructions are located in accumulator A 36 and in register B 34. It is implemented a single spacer (all-zeroes state).

SNOT, SOR and SAND instructions perform dual-rail NOT, OR and AND operations. The operand and the result for SNOT instruction are located in accumulator A 36 only. The operands and the results for SOR and SAND instructions are located in accumulator A 36 and in register B 34. It is implemented dual spacers (all-zeroes and all-ones states).

The VPALU 37 control bits are signal line 29 which is 5-bit wide. The different VPALU 37 operations depend on the control bits. Accumulator A 36 and register B 34 are provided by this invention to aid in the execution of extended instructions in VPALU 37.

Accumulator A 36 is a 16-bit register. It usually contains one of the two operands involved in the concrete operation. The second operand is read by memory or by register B 34. The result of the operation is also stored into accumulator A 36 either into register B 34 or into both of them. The load signal line 30 is applied to load/store operations.

Register B 34 is a 16-bit one. It plays the same role as the accumulator A 36 in some instructions. The added letter B in the assembly instruction names specifies the use of the register B 34 in their execution. Accumulator A 36 and register B 34 are both used in some operations, too.

The clock 13 and reset 56 signal lines are distributed to other datapath 23 components except data multiplexer 35. The decrement 26, increment 27 and load 28 signal lines are applied to register B 34 inputs only.

Multi-valued register 38 is a 16-bit one. It stores the processed multi-valued data. The load signal line 31 is used In order to be performed this operation. The multi-valued register 38 output signal line is number 17. For different type of data excluding multi-valued one, the output signal line of the datapath 23 is number 18.

Figure 3b shows the internal architecture of the VPLP control unit 24. The control unit 24 issues appropriate signals in order to be executed the current command. The instruction fetching and decoding is also performed by the control unit 24. It is consists of storage units such as instruction register 48, program counter 49, and a variable predicate logic controller 47 composed of combinational and sequential building blocks.

Instruction register 48 is a 16-bit one. It holds the current instruction previously fetched from the memory. Every instruction is encoded in eight bits. The reset 56 and clock 13 signal lines are distributed to other control unit 24 components.

Variable predicate logic controller (VPLCI) 47 is the main component of the control unit 24.

VPLCI 47 is realized as finite state machine (FSM). Every state of the FSM corresponds to a different instruction and it is encoded in eight bits. Depends on the decoded instruction, different control signals are issued and sent to the datapath 23 or control unit 24 components. These signals are required for proper instruction execution.

Memory data is transferred to the instruction register 48 using signal lines 16. These data is sent also to the signal lines 46.

The VPLCI 47 output signal line 39 selects VPALU 37 operation.

Memory read or write operation is performed when 19 or 20 signals are applied.

Select signal line 40 is coupled to the data multiplexer 35 signal line 32.

The next output signal lines are load signals. The signal line 41 is set to load the accumulator A 36. The signal line 42 is used to load multi-valued register 38. The next signal line 43 is applicable to register B 34.

When logic one is set to 44 or 45 control signals, it is possible to increment or decrement the value of the register B 34.

Program counter 49 is an 8-bit register. It holds the address of the current instruction. The program counter 49 needs to be incremented by one count for every instruction or two instructions. The output of the program counter 49 is the address bus 21.

Figure 3c illustrates the program counter 49 implementation. The electronic circuit consists of adder 53 and a register 54. The register 54 is incremented by one using the adder 53, and corresponding signal line 51. It is used the input operand equal to value one and input signal line 52. The signal lines 13 and 50 are clock and reset signals.

Figure 3d shows the VPLP reset circuit 22. The building blocks are two D flip-flops 57 and 59. The clock 13 and reset 14 signal lines are connected to both flip-flops numbers 57 and 59. D input 55 of the first D flip-flop 57 is coupled to the ground. Its output signal line 58 is connected to the D input of the second flip-flop 59. The output of the reset circuit 22 is the signal line 56.

Reset circuit 22 synchronize asynchronous VPLCA 12 reset signal 14. It is avoided any potential problems with asynchronous reset signal 14 using this reset circuit 22.

Memory 25 stores the program code and data.

Claims (6)

1. Claims 1. A variable predicate logic computer architecture which consists of a predicate logic processor variant and a specially designed predicate field programmable gate array performing operations with the predicated signals and partially reconfigured by the control unit.
2. 2. A variable predicate logic computer architecture consists of an object-oriented predicate logic processor and partially reconfigurable during run-time fine-grain predicate field programmable gate array.
3. 3. A variable predicate logic computer architecture comprising variable predicate logic processor, and memory.
4. 4. A variable predicate logic processor according to claim 3 comprising reset circuit, a datapath, and control unit.
5. 5. A variable predicate logic processor according to claim 4, in which datapath has a variable predicate arithmetic logic unit.
6. 6. A variable predicate arithmetic logic unit according to claim 5, in which several types of logic operations especially Boolean logic, multi-valued (multiple-valued) logic, pseudo-quantum logic, reversible logic, dual-rail (differential) logic and its modifications using single spacer (all-zeroes state) or dual spacers (all-zeroes and all-ones states) have been implemented.