GB2504110A

GB2504110A - Data slicing level and timing adjustment

Info

Publication number: GB2504110A
Application number: GB201212760A
Authority: GB
Inventors: Richard David Simpson; Pulkit Khandelwal
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2012-07-18
Filing date: 2012-07-18
Publication date: 2014-01-22
Also published as: GB201212760D0

Abstract

Attenuation and spread caused by a lossy transmission channel to a pulse signal waveform, having a peak h0 at t0 and sampled at Unit Intervals (UI), is measured and compensated for by dynamically adjusting the slicing threshold (21) and the timing at which the peak is sampled (22) according to the size of the eye diagram (55) at whose corners (51-54) extra test samples are taken. The data slicing level 21 and time 22 together define a data slicing point 20. Points 51 & 52 determine the slicing threshold and offset, while points 53 & 54 determine the clock recovery period and offset.

Description

DATA SLICING LEVEL AND TIMING ADJUSTMENT

The present invention relates to clock and data recovery from a transmitted signal.

Background

As is well-known in the art, data pulses sent along transmission lines are subject to various processes which cause them to spread, affecting the signal level within neighbouring pulses, the latter effect being termed inter-symbol interference.

Figure 1 shows the effect of a channel in a typical example on a received pulse (typically representing one bit of data) originally lasting one UI (unit interval) (the scale of the horizontal axis) and having a pulse height of 1 unit (on the scale of the vertical axis) when it was transmitted. In this particular example, it can be seen that there is an excursion of the received pulse below zero. This is due to the pre-emphasis applied to the pulse before transmission, which comprised a negative pulse following the positive pulse. The channel is lossy -it attenuates the pulse, with different frequencies being attenuated more than others, and the different frequencies also have different velocities, leading to spreading of the pulse.

Figure 2 shows the outcome of sending the same pulse down a less lossy channel than in Figure 1. Here, the final pulse has spread less and has a larger amplitude. By convention in these diagrams, time zero is the time at which the pulse is sampled and is typically close to the maximum of the received pulse.

The received amplitude at that time zero is given the symbol h. The amplitude of the pulse at earlier and later times spaced at 1 UI intervals are labelled h2, h1, and h-, h2 etc. Figure 3 illustrates a known method for reoovering the olook and data from the received signal. Owing to the spread of the pulses, the shape of the waveform received during any particular interval of 1 UT is dependent on the history of the previous few bits (in theory, of course, the relevant history is infinite but the influence of earlier bits declines with time) Figure 3 shows the traces of the received waveform for where the previous bit is a +1 pulse; for the case where the previous bit is a -1 pulse the diagram would be reflected at the zero level on the vertical axis. (The notation +1 and -l is used here because the pulses transmitted, which typically represent logical ls and Os, are usually arranged to have such equal and opposite amplitudes about a reference level.) In the centre of the upper half of Figure 3 there is a space free of waveform traces, which is known as the eye, above which pass the traces when the present bit is +1 and below which pass the traces for when the present bit is a -1.

A typical circuit for reading a data signal is shown in Figure 4. To read the data, i.e. discriminate between a +1 and -1, the data signal 1 is passed to a comparator 2, which compares it to a data slicing reference level 5 which is set at the amplitude +h1 for the channel, the level +h-being represented by the dotted horizontal line in the eye in Figure 3, so that the traces passing above that level are recognised as a +1 and those below as a -1. (h can be measured for the channel or guessed appropriately.) As noted above, the diagram of Figure 3 is for the case where the previous bit was a +1. For the case where the previous bit was a -1, another comparator 3 is provided to compare the level of the data signal to -h 16. In the circuit, both of these comparators are physically provided and are used to compare the level of the data signal of all data bits to their respective reference levels. However, the recovered previous data bit, held in clocked latch 4, is then used to determine which of the comparators is selected to provide its output as the value for the current bit, which is latched into latch 4 at the next clock pulse, the multiplexer 6 making the selection. (Latch 4 is the first bit of a shift register 7 which holds recent recovered data bits for use by the circuits downstream. Multiplexer 6 is marked with the logical values I and C of the data from latch 4 in respect of the input that each selects; those values of course correspond respectively to the +1 and -1 levels on the channel.) A problem with this method, the inventors have realised, is that there can be a relatively small noise margin, in this case to the left (earlier side) of the sampling point (represented by the smaller arrow pointing down and to the left) , whereas there is an unnecessarily large noise margin to the other side (represented by the larger arrow pointing up and to the right) Tn this known method of Figure 3, the timing of the data slicing point (the process of determining which is known as clock recovery) is set to coincide with the zero crossing of bits in which the previous bit is a +1 and the current bit is a -1. As is known in the art a comparator 9 (Figure 4) slices the waveform at the zero level (marked with the horizontal dashed line in Figure 3) at the data slicing time (that being the zero time on the horizontal axis of Figure 3) storing the result in a clocked latch O, and early/late detector 8 is responsive to that result value by adjusting the phase of the local clock produced by clock 11, which is in turn used to control the sampling time (of all three comparators), according to the following rule. If the result of the zero level sample is a -Fl it means that the sample point is early, and so the phase of the local clock is delayed. If the sample is a -1 then the sample is taken late and so the phase of the local clock is advanced.

In order not to respond too quickly to the effeots of other kinds of noise this feedback loop is low pass filtered, by low pass filter 11 between the early/late detector B and the clock 11, so that the sampling point follows the low frequency jitter.

A typical use of the prior art circuits and the invention described below is in the communication of data between circuit boards, e.g. via a backplane, in a multi-board system, e.g. a high performance computer.

SUMMARY OF THE INVENTION

The present invention provides methods and apparatus as defined in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGURE 1 is a graph illustrating the effect of a lossy channel on a transmitted pulse, FIGURE 2 is a graph illustrating the effect of a relatively less lossy channel on a transmitted pulse, FIGURE 3 is an eye diagram illustrating an eye diagram illustrating a prior art method of data slicing and clock recovery.

FIGURE 4 is a circuit diagram of a prior art circuit for carrying out that method, FIGURE 5 is an eye diagram illustrating a first exemplary method according to the invention of data slicing and clock recovery, FIGURE 6 is a circuit diagram of a first exemplary cirouit acoording to the invention for carrying out the first exemplary method, FIGURE 7 is an eye diagram illustrating a second exemplary method according to the invention of data slicing and clock recovery, and FIGURE 8 is a circuit diagram of a second exemplary circuit according to the invention for carrying out the second exemplary method.

EXAMPLES

Figures 5 and 7 illustrate preferred methods of the invention for setting a data slicing point 20 within the eye and Figures 6 and 8 show example circuits for carrying out the methods. In contrast to the prior art method described above, these methods differ in two ways. First, they adjust dynamically the actual data slicing level 21 (which was static, at h-, in the prior art method) and second they improve on the clock recovery method.

Both the example methods make use of extra test samples taken at points in the eye relative to the data slicing point 20 which are examined to adjust both the slicing level 21 and the timing 22 of that point. Ihe extra test samples are for simplicity each in the form of whether the level of a waveform exceeds a particular threshold defined by an associated reference level or not. (A more complex approach could, for example, take into account the difference in level between the test sample threshold and waveform level but the simple above below test is preferred so that the implementation will be a simple and fast circuit.) In Figure 5, the corners 51, 52, 53 and 54 of a diamond shape 55 in the eye represent four points at which those extra test samples are made. Samples 51 and 52 are taken at the same time as the actual data sample 20 at levels above and below that and are used to set the threshold, or "slicing", level 21 for the recovered data itself, i.e. the level used to discriminate between +1 and -1 in the incoming data waveform. The timing for the data sample 20 and the samples 51 and 52 are, in this example, determined by the improved clock recovery method to be described later, which involves test sample points 53 and 54.

(Or alternatively the timing may be set by known methods, for example as described earlier above.) The sample points 51 and 52 are preferably offset symmetrically in signal level (usually voltage) about the dynamically set data slicing level 21 by an amount that is dynamically adjusted by the circuit. The larger diamond 54 shows an example of one particular equilibrium position that the diamond might adopt.

The initial references for samples 51 and 52 have zero offset from the data sampling level 21, which itself has an initial level of +h1 in a typical case (and again hi may be measured for the channel or easily guessed at) . The smaller diamond 56 shows an intermediate position in which the data slicing level is at +h1 and the reference levels of the sampling points 51 and 52 are at an intermediate offset (of 0.07, on the dimensionless scale of Figure 7) above and below the data slicing level.

After the initialisation at the point noted above, the method then proceeds as follows, samples 51 and 52 are taken at the initial positions and adjustments to the data slicing level 21 and the offset therefrom in level of the two sampling points 51 and 52 are then made for the next samples depending on whether a collision between the diamond at those particular corners and the signal waveform is detected and on which of the corners has the collision. This process of testing and adjustment is repeated.

A collision is recognised if the value, produced by the comparator, of the sample at corners 51 or 52 is different from that produced by the data slicer using level 21, which means that the corner is on the other side, from the centre of the diamond 20, of the trace of the received signal waveform.

The actions are taken are as set out in the table below: (a) No collision at (i) The data slicing level 21 is not upper corner 51 or adjusted.

lower corner 52 (ii) The offset in level of the corners 51 and 52 from the data slicing level 21 is increased.

(b) Collision at (i) The data slicing level 21 is the upper corner 51 lowered.

(ii) The offset in level of the corners 51 and 52 from the data slicing level 21 is reduced.

(c) Collision at (i) The data slicing level 21 is the lower corner 52 raised.

(ii) The offset in level of the corners from the data slicing level 21 is reduced.

Table 1

For ease of comparison, the method of Figure 7, particularly the parts of the method for adjustment of the data slicing level 21, is described next.

Tn Figure 7 the corners 71, 72, 73, 74 of the central rectangle represent four points at which the samples are made, by the circuit, of the incoming data signal, which samples are used to determine the sampling, or "slicing", level 21 for the recovered data itself, i.e. the level used to discriminate between +1 and -1. The circuit slices the data signal at a level indicated by the horizontal dotted line 21 at a time of zero 22 in the diagram (which time is determined by the improved clock recovery method to be described later, or alternatively for example by the known method described above), i.e the data is taken at the centre 20 of the rectangle.

The four test sampling points are symmetrically disposed in time about that time = zero point by a fixed interval, the interval between the time = zero point and the sampling point being typically 0.1 UI. (The unit of the timebase marked on Figure 7 is UI/48.) The test four sampling points are offset symmetrically in signal level (usually voltage) about the dynamically set data slicing level 21 by an amount that is also dynamically adjusted by the circuit. The larger rectangle 75 shows an example of one particular equilibrium position that the rectangle might adopt.

The initial position is with zero offset from the data sampling level 21, with that level being typically initially +h. The smaller rectangle 76 shows an intermediate position in which the data slicing level is at +h and the levels of the test points are at an intermediate offset (of 0.05 on the dimensionless scale of Figure 7) above and below the data slicing level 21.

After the initialisation at the position noted above, the method then proceeds as follows. Samples are taken at each of the four corners of the rectangle. Different sets of adjustments to the slicing level 21 and the offset of the four test points are then made depending on whether a collision between the rectangle and the signal waveform is detected and on which of the corners has the collision.

A collision is recognised if the value of the test sample at a corner 71, 72, 73, 74 is different from that produced by the data slicer at level 21, which means that the corner is on the other side of the trace from the centre 20 of the rectangle.

(Note that the collision is not recognised unless the previous bit was a +1 which is of course what defines the eye of Figures 3, 5 and 7. The method of course could also be used in the other eye for which the previous bit s a -1.) The actions are taken by the circuit are as set out in the table below: (a) No collision (I) The data slicing level 21 is not adjusted.

(ii) The offset in level of the corners 71, 72, 73, 74 from the data slicing level 21 is increased.

(b) Collision at (i) The data slicing level 21 is either of the lowered.

upper corners (ii) The offset in level of the 71, 72 corners 71, 72, 73, 74 from the data slicing level 25 is reduced.

(c) Collision at (i) The data slicing level 21 is either of the raised.

lower corners (ii) The offset in level of the 73, 74 corners 71, 72, 73, 74 from the data slicing level 25 is reduced.

Table 2

In both the methods of Figure 5 and Figure 7, the action (a) causes the system to look for collisions, with action (a) (ii) advancing the test point toward the traces, so that information about the position of the traces may be gained. Zctions (b) (i) and (c) (i) move the data slicing level 21 away from a trace causing a collision, which has the result that the diamond or rectangle reaches a position 75, 55 where two diagonally opposite corners of the diamond or rectangle are close to the traces. (In the method of Figure 7, four test samples are taken because the shape of the eye depends on the nature of the particular transmission channel in use and so the other pair of diagonally opposite oorners from that touching the traces in Figure 7 may be active for other eye shapes. For the diamond only the upper and lower corners 51 and 52 are used for the setting of the slicing level 21.) Actions (b) (ii) and (c) (ii) reduce the height of the diamond or rectangle so that it can accommodate the eye becoming smaller. Doing that at the same time as adjusting the data slicing level 21 is advantageous because the corner that has caused a collision is further pulled away from the trace more probably allowing another approach by action (a) rather than another collision occurring immediately and because at the opposite corner reducing of the height of the diamond or rectangle moves the opposite corner towards the traces but the reduction of the offset works in the opposite direction from that by moving that corner away from the traces.

(If the magnitude of the two adjustments is the same, which is the preferred method, then the corner does not move.) Moving the opposite corner significantly towards the traces during (b)/(c) is not desired because it could immediately cause a collision there rather than by the approach to the trace of action (a) In Figures 5 and 7 the diamond and rectangle are shown fortunately positioned so that as they expand vertically each comes into contact with traces above and below at the same time, i.e. the initial guess for the data slicing level 21 was correct. However if the initial guess for that was not correct, the data slicing level 21 is moved up or down by actions (b) and/or (o) until it is at a position where top and bottom opposite corners of the diamond, or top right and bottom left (or alternatively in some cases top left and bottom right) of the rectangle, collide with the traces.

Also in the preferred methods the adjustments made in action (a) are quite small compared to those in (b) and (c) . This means that the ratio of the step sizes determines the bit error rate of the corner having the collisIon -i.e. how often the sample differs from that found at the actual data point at the centre of the square or diamond. E.g. if the size of step (b) is 1000 times bigger than the size of step (a), the method finds and settles around the level that has a 1 error per 1000 bits for that corner. (If the steps were equal it would settle at the position of 50% errors.) It is desired however to detect where errors are just starting to occur, hence the much greater ratios used for the step sizes typically.

The resultant position (the larger diamond or rectangle 55, 75) provides equal noise margins between the data slicing point at the centre of the rectangle and the bounding traces of the eye.

This is advantageous because if one margin is smaller than the other then bit errors are more likely on that side and the number of errors overall is increased.

A particular typical example of values for the sizes of the adjustments is as follows. The data and corner samples are taken at each UI and in case (a) the adjustment made to the offset is 0.lmV/1024 ( l05mV) whereas in oases (b) and (o) the adjustment to both the data slicing level 25 and the offset is 0.lmV.

The methods of Figures 5 and 7 could be used without actions (a) (ii) and b(ii) and (o) (ii) but then the testing point diamond or rectangle would be of fixed size, for example just smaller than the size of the eye, but it would not be optimal.

The above preferred methods can be used with any method of clock recovery including known ones. Such a olock recovery method will usually allow for jitter since transmitted data signals generally suffer from that. Note however that the timing of the samples derived by the known method of Figure 3 is not ideal so if the clock recovery method of that Figure (i.e. sampling for early/late detection at CV when the previous bit is +1 and the current bit is -1) is used a delay should preferably be added when being used with the data slicing adjustment methods of Figures 5 and 7 to the clock so determined. For example for the method of Figure 7 using the timing point of Figure 3 the four sample rectangle would expand until both the left sample points meet the traces, which would not give egual horizontal noise margins.) A better position for the rectangle in Figure 3 would be more to the right in the centre of the eye, which is where it is shown in Figure 7.

However the other aspect of the invention also improves clock recovery. Preferred examples of this improved clock recovery method are also provided by the exemplary methods of Figure 5 and 7. Like the prior art method early/late detection based on a comparator to follow jitter is used. However instead the method uses a different one of the traces; namely the comparator is set to slice the incoming signal, preferably at the same time in the unit interval (UI) as the actual data slicer 2, 3, but against a timing reference level 28 of h--he-h-or a nearby level. While this sample is taken during each UI it is only used for early/late detection when the data in the previous, current and next bits are +l,-l,-1, since it is only the traces 29 for that pattern which cross that level during a time near the centre of the eye. (The method would work egually with the other eye for which the trace tested would be that of -1,+l,+l and the slicing level would be around -(h--h-h1) .) The timing reference level 28 testing the +1,-l,-l traces for early/late detection and adjustment of the timing could be determined by measurement etc for the channel and used for example in a circuit like that of Figure 4 as the reference level for comparator 9. However the preferred exemplary methods of Figures 5 and 7 make a further improvement, which is as follows. When a collision takes place further actions are taken as set in the tables below: For the method of Figure 5: (d) Collision at the right (i) Timing reference later oorner 53 of the level 28 is raised diamond (ii) The offset in time from the data sampling time 22 to the later corner 53 and the earlier corner of the diamond 54 is decreased (e) Collision at the left (i) Timing reference earlier corner 54 of the level 28 is lowered diamond (ii) The offset in time from the data sampling time 22 to the later corner 53 and the earlier corner of the diamond 54 is decreased (f) No collision at either (i) The offset in time the later corner 53 or the from the data sampling earlier corner of the time 22 to the later diamond 54 corner 53 and the earlier corner of the diamond 54 is increased

Table 3

For the method of Figure 7: (d) Collision at either of (1) Timing reference level the right (later) corners 28 is raised of the rectangle 72, 74 (e) Collision at either of (i) Timing reference level the left (earlier) corners 28 is lowered of the rectangle 71, 73

Table 4

When there is a collision at the right hand corner 53 of the diamond or at one of the right hand side corners 72, 74 on the rectangle this suggests that the diamond or rectangle is near the traces to the right of the eye so perhaps the sampling points of the diamond or rectangle and hence the actual data sampling point 21 are late, so the action is raise the timing slicing level 29. This then causes the basic jitter following timing loop to advance the local clock that sets the timing of the samples because that makes the intersection between the level 29 and the +l,-1,-1 traces earlier in the bit interval, which in turn causes the data sample and the timing sample to have the same value, -1, (the +1,-1,-1 trace slopes down at this point) which is taken to indicate that the sampling points are late and in response the local clock is advanced. (Note that if there are collisions to the right and left sides at the same time both up and down adjustments are made to the level 29 so the overall adjustment is zero.) Similarly, when there is a collision at the left corner 54 of the diamond or at one of the left hand side sampling points 71, 73 on the rectangle this suggests that the diamond or rectangle is near the traces to the left of the eye so perhaps the sampling points of the diamond rectangle and hence the actual data sampling point are early, so the action is lower the timing slicing level 28. This then causes the jitter following timing loop to retard the local clock because that makes the intersection between the level 29 and the +1,-1,-1 later earlier in the bit interval, which in turn causes the data sample to have the value -1 whereas the t±ming sample is +1, which is taken to indicate that the sampling points are early and in response the local clock that sets the timing of the samples is retarded.

In the method of Figure 7 the rectangle is of fixed width. That is the offset in time between the test points 71, 72, 73 and 74 and the data point 20 is a constant.

However in the method of Figure 5 the width of the diamond is initialised at zero but expands in width, by increasing the offset in time between points 53 and 54 and the data point 20, when there are no collisions at points 53 and 54 (action (f) in Table 3) -The diamond then shrinks in width when there is a collision at 53 or 54 (actions (d) (ii) and (e) (ii) in Table 3) In the method of Figure 5, although the rectangle is of fixed with, a good timing point can be found, however, because when it shrinks in height following a collision, there is room for the rectangle inside the eye for the rectangle to move earlier or later.

The feedback loop that adjusts the timing slicing level is arranged to operate more slowly than the basic jitter following loop (8, 9, 10, 11,12 of Figures 3, 5 and 7) because it is not used to react to jitter (which is catered for already with its own loop) but to variations in the lossiness of the channel.

Although these can occur in a transmission system over time, the method is used particularly to adjust at start-up to the lossinees of a particular system. Different lossiness causes changes in the slope of the traces to change. In particular they become less steep as the lossiness increases. Consider the +1,- 1,-l trace. When it is less steep it reaches the timing slicing level later and so this will retard the clock to later in the eye, which moves the sampling rectangle later so it collides with the right of the eye. The response of the method as noted above is to raise the timing slicing level which results in the timing being advanced and hence the rectangle is brought back to the centre of the eye.

Figures 6 and 8 are exemplary circuits for carrying out the methods of Figures 5 and 7 respectively. The exemplary circuits of Figure 6 and 8 have similar basic components to that of Figure 4, but have further components and modifications as described below for carrying out the adjustment of the data slicing level and the timing of the data slicing.

The circuit of Figure 6 comprises test comparators 601, 602, 603 and 604 and respective latches 611, 612, 613, 614 for sampling the data waveform 1, each comparator receiving that at its positive input and having its output connected to the data input of its respective latch. The latches respectively produce the samples 51, 52, 53 and 54. The outputs of those are processed by reference control unit 605 and timing control unit 606 to control the positions of the test sample and also the data sample 20.

Reference ccntrol unit 605 receives samples 51 and 52 and the data sample 20 from the same bit interval to which it compares them as described above. It also receives the previous data sample 30 so that it can check that the previcus bit was a +1 before comparing the test samples to the data sample (since in this example the checking is done for the eye diagram of Figure and the cther eye fcr the previous sample being -l is not checked as this would reguire more comparators and the one eye is sufficient) The reference control unit 605 receives samples 51 and 52 and produces a first control word to control data a slicing level digital to analogue converter (DAC) 607 whose output, the data slicing level 21, is supplied as the reference (negative) input of comparators 2, 3, 603 and 604, and a second control word to control offset DAC 608 to provide the offset level for samples 51 and 52. Analogue subtractor 620 subtracts the offset level from the data slicing level and supplies the resultant to the reference input of comparator 602, while analogue adder 621 adds the offset level to the data slicing level and supplies the resultant to the reference input of comparator 601.

Timing control unit 606 supplies a control word to timing DAC 609 whose output is supplied as the reference to comparator 9, which takes the samples for the early/late loop (8, 9, 10, 11, 12) . The timing control unit 606 receives samples 53 and 54 as well as the data sample 20 to which it compares them as described above. It also receives the previous data sample 30 so that it can check that the previous bit was a +1 before comparing the test samples to the data sample.

The local oscillator 11 supplies its clock signal to the clock inputs of latches 4, 611 and 612 and to phase interpolators 621 and 622, which respectively produces clock signals of phase offsets to the basic clock signal 22 which are respectively supplied to time latches 613 an 614 to produces samples 53 and 54. These offsets are controlled by control words produced by timing control unit 606 so that samples 53 and 54 are earlier and later than the data sample by the amount determined by the exemplary method of Figure 5.

Analogue adder 622 sets the reference level for the comparator 3 which takes the data for the other eye. It adds the output of the DAC 607 to the incoming waveform 1 before with the result being applied to the positive input of the comparator. This turns the positive slicing level into a negative one of the same magnitude since the negative input of the comparator is tied to the zero, or ground, level.

The exemplary circuit of Figure 8 has the same DICs and adders and subtractcr but the connections of the comparators and latches to the reference levels and clocks to reflect the different pattern of sampling points in Figure 7. The control functions of the reference control unit and the timing control unit are also different to reflect the exemplary method described in relation to Figure 7 and accordingly have been renumbered 805 and 806 accordingly. These control units now receive all four test samples 7, 72, 73 and 74 (as well as the current and previous data samples 20 and 30) since collisions at any one of them, according to the actions for the exemplary method of Figure 7, cause a change in the timing and the slicing levels -The comparators have been renumbered 801, 802, 803 and 804 and their respective latches 811, 8:2, 813 and 814 and they respectively produce test samples 71, 72, 73 and 74. Comparators 801 and 802 receive the sum of the outputs of the data slicing and offset DACs as their reference input, while comparators 803 and 804 receive the difference. Latches 811 and 813 are timed by the clock from a phase interpolator 821 and latches 812 and 814 are timed by the clock from phase interpolator 822. The phase interpolators respectively provide fixed phase offsets from the basic clock signal 22 so that the samples they time are respectively earlier and later than the data sample point 20 by a fixed amount in accordance with the exemplary method of Figure 7.

The exemplary circuits of Figures 6 and 8 described above include comparators and latches to sample all four test points during the same bit interval. That is not necessary however. The use of a sampler, being a comparator and associated latch, can be time divided between the test points. So there need only be one such sampler for the test samples. (There could also be more than one but less than the number of test points.) A time division unit (not shown) can then control the connections between the outputs of the DACs and the comparator(s) and between the latches and the clock signals output by oscillator 11 and the phase interpolators to produce a particular one(s) of the test samples for that bit period. The time division unit also informs the reference control and timing control units which test sample is currently being generated. These units then store the recent values of the test samples, for example the most recent of each test sample and make their decisions based on each.

Note that it is not needed to take a test sample for all bit intervals providing the eye, or eyes being used to eyes being used (in the examples the eye used is that for which the previous bit is +1) Tn a particular example of time dividing a single test sampler is as follows. This may be used in the methods of Figures 5 and 7.

The bit rates in many data transmission systems are so high that the time it takes for a DAC to settle is much longer than 1 UI.

Therefore in this example data slicing level and offset DACs (607, 608), and if necessary phase interpolators (621 and 622), are first programmed for a particular one of the test sample points 51, 52, 53, 54, 71, 72, 73, 74, and then 2k UI are allowed to pass to allow the DADs to settle. Next for 8k UI that particular test point is sampled (as well the data point 20) with the rules (a) and (b) being applied. Again the data is being produced very guickly so the sampled data points 20 and test samples are each gathered into 8 bit bytes which are presented in parallel to logic (e.g. the reference control unit and timing control unit of Figures 6 and 8) which processes them according to the rules.

For the timing adjustment this is low pass filtered by the control word which sets the level (e.g. as applied to timing DAC 609) being a held in counter which incremented or decremented when the method of the invention indicates that the level should be changed. However the counter has lower order bits (for example 6 bits out of 13) that are not presented to the DAD, so a net total of 64 collisions, either to the early side or the late side, are made with the eye before the actual timing slicing level 29 is adjusted.

The same procedure is then applied to each of the other three test points in turn.

The diamond and rectangle test patterns of the examples above are easy to generate with simple circuitry but other patterns are possible. As noted above just two samples may suffioe in some oases to meet both the level and timing adjustments. (Those would be (A) one above and early and one below and late or (B) one above and late and one below and early.) However more generally a plurality of points spread in the eye at the oorners of a polygon inside the eye may be used. The polygon withdraws from the eye when a oorner collides with the eye and adjusts the level in oases where the oorner is above or below the data sampling point (or possibly for only one or more of each of those corners above less than all of the plurality and one or more of those below) and adjusts the timing when a corner collides with the eye where the corner involved is earlier or later than the data sampling point (or possibly for only one or more of each of those corners earlier less than all of the plurality and one or more of those later)

Claims

C LA I N S1. A method of adjusting a data slicing reference level comprising: receiving a signal waveform comprising a series of intervals, comparing the waveform at a data slicing time in each interval to a data slicing reference level and outputting the result as a recovered data value, the data slicing reference level and the data slicing time defining a data slicing point, comparing the waveform at a plurality of testing points, each having an associated reference level with which the waveform is compared and an associated point in time in the interval at which the comparison is made, each of those comparisons being made in certain ones of the intervals, the plurality of testing points incThding a set of one or more first testing points having its associated reference level above, in signal level, the data slicing reference level, and set of one or more second testing points having its associated reference level below, in signal level, the data slicing reference level, and in response to any of the comparisons for the plurality of testing points indicating that that testing point is on the other side of the signal waveform from the data slicing point in the same interval, adjusting the level of the data slicing level in a direction away from the reference level of the said testing point on the other side of the signal waveform.
2. A method as claimed in claim 1 further comprising: in response to any of the comparisons for the plurality of testing points indicating that that testing point is on the other side of the signal waveform from the data slicing point in the same interval, adjusting the reference level of one or more of the testing points in a direction towards the data slicing level, and, in other cases, adjusting the reference level of one or more of the testing points in a direction away from the data slicing reference level.
3. A method as claimed in claim 2 wherein the adjusting step of the reference level of one or more of the testing points in a direction towards the data s1icng level is smaller than the adjusting step of the reference level of one or more of the testing points in a direction away from the data slicing reference level.
4. A method as claimed in claim 1 or claim 2 or claim 3, wherein the plurality of testing points comprises a first testing point having its associated reference level above, in signal level, the data slicing point, and a second testing point having its associated reference level below, in signal level, the data slicing point.
5. A method as claimed in claim 4 wherein both the first and second testing points are at the same point in time in the interval as the data slicing po:nt.
6. A method as claimed in claim 1 or claim 2 or claim 3, wherein the plurality of testing points comprises four testing points: one testing point hav±ng a reference level above, in signal level, the data slicing point and being at a point in time in the interval before the data slicing point, one testing point havThg a reference level above, in signal level, the data slicing point and being at a point in time in the interval after the data slicing point, one testing point havThg a reference level below, in signal level, the data slicing point and being at a point in time in the interval before the data slicing point, one testing point having a reference level below, in signal level, the data slicing point and being at a point in time in the interval after the data slicing point.
7. A method as claimed in claim 6 wherein two of the four testing points are at the same level above the data slicing point and two are at the same level above the data slicing point.
8. A method as claimed in claim 6 or claim 7 wherein two of the four testing points are at the same point in time in the interval before the data slicing point and two are at the same point in time in the interval after the data slicing point.
9. Apparatus for carrying out the method of any one of claims 1 to 8 comprising: a local oscillator connected to provide a clock signal to define the data slicing time and the test point comparison times, a data sampler connected to receive the signal waveform, one or more test samplers connected to receive the signal waveform and the associated reference levels and to compare those at times defined by the local clock signal, a control unit responsive to the data samples produced by the data sampler and test samplers to control the levels of the data slicing level or of the data slicing level and the associated reference levels.
10. A method of recovering a clock signal comprising: receiving a data waveform comprising a series of intervals, comparing the waveform at a data slicing time in each interval to a data slicing reference level and outputting the result as a recovered data value, the data slicing reference level and the data slicing time defining a data slicing point, comparing, during at least some intervals, the data waveform at a timing slicing point in time in the interval to a timing slicing level and adjusting in response to that the data slicing and timing slicing times, the method further comprising: comparing the waveform at a plurality of testing points, each having an associated reference level with which the waveform is compared and an associated point in time in the interval at which the comparison is made, each of those comparisons being made in certain ones of the intervals, the plurality of testing points including a set of one or more first testing points having its associated comparison time later than the data slicing time, and set of one or more second testing points having its associated comparison time earlier than the data slicing time, and in response to any of the comparisons for the plurality of testing points indicating that that testing point is on the other side of the signal waveform from the data slicing point in the same interval, adjusting the timing slicing reference level in a direction that results in the timing of the test point on the other side of the waveform from that data point being moved in a direction toward the data point.
11. A method as claimed in claim 10 comprising: in response to any of the comparisons for the plurality of testing points indicating that that testing point is on the other side of the signal waveform from the data slicing point in the same interval, adjusting the timing of one or more of the testing points in a direction towards the data slicing time, and, in other cases, adjusting the timing of one or more of the testing points in a direction away from the data slicing time.
12. A method as claimed in claim 10 or claim 11, wherein the plurality of testing points comprises a first testing point which is at a point in time in the interval before the data slicing point and a second testing being at a point in time in the interval after the data slicing point
13. A method as claimed in claim 12 wherein both the first and second testing points have the same reference level.
14. A method as claimed in clainl3 wherein the level of the first and second testing points is at the data slicing level.
15. A method as claimed in 10 or claim 11, wherein the plurality of testing points comprises four testing points: one testing point havThg a reference level above, in signal level, the data slicing point and being at a point in time in the interval before the data slicing point, one testing point havThg a reference level above, in signal level, the data slicing point and being at a point in time in the interval after the data slicing point, one testing point having a reference level below, in signal level, the data slicing point and being at a point in time in the interval before the data slicing point, one testing point having a reference level below, in signal level, the data slicing point and being at a point in time in the interval after the data slicing point.
16. A method as claimed in claim 15 wherein two of the four testing points are at the same:evel above the data slicing point and two are at the same level above the data slicing point.
17. A method as claimed in claim 15 or claim 16 wherein two of the four testing points are at the same point in time in the interval before the data slicing point and two are at the same point in time in the interval after the data slicing point.
18. A method as olaimed in any one of olaims 10 to 17 comprising checking that the previous, current and following data bits to the current interval for which the test point is sampled are respectively a first binary logic value, the opposite binary logic value and the opposite binary logic value, and then in that case only performing the adjusting of the timing slicing reference level in a direotion that results in the timing of the test point on the other side of the waveform from that data point being moved in a direction toward the data point.
19. A method as claimed in claim 18 wherein the timing slicing level is +/-h--h-h of the data waveform.
20. Apparatus for carrying out the method of any one of claims to 19 comprising: a local oscillator connected to provide a clock signal to define the data slicing time and the test point comparison times, a data sampler connected to receive the signal waveform, one or more test samplers connected to receive the signal waveform and the associated reference levels and to compare those at times defined by the local clock signal, a control unit responsive to the data samples produced by the data sampler and test samplers to control the levels of the data slicing level or of the data slicing level and the associated reference levels.
21. A method of recovering a clock signal comprising: receiving a data waveform comprising a series of intervals, comparing the waveform at a data slicing time in each interval to a data slicing reference level and outputting the result as a recovered data value, comparing, during at least some intervals, the data waveform at a timing slicing point in time in the interval to a timing slicing level and adjusting in response to that the data slioing and timing slicing times, wherein the method comprises checking that the previous, current and following data bits to the current interval for which the test point is sampled are respectively in value: a first binary logic value, the opposite binary logic value and the opposite binary logic value, and only in the case of those bits having those values, adjusting the data slicing and timing slicing times.
22. A method as claimed in claim 21 wherein the timing slicing level is a fixed predetermined level.
23. A method as claimed in claim 22 wherein the timing slicing level is +/-h--h-h of the data waveform.23. A clock recovery circuit comprising: an input for a data waveform, a data sampler connected to sample the data waveform, a timing sampler connected to sample the data waveform, a local oscillator connected to provide a olock signal to define the sampling times of the data sampler and the timing sampler, a control unit connected to receive the outputs of the data and timing samplers and in response to those outputs to check that the previous, current and following data bits of the current interval for which the test point is sampled are respectively in value: a first binary logic value, the opposite binary logic value and the opposite binary logic value, and only in that case to adjust the data slicing and timing slicing times. 3'24. A method both as olaimed in any one of olaims 1 to 8 and as in olaimed in any one of olaims 10 to 19, or oiaim 21 or olaim 22.