GB2502293A - A method for manufacturing a back contacted back junction solar cell module - Google Patents
A method for manufacturing a back contacted back junction solar cell module Download PDFInfo
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- GB2502293A GB2502293A GB1208990.0A GB201208990A GB2502293A GB 2502293 A GB2502293 A GB 2502293A GB 201208990 A GB201208990 A GB 201208990A GB 2502293 A GB2502293 A GB 2502293A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
- H01L31/1896—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates for thin-film semiconductors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
Silicon based back-contacted back junction (BC-BJ) solar modules use the crystalline silicon on glass (CGS) technology approach on epitaxially grown wafers with emitter doping, optionally including surface field doping, followed by plasma texturing and CVD Âbased deposition of surface passivation films to finish the front side of the solar cells. Three epitaxial silicon layers (epi-layers) are grown on a porous release layer (Fig. 1b; 2) which is formed on a silicon donor wafer (Fig. 1b; 1). The first epi-layer 3 is an emitter layer, 0.2 - 5 microns thick, doped to a concentration from 1.1016 1.1020 cm-3 of either an N-type or a P-type doping element; the second epi-layer 4 is a base layer, 10 65 microns thick, doped to a concentration from 1.1015 to 1.1017 cm-3 of a doping element of the opposite conductivity to the first epi-layer; and the third epi-layer 5 is a surface field layer, 0.2 5 micons thick, doped to a concentration from 1.1016 to 1.1020 cm-3 of either a P-type or an N-type doping element. The major surface of the third epi-layer is surface textured 6 and a surface passivation film7 is formed on the major surface of the third epi-layer. The semi-finished cells are separated from the donor wafer (Fig. 1b; 1) by attaching a temporal chuck (Fig. 1c; 9) and cleaving the porous release layer, and laminated onto the front glass substrate (Fig. 1e; 22) of the solar panel such that a smooth and planar back surface is obtained, and back-side surface passivation 11 and electric contacts 14, 15 and cell interconnects are formed.
Description
A method for manufacturing a back contacted back junction solar cell module
Field of the invention
The present invention relates to cost effective production methods of high efficient silicon based back-contacted solar panels and solar panels made by the method.
Background
There are raised many concerns that the use of fossU energy is increasing the earth greenhouse effect to an extent that may turn dangerous. Thus the present consumption of fossil fuels should preferably be replaced by energy sources/carriers that are renewable and sustainable for our climate and environment.
One such energy source is solar light, which irradiates the earth with vastly more energy than the present and any foreseeable increase in human energy consumption.
However, solar cell electricity has up to date been too expensive to be competitive with nuclear power, thermal power, hydroelectric power etc. This needs to change if the vast potential of the solar cell electricity is to be realised.
The cost of electric ity from a solar panel is a function of the energy conversion cfficicncy and the production costs of the solar panel. Thus thc search for cheaper solar electricity should be focused at high-efficient solar cells made by cost-effective manufacturing methods.
The presently dominating processing route of silicon based solar panels may roughly be described as follows; manufacturing the solar grade feedstock in the form of crystalline blocks ofhigh purity silicon, sawing the blocks into a set of thin wafers, cefl processing each wafer to a solar cell, and then mounting the so'ar cells to form solar panels which arc further installed and integrated as solar systems.
The present dominating processing route is however encumbered with a very low utility degree of the silicon feedstock, mainly due to two factors; the present day sawing process requires a minimum thickness of the wafers of 150 -200 iim while the most significant photovoltaic active layer in the wafer is only about 20 -30 tm, and the formation of the wafers by sawing results in about half of the solar grade silicon feed material being lost as kcrf remains. It is thus highly dcsirafflc to find a process route for silicon based solar panels without need for sawing the wafers and which may form wafers with a thickness in accordance with the photovoltaic requirements.
Prior art
A method for manufacturing back contact back junction solar cells (BC-BJ cell) based on solar grade feedstock in the form of crystalline blocks of high purity silicon being sawed into wafers and then processed to BC-BJ cells is known from US 6 337 283. The document discloses a method of fabricating a back surface point contact silicon solar cell having p-doped regions and n-doped regions on the same side by forming a passivating layer on a surface of the cell having opened windows at the p-doped regions and the n-doped regions, b depositing and patterning a first metal layer on the passivating layer in such a way that the first metal layer comes into contact with the p-doped regions and the n-doped regions, by depositing a first insulator layer of polyimide on the first metal layer, by etching and patterning the first insulator layer ofpolyimide in such a way that the insulator layer has opened windows at, at least one of the p-doped regions and the n-doped regions, by depositing a second insulator layer of polyimide on the first insulator layer of polyimide, by etching and patterning the second insulator layer of polyimide in such a way that the insulator layer has opened windows at, at least one of the p-doped regions and the n-doped regions, by curing the first insulator layer of polyimide by heating at a predetermined second temperature for a predetermined second time, and by depositing a second metal layer on the second insulator layer of polyimide in such a way that the second metal layer comes into contact with the one of the p-doped regions and the n-doped regions. With this, the cell surface to be soldered onto a metallized substrate is well planarized and even to ensure sufficient conductibility, with less voids and less solder fatigue.
A similar approach is known from WO 2008/039078 which discloses a method for producing a back-contacted solar cell, where the method comprises applying a silicon substrate, wafer or thin film, doped on the back side with alternating P-type and N-type conductivity in an interdigitated pattern and optionally a layer of either or N-type on the front side of the wafer, characterised in that the method further comprises: -depositing one or more surface passivation layers on both sides of the substrate, -creating openings in the surface passivation layers on the back side of the substrate, -depositing a metallic layer covering the entire back side and which fills the openings in the surface passivation layers, and -creating openings in the deposited metallic layer such that electric insulated contacts with the doped regions on the back side of the substrate is obtained.
The problem of low utility degree of the solar grade feedstock when applying wafers sawn out of blocks has been solved by making solar cells from silicon films deposited on a substrate. An example of this technology is disclosed in Keevers et al. [I], where a photovoltaic panel comprising a polycrystalline thin film of silicon is deposited on a glass substrate. This technology is known as crystalline silicon on glass, or CSG-technology. The manufacturing process begins with texturing one surface of the glass substrate by dip-coating with 0.5 iim silica beads. Then a layer of SiNX and a layer of p-doped amorphous silicon are deposited onto the textured surface by use of plasma enhanced chemical vapour deposition (PECVD). Then a thin film of polycrystalline silicon is formed by use of solid phase crystallisation followed by a rapid thermal treatment and rapid in-line hydrogenation. The deposited semiconductor layer is then partitioned to a set of individual cells by use of laser scribing, before a resin layer is applied by roller coating. Then a set of contact openings in the resin layer is formed by ink-jet printing an etching agent before the panel is finished by depositing an Al layer by sputtering followed by scribing to form the interconnects. The drawback of this technology is low photovoltaic efficiencies of the solar cells as compared to wafer based monocrystalline solar cells.
WO 2009/1 28721 discloses a solution to the problem of low photovoltaic efficiencies by combining the traditional wafer based approach and the CSG-approach. This document discloses a method for producing solar panels which comprises employing a number of semiconductor wafers and/or semiconductor sheets of films prefabricated to prepare them for back side metallization, which are placed and attached adjacent to each other and with their front side facing downwards onto the back side of the front glass, before subsequent processing that includes depositing at least one metal layer covering the entire front glass including the back side of the attached wafers/sheets of films. The metallic layer is then patterned and divided into electrically isolated contacts for each solar cell and into interconnections between adjacent solar cells. This invention makes use of an adaption of the CSG-tcchnology for wafer based solar cell production, and thus takes advantage of the work load savings associated with the CGS-technology and the high conversion efficiencies obtainable by use of monocrystalline or muhicrystalline wafers.
From WO 2011/03 1707 it is known a method for fabricating a photovoltaic (PV) cell panel wherein each of a plurality of silicon donor wafers has a separation layer formed on its upper surface, e.g., porous anodieally etched silicon. On each donor wafer, a PY cell is then partially completed including at least part of inter-cell interconnect, after which plural donor wafers are laminated to a backside substrate or frontside. All of the donor wafers are then separated from the partially completed PY cells in an exfoliation process, followed by simultaneous completion of the remaining PY cell structures on PV cells. Finally, a second lamination to a frontside glass or a backside panel completes the PY cell panel. The separated donor wafers may be reused in forming other PV cells. Use of epitaxial deposition to form the layers of the PV cells enables improved dopant distributions and sharper junction profiles for improved PV cell efficiency.
Beaucarne et al. [2] discloses surface texturing silicon wafers by use of microwave induced reactive plasma etching with SF6, N2O, and Cl2 as plasma gases. The process is self-masking and obtains a moderate surface reflectance of 15 -22 % ofa multi-crystalline Si-wafer, which is comparable with typical results obtained by chemical surface texturing.
Lc Quandt et aL [31 informs that microwavc plasmas cmploying SF6, N20, and Cl2 as plasma gases obtains surface texturing by the following reactions: Fluorine radicals (coming from SF6) react with S-atoms at the wafer surface: Si + 4F -* SiF4 ( and othcrs SiF).
Then oxygen radicals (coming from N20) passivate the surface of the etched silicon surface: SiF+O -*SiO+F SiF+O-.SiFO And then chlorine radicals (from Cl2) react selectively with front bonds on the wafer surface, which leads to an increase of the surface roughness. Depending on the ratio of N20, SF6 and Cl2, the surface texturing may be tailored to give preferred shapes and sizcs of thc surfacc structure cnabling for good clectrical and optical properties during subsequent front surface passivation and anti-reflect coating. The document informs that the surface reflectance may be significantly reduced compared to alkaline textured surfaces (-2 %).
Objective of the invention The main objective of the invention is to provide a cost effective manufacturing method for back contact back junction solar cells.
The objective of the invention maybe achieved by the features as set forth in the description below and in the appended claims and attached figures. The attached figures show embodiments of the invention.
Description of the invention
The invention is based on the realisation that a significant work load reduction and cost sayings in the manufacturing process may be achieved by using the CGS-technology approach on epitaxially grown wafers with emittcr and base Iaycr, optionally including a surface field layer doping during the epitaxial deposition of the wafer. This specific order of the process steps provides a process route with significantly fewer process steps and allows use of similar process equipment in a considerable portion of the manufacturing process.
Thus in a first aspect, the present invention relates to a method for manufacturing a back contacted back junction solar cell module, where the method comprises: -forming a plurality of scmi-finishcd solar cclls, each on a respcctive donor wafer having at least one porous release layer, and -separating each of the semi-finished solar cells from their donor wafer by attaching a temporal chuck to the upper major surface of the semi-finished solar cell and cleaving the at least one porous release layer, and optionally -removing the remains of the at least one porous release layer on the separated semi-finished solar cells by chemical etching, and where -the formation of each semi-finished solar cell includes at least the following process steps in successive order: i) employing a monocrystalline silicon donor wafer having a planar deposition surface into which at least one porous release layer is formed, ii) placing the donor wafer in a chemical vapour deposition chamber and cpitaxially depositing a three layered structure of doped monocrystalline silicon layers epi-layers) onto the porous release layer of the deposition surface such that: a) the first epi-layer is given a thickness from 0.2 -5 jim and is doped to a concentration from 1.1016 -1.1020 cm3 of either an N-type or p type doping clement, b) the second epi-layer is deposited directly onto the first epi-layer and is given a thickness from 10 to 65 pm and doped to a concentration from 1.1015 to 1.1017 cm3 of an doping element giving the opposite conductivity of the first epi-layer, and c) the third cpi-laycr is deposited directly onto the second cpi-laycr and is given a thickness from 0.2 -5 jim and doped to a concentration from 1.1016 to Li 2O cm3 of either P-type or N-type doping element, iii) surface texturing the upper major surface of the last epi-layer deposited in step ii), and iv) depositing at least one surface passivation layer and optionally at least one anti-reflective coating layer on the textured surface.
As an alternative, the method according to the first aspect of the invention may further comprise one or more of the following process steps: -attaching a number of the semi-finished solar cells with their lower major surface of the first deposited epi-layer facing down in a pattern defining the positions of the plurality of solar cells of the solar module onto a lamination board and removing the temporal chucks, -laminating the back-side of a module front glass containing transparent adhesive onto the deposited semi-finished solar cells and removing the lamination board, -removing eventual remains of the at least one porous release layer on the lower major surface of the first deposited cpi-layer of each of the deposited semi-finished solar cells by chemical etching, -selectively removing portions of the first epi-layer to expose the underlying second deposited epi-layer for of each of the deposited semi-finished solar cells, -depositing at least one surface passivation layer covering the entire back side of the front glass including each of the laminated semi-finished solar cells, -forming electric contacts electrically connecting the N-type and P-type doped regions at the back side of each of the deposited solar semi-finished solar cells, -completing the processing to finished solar cells by forming interconnects connecting the solar cells of the module together, and -laminating a back side module substrate onto the back side of the front glass for protecting the deposited finished solar cells of the module.
Alternatively, the solar module may be formed by depositing and laminating the semi-finished solar cells one by one onto the module front glass until the intended pattern of tessellated solar cells in the module is formed. In this case, the semi-finished solar cell will be deposited with their back-side facing down onto a second temporal chuck after separation from the donor wafer, optionally also after removal of the remains of the at least one porous release layer. When the second temporal chuck is attached onto the back-side, the semi-finished cell is deposited at its intended position and laminated with its front side facing onto the front glass of the module.
In a second aspect, the present invention relates to a back contacted back junction solar module, wherein the module comprises: -a number of solar cells based on monocrystalline epitaxially grown silicon wafers having a stratified layered structure of doped silicon layers consisting of: -a first epitaxially grown layer (epi-layer) of thickness from 0.2 -5 Lm 16 20 doped to a concentration from I 1� -1 10 cm of either an N-type or P-type doping element, -a second intermediate cpi-laycr of thickness from 10 to 65 p.m doped to a concentration from 1.1015 to 1.1017 cm3 of an doping element of the opposite conductivity of the first layer, and -a third epi-layer of thickness from 0.2 to 5 p.m doped to a concentration from 1.1016 to 11020 cm of either P-type or N-type doping element, where each solar cell of the module is having: -a surface texture, at least one surface passivation film, and optionally at least one anti-reflective coating on the major surface of the third epi-layer, -an interdigitated pattern of N-and P-type doped regions on the major surface of the first epi-layer made by locally removing portions of the first epi-layer to expose the surface of the underlying second epi-layer, -at least one surface passivation film covering the back side, and -electric contacts electrically connecting the N-type and P-type doped regions of the back side of the cell, where the module further comprises: -electric interconnects serially connecting the electric contacts of the solar cells of the solar module together, -a front glass, and -a back cover, and where -each solar cell of the module is laminated to the front glass and back cover such that the cells are forming a more or less tessellated pattem with the major surface of the third epi-layer facing the front glass.
The terms "front side" and "back side" as used herein are related to the orientation of the solar module or solar cells during normal operation, such that the front side is the side of the module or solar cells facing the sun and the back side is the opposite side facing away from the sun.
The term "silicon wafer" as used herein means any thin planar object of monocrystalline silicon made by epitaxial deposition of silicon having the stratified three-layered structure of doped silicon consisting of a first epitaxially grown layer (epi-layer) of thickness from 0.2 -5 m doped to a concentration from 1.1016 - 11020 cm3 of either an N-type or P-type doping clement, -a second intermediate epi-layer of thickness from 10 to 65 jim doped to a concentration from 1.1015 to i* io'7 cm3 of an doping element of the opposite conductivity of the first layer, and a third epi-layer of thickness from 0.2 to 5 jim doped to a concentration from 11016 to hO20 cm3 of either P-type or N-type doping element. The silicon wafer will have two major (free) surfaces in parallel and opposite each other of which one is on the third epi-layer and will form the front side of the solar cell, while the other forms the back side of the solar cell and is composed of interdigitated portions of the surface of the first and second epi-layer. The major surfaces of the silicon wafer may have any known or conceivable geometry and characteristic dimensions associated with solar cells. Examples of suited geometry of the major surfaces of the silicon wafers include, but are not limited to, squares, rectangles, circles, semi rectangles and semi squares, where "semi" refers to rounded corners, chamfered corners, or angled corners. The geometry of the major surfaces may advantageously be of a shape that allows laying the wafers in a pattern on a substrate surface such that they substantially tessellate when being laid side by side onto the substrate surface with a small gap between the wafers. The simplest geometric shapes of wafers able to substantially tessellate are wafers with a square or rectangular surface area of the major surface. In these cases the characteristic dimensions of the major surface may advantageously be a length 1 and width d in the range from 50 to 400 mm, preferably 125 -300 mm. In cases of employing circular wafers, the characteristic dimension may be a diameter in the range from 30 to 300 mm. The thickness, i.e. the shortest distance between the opposed major surfaces, of the epitaxially grown silicon wafer maybe any known or conceivable thickness associated with solar wafers. However, the thickness may advantageously be a trade-off between the need for obtaining sufficient photovoltaic activity, avoiding excessive use of the silicon raw material and obtaining a sufficient mechanical strength of the wafer. Thus, the thickness of the first epi-layer may advantageously be in one of the following ranges; from 0.2 -5 jim, from 0.3 -3 jim, from 0.3 - 2 jim, or from 0.4 -1 jim, the thickness of the second epi-layer may advantageously be in one of the following ranges; from 10 to 65 jim, from 20 to 50 jim, or from 30 to 40 jim, and the thickness of the third epi-layer may advantageously be in one of the following ranges; from 0.5 -20 jim, from 1 -10 jim, from 1 -5 jim, or from 1 -3 jim.
The concentration of doping elements in the first epi-layer may advantageously be in one of the following ranges; from 1.1016 -1.1020 cm* from 1.1017 to 1.1020 cm3, from 1.1018_S. 1019 cm3, or from 1.1019_S. 1019, in the second epi-layer may advantageously be in one of the following ranges; from 1.1015 to 1.1017 cm3, from io'5 to 51016 cm3, or from 1.1016 to 5.1016, and in the third epi-layer may advantageously be in one of the following ranges; from 1.1017 -1.1020 cm3, from 510'7to 510'9cm3,orfromL1018-L1019cm*Inordertoformthebaek junction feature of the solar cells, it is mandatory to have an opposite conductivity of the first and second deposited epi-layer. That is, the if the first epi-layer is given a N-type conductivity the second epi-layer must be given a P-type conductivity, or if the first epi-layer is given a P-type conductivity the second epi-layer must be given a N-type conductivity. Due to the above specified concentration levels, the first epi-layer is relatively heavy doped and will thus form the emitter layer of the solar cell and the second epi-layer will form the base layer of the solar cell. The invention may thus form solar cells having an emitter layer of either P-or N-type.
The third epi-layer may form either floating junction or front surface field layer of the solar cell and may have conductivity independent of the base layer conductivity.
That is, the third epi-layer may have either an N-or P-type conductivity regardless of whether the base layer is of P-or N-type. The possible configurations of the stratified three layer wafer of the solar cell according to the present are given in
Table 1.
Table I Possible configurations of the stratified layers of the solar cell according to the present invention Epi-Conductivity layer Configuration! Configuration 2 Configuration 3 Configuration 4 1 N P 2 P N P N 3 N' P P' N' The term "P-type doping" as used herein means a bulk area of the silicon wafer where a doping material resulting in an increased number of positive charge carriers forming a region of the wafer with P-type conductivity. The term "N-type doping" as used herein means a bulk area of the silicon wafer where a doping material resulting in an increased number of negative charge carriers (mobile electrons) forming a region of the wafer with N-type conductivity.
As used herein, the term "semi-finished solar cell" means an epitaxially grown wafer of monocrystalline silicon doped to the stratified three-layer structure as dcfined above and where the front surface of the cells, i.e. the major surface of the third epi-layer are processed to a point where the front side of the solar cell is finished and may be laminated onto the front glass of the module. The "semi-finished state" will thus involve at least surface texturing and surface passivation, and may optionally also include forming an anti-reflective coating. Any other conceivable process step associated with processing of the front surface of back junction back contact cells may also be included.
The invention may apply any known or conceivable chemical vapour deposition technique or equipment able to epitaxially grow a crystalline silicon layer by chemical vapour deposition (CVD). Suitable deposition techniques includes, but are not limited by, atmospheric pressure CYD (APCVD), low-pressure CYD (LPCVD), ultrahigh vacuum CVD (UHYCYD), aerosol assisted CYD (AACVD), microwave plasma-assisted CYD (MPCVD), plasma-Enhanced CYD (PECVD), remote plasma-enhanced CYD (RPECVD), atomic layer CVD (ALCVD), hot wire OlD (HWCVD), catalytic CVD (Cat-CVD), and hot filament CYD (HFCVD). Examples of suitable precursor gases for formation of the silicon layer includes but is not limited to silane, tetrachloro silane, dichloro silane, or any other known or conceivable silane based pre-cursor gas(es).
The doping of the emitter, base and front surface layer of the silicon wafer may be obtained by mixing the silicon precursor gases with gases containing p-type or n-type doping elements at suitable concentrations to provide the specified doping levels. For example, to obtain p-type doping the precursor gases maybe added a boron-containing gas such as i.e. diboranc, B2H6. Any gaseous compound containing an element known to dope silicon to p-type may be applied. Similarly, any gaseous compound containing an element known to dope silicon to n-type may be applied when forming the emitter layer or eventually a n-type front layer of the wafer. Examples of suitable elements for forming n-type doping includes, but is not limited to arsenic, As, or phosphorus, P, in the form of i.e. phosphine. The process of doping a silicon layer during chemical vapour deposition is known to those skilled in the art and need no further description. The invention may apply any known or conceivable process parameter which is able to provide crystalline silicon layers with the specified doping levels.
The method according to the first aspect of the invention results in that the emitter layer is formed at the back side of wafer (near the porous silicon surface of the donor wafer), while the front layer defines the front side of wafer (top surface of the grown layer). The term "back-contacted" means that all electric contacts are placed on the hack side of the solar wafer.
The term "silicon wafer" should not be confused with the term "donor wafer", since as used herein, the term "donor wafer" means a thick (in relation to the silicon wafer) object of monocrystallinc silicon with a planar deposition surface to be used as deposition target during the epitaxial growth of the silicon wafer. The term "deposition surface" as used herein refers thus to the planar area dedicated for the deposition of a silicon wafer/thin layer through epitaxial growth. The donor wafer may advantageously be shaped into a rectangular parallelepiped of length A, width B and height C, where one of the major surfaces defined by length A and width B functions as the deposition surface. The dimensions of length A and width B will be determined by the dimensions of the intended epitaxially grown wafer, which has an intended length I and intended width w, such that the differences (A -I) and (B -w) are in the range from 0.1 to 10mm, preferably in the range from 0.1 to 5 mm, or 0.2 to 2 mm. The thickness (height C) of the donor wafer should advantageously be a trade-off between the need for mechanical strength and number of possible reuses, and the need for avoiding excessive thermal mass in the deposition chamber, i.e. the hcight C may advantageously be in the range from 100 to 1000 jim, preferably in the range from 200 to 800 jim or in the range from 400 to 600 jim. The term "characteristic dimensions" as used herein means the dimensions characteristic for the extension and size of the surface area of the donor wafer.
In order to alleviate the separation of the epitaxially grown wafer and the donor wafer, the planar deposition surface of the donor wafer is made porous since a porous layer of a material is mechanically weaker than a continuous solid phase of the material. The use of a porous layer is advantageous in that the epitaxial growth process will form a homogeneous and continuous (i.e. not porous) wafer on top of the porous layer with the same crystal structure (ordering) as the donor wafer. Thus, since the underlying porous layer is mechanically weaker than the grown wafer, it becomes possible to separate the wafer from the donor wafer by use of mechanical shear stress, ultrasound, laser heating etc. The term "porous layer" as used herein means a layer in the deposition surface of the silicon donor wafer which contains a number of pores, holes or cavities which may or may not be connected. The invention is not tied to any specific thickness of the porous layer, but will in practice be limited to use of porous layers with a total thickness in the range from 0.1 to 10 pm, from 0.4 to 5 jim, or preferably from 0.5 to 2 jim. It maybe formed more than one porous layer on the deposition surface, for example one first layer with a low porosity optimized for high crystal quality and high electrical quality in the subsequent epitaxially grown silicon layer, and a second layer with a high porosity which is optimized for low separation force, forming a stratified structure of two or more layers with different porositics. The porosity of the uppermost starting layer (first layer) may be from 10 -50 %, preferably 20 -30 %, and the thickness may be in the range 0.1 -3 pm, preferably 0.5 -1.5 pm. The porosity of the second porous layer may be from 30 to 60 %, or preferably from 40 to 50 %, and the thickness maybe from 0.1 to I jtm, or preferably from 0.2 to 0.5 jim.
Formation of porous layers at the surface of silicon objects is known to those skilled in the art. The present invention may apply any known or conceivable technique for forming the porous layer(s) on the deposition surface of the donor wafer.
After formation of the crystalline silicon wafer with stratified doping layers, the front side of the wafer should be textured in order to maximise the light trapping properties of the solar cell. The term "textured" as used herein means that the wafer surface has been subject to some form of treatment for enhancing the surface roughness of the wafer. The texturing may be obtained by any known or conceivable process known to a skilled person, such as laser structuring, anisotropic chemical etching, plasma etching, etc. One advantage with epitaxially grown wafers is that they are not subject to sawing and thus fl-ce of sawing damages. The lack of sawing damages offers the benefit of allowing use of a shallow surface texturing technique such as plasma etching. Plasma etching is known to provide a stress free low temperature process with reduced environmental impact compared to the presently used acidic etching techniques. Plasma etching has the advantage that it may be applied in dry state, may be applied on only one side of the wafer, may be applied to large surface areas (large wafers/entire panels), and having the potential of becoming compatible with existing photovoltaic industrial production lines, in particular when sufficient surface topography can be obtained by removing as little as in the range of 1 jim thickness. The use of plasma etching is also beneficial from a cost perspective in that it only removes a surface layer of about 1 jim of the one side of the wafer being exposed to the plasma, as compared to conventional chemical etching which typically removes in the range 5 -10 pm of the surface layer on both sides of the wafer in order to eliminate surface cracks and other damages from the sawing process. In addition, the use of chemical etching induces a high consumption of deionised water to clean the wafer after etching. Beaucarne et al. [2], Le Quandt et al. [3], and Kumaravelu et al. [4] have demonstrated that reactive ion etching (ME) with a gas mixture of SF6, N20, and Cl2, or SF6 and 02 as plasma gases results in self-masking etching processes which result in textured surfaces on mono-or muhi-crystalline silicon wafers with excellent light reflectance. Kumaravelu et al. [4j informs that a mask-less RIB with SF6 and 02 as plasma gases givcs a silicon surface with a reflectance of 1.4 % at wavelengths from 400 to 1000 nm, with a minimum at 1000 nm of 0.8 %.
Reactive ion etching is well suited for wafers formed by epitaxial growth since the epi-layer growth is a relatively costly process, and the cost is nearly proportional to the thickness of the wafer. Thus, it is preferable to remove as little as possible of the grown layer for creating the surface topography that is preferred for low optical reflection in order to capture as much light as possihle Plasma texture has the capability of creating large topography at average etching depth in the range of 1 jim, which is advantageous both with respect to plasma etching time (and cost) and with respect to minimal removal of the grown epitaxial-layer. The plasma texture etching process is a vacuum process with a process pressure of a few mbar at room temperature or slightly elevated temperature. In some cases it can be advantages to reduce the wafer temperature by cooling during process.
Since the front surface field may be defined during the epitaxial growth process and provided that the front surface doping profile has sufficient thickness compliant with the texture etching process, there will be no need for a separate FSF diffusion step following the texture etching process. Therefore, the plasma texture etching process may immediately be followed by PECVD deposition of the surface passivation layers without any intermediate wet chemical process step for surface cleaning or surface preparation. These two vacuum processes may therefore be integrated in one multi-chamber vacuum system. This enables for a significant simplification of the process sequence compared to the present conventional ccli process for crystalline silicon solar cells.
The method according to the first aspect of the invention may apply any known or conceivable dielectric film suited to be used as surface passivation on silicon semiconductors and which may be deposited by chemical vapour deposition. It may be employed one or more deposited dielectric films, of the same dielectric material or of a combination of different dielectric materials. Examples of suitable dielectric films include, but is not limited to, hydrogenated amorphous silicon, a-Si:H; hydrogenated silicon nitride, a-SiN:i-1; and silicon oxide, Si02. The hydrogenated amorphous silicon film may be formed by chemical vapour deposition of silanc gas at a temperature in the deposition chamber of 50 -500 °C. The hydrogenated silicon nitride film may be formed by employing any known or conceivable precursor gas able to form silicon nitride by chemical vapour deposition. Examples of suitable precursor gases includes, but arc not limited by, SiH4, SiCI2H2, N2, and NH. The silicon dioxide film may be formed by chemical vapour deposition using silane and oxygen at temperature in the deposition chamber between 50 -500 °C. It is also possible to employ dichlorosilane, SiC12H2, nitrous oxide, N20, or an organic silicon compound.
It is envisioned that, as an alternative, that the wafers may be diced while still attached to the donor wafer. By performing the dicing while the wafers are still attached to the donor wafer, the wafers will have the advantage of having the mechanical support from the donor wafer. The dicing may be obtained by forming a set of scribes/notches/grooves going approximately 90 % through the thickness of the epitaxially grown wafer. It is advantageous to not avoid that the scribes/-notches/grooves extends through the entire thickness of the epitaxially grown wafer to ensure that the scribes/notches/grooves does not enter into the underlying donor wafer. The scribes/notches/grooves may be formed by laser cutting or ablation, chemical etching, plasma etching, reactive ion etching, diamond blade cutting, or by a combination of these techniques. In case of employing dicing before lift-off, the temporal chuck may be engaging one of the scribed regions and simultaneously separating the diced region from the donor and tear the remaining approx. 10 % of the wafer thickness forming a bridge to the adjacent diced region of the wafer.
Alternatively it may be applied a temporal chuck able to engage aH diced regions of the wafer and separate them in one single operation, and then expand laterally such the metal bridges (the approx. 10 % of the thickness not removed by the scribe) are torn after lift-off from the donor wafer.
The separation of the semi-finished solar cell from the donor wafer may be obtained by attaching a temporal chuck by i.e. vacuum suction etc., and then applying a mechanical shear stress, ultrasound, or laser heating to tear along or cleave through the porous release layer(s) such that the semi-finished solar cell may be lifted off After separation from its donor wafer, the next step is to deposit and attach the released semi-finished solar cell onto a lamination board with its back surface facing down onto the lamination board. This process is repeated until the lamination board has attached the intended number of semi-finished solar cells in a geometric pattern forming the tessellation of the solar cells of the solar module. After removing the temporary chucks, the semi-finished solar module is ready for lamination of the front glass. This is obtained by pressing a front glass having a layer of transparent adhesive onto the lamination board such that the attached semi-finished solar cells become laminated to the front surface facing the front glass.
Then the lamination board may be removed. Alternatively, after separating the wafer from its donor wafer, the wafer can be transferred and attached/encapsulated to the module glass individually by using a transparent glue or a transparent encapsulation material. The passivated front-side of the wafer is attached/-encapsulated to the module glass.
This latter step constitutes the end of the front side processing of the module. The back side processing will comprise removing remains of the porous release layer(s), surface passivation, forming electric contacts with the P-type and N-type doped regions, and forming cell and module electric interconnects for collecting the photovoltaic power produced by the module. Thc back side processing is performed in "module"-modus, that is, including all solar cells of the module while laminated to the front glass module of the solar module. Alternatively, after separating the wafer from its donor wafer, some of the back-side processing may be performed before the wafer is attached/encapsulated to the module glass.
The first back side process step is removal of remains of the porous release layer(s) on the hack side of the solar cells, and may advantageously he performed by chemical etching. The term "chemical etching" as used herein means any known or conceivable method for removing intended parts of crystalline silicon by dissolving them in an acid, base or other chemical solution. Examples of suited chemical etching agents includes: aqueous potassium hydroxide (ICON) solutions, tetramethyl-ammon ium-hydrox ide (TMAH, (CH)4NOW) water solutions, cthylcncdiaminc water solution (EDP), aqueous sodium hydroxide (NaOH) solutions, and aqueous lithium hydroxide (LiOH) solutions.
When the remains of the porous release layer(s) have been removed, the semi-finished solar cells are made ready to be processed to a finished state of functioning photovoltaic cells by forming the back side surface passivation and electric contacts to the p-and n-type regions of the cell. The first step in this process is to form the back side P/N-regions. This is obtained by removing the emitter layer at localised regions to expose the underlying base layer, forming an interdigitated pattern of P-and N-type conductivity, as shown in i.e. US 6 337 283. The invention is not tied to any specific method for selective removal of the emitter layer, but may apply any known or conceivable method which does not involve unacceptable high temperatures incompatible with the module glass and the encapsulation material, i.e. does not involve heating the semi-finished solar cells to higher temperatures than approximately 300 °C for a limited duration.
An example of a suited method is selective chemical etching of the emitter layer, either by applying an etching mask or by ink-jet printing of an etching agent. The process of selective removal of crystalline silicon by chemical etching is well known to a person skilled in the art, and needs no further description.
When the interdigitated pattern ofP-and N-type regions is formed, the back side of the solar cells is surface passivated by depositing at least one dielectric film. As for the front side, the invention may apply any known or conceivable dielectric film suited to be used as surface passivation of silicon semiconductors and which may be deposited by chemical vapour deposition. It may be employed one or more deposited dielectric films, of the same dielectric material or ofa combination of different dielectric materials. Deposition of dielectric films by CVD is well known to a person skilled in the art and needs no further description.
The invention may apply any known or conceivable processes for forming the electric contacts for connecting the P-type and N-type doped regions together and collecting the electric current produced by the solar cells. One example of a suited method is a modification of the method disclosed in WO 2008/039078 for forming back contacts, and comprises the following process steps: -creating openings in the deposited surface passivation layers in a per se known manner to expose the underlying P-type and N-type conductivity regions in all wafers, -depositing in a per se known manner a metallic layer covering the entire back side of the solar module, and -creating in a per se known manner openings in the deposited metallic layer such that electric insulated contacts with the doped regions on the back side of every semi-finished solar cell and the module interconnects of the solar module are obtained.
However, the invention is not tied to any specific configuration or method of forming the electric current collectors and cell interconnects, but may apply any known or conceivable configuration or method of forming the electric current collectors and cell interconnects connecting the individual photovoltaic cells to a back contacted solar module. The electric contacts and cell interconnects may alternatively be formed by one stack of metal layers which are partitioned to form the separate electric contacts for both terminals and another stack of metal layers forming the module interconnects. The module interconnection may be provided conventionally by soldering or gluing metal ribbons between metal contacts on adjacent cells.
The method according to the first aspect of the invention has the advantage that the epitaxially grown, and thus very thin, wafers can be processed or handled without the mechanical support by a substrate which is adhered or clamped to one side of the wafer. There is thus no handling or processing of free-standing wafers such that problems associated with bending or buckling (or breaking) of the wafers is eliminated or at least minimised. Another advantage of the inventive method is that there is no metallisation of the wafers while they are still attached to the donor wafer. This feature is a significant economic advantage in that the elimination of the risk of polluting (or contaminating) the donor wafers with metal or metal paste ensures that the relatively high-cost donor wafers may be applied in long series of wafer formation. Metal contamination of the donor wafer is critical due to the high-temperature epitaxial growth of subsequent thin layers. Each donor wafer may be applied for forming a large number of epitaxially grown thin wafers.
Another advantage with the present method is that the semi-finished solar cells (with processed front side) may be inspected for defects and malfunction after the relatively stressful and error prone cleavage from the donor wafer, and before being laminated onto the front glass of the module. Thus it is possible to sort out single malfunctioning wafers/semi-finished solar cells after they are subject to the relatively high-risk separation for the donor and before being irrevocably integrated onto the front glass of the solar module. It is thus envisioned including an optional inspection and/or control of the functionality of the wafers after step vii) but before step j) in the method according to the first aspect of the invention. This feature makes it possible to significantly decrease the reject rate in industrial production lines as compared to prior art methods due to the possibility of removing semi-finished solar cells before the irrevocable front glass lamination.
A further advantage of the present invention is that the process allows placing the wafers with their emitter layer facing down onto a lamination table directly after being released from the donor wafer. When laminating the grown thin wafers onto the front glass of the module, the transparent glue will more or less fill the voids between the grown thin wafers, lamination board, and front glass, such when the lamination board is retracted, the back sides of the deposited wafers and the transparent glue will form a smooth back surface of the module without unacceptable gaps, dents or other form ofdiscontinuities in the surface area between the wafers to forming the electric contacts and cell interconnects by depositing and partitioning a metallic layer. The process may also with the right amounts of glue and applied lamination pressure be tuned to make the glue practically fill the entire gap between the wafers. The lamination board may advantageously apply electrostatic clamping or vacuum suction to hold the semi-finished solar cells, and have a practically non-adherent towards the transparent glue. That is, the coating or surface does not permanently bond to the transparent glue and which can be delaminated from the lamination board without releasing material from one surface to the other surface. An example of suitable lamination board is a perforated aluminium plate coated with Teflon on the side facing the semi-finished cells and where the other side is in flow communication with a suction or vacuum pump. Ethylene-vinyl-acetate (EVA) is most commonly used as transparent glue and encapsulation material in conventional PV modules.
Alternative module encapsulation materials are polyvinyl butyral (F'VB) and any known silicon based transparent glues, which arc commercially available from several industrial companies.
A further advantage of the invention according to the invention is that the silicon wafer is produced and doped to the intended electrical conductivity in one single operation in a single chemical vapour deposition chamber and that no further in-diffusion of doping elements after formation of the wafer is needed. This saves several process steps as compared to prior art solutions where in-diffusion of doping elements is integrated in the processing of the wafers to solar cells, and represents thus a significant cost reduction of the present production process as compared to
prior art production processes.
List of figures Figures Ia to Ig is schematic drawings of a cross-section view seen from the side illustrating the process stcps according to the first aspect of the present invention.
Figurc 2a and 2b is schcmatic drawings of a cross-section view seen from the sidc illustrating an alternative embodiment of the first aspect of the invention.
Figure 3 is a schematic drawing drawings of a cross-section view seen from the side illustrating one embodiment of the invention.
Figure 4 is a diagram comparing the process steps of typical prior art methods with the manufacturing process according to the present invention.
Figures 5 a to c are graphs showing measured doping concentration versus distance for wafers made according to present invention.
Example embodiment
The invention will be described in greater detail by way of an example embodiment of the invention. The example embodiment is shown in Figures Ia to 1g.
As illustrated in Figure Ia), the manufacturing process initiates with applying a monocrystalline silicon donor I doped to P-typc conductivity (by having incorporated in thc range of 1.1018 -1.1020 cm3 of boron atoms in the silicon, or more preferably boron-doped at a concentration in the range of 2 1018 _21019 cm3 and shaped into a rectangular parallelepiped. The dimensions of the dolor wafer are typically ill the range of; length 125 -300 mm, width 125 -300 mm (not shown) and thickness in the range 200-1000 jim, or more preferably in the range 300 - 700 jim. On a major surface 4, there is formed a first porous silicon layer 2 by an clectrochemical etching scqucncc in thc applied crystal oricntation at room temperature in an etching solution composed by hydrofluoric acid isopropyl alcohol or ethanol: water in a ratio of 1: 1: 1. The first porous layer 2 has thickness of 0.5 -1.5 t.m and a porosity in the range from 20 to 30 % obtained by applying a constant current density of 5 -10 mAJcm2 for 90-120 seconds. Then a second porous (not shown) with a different porosity is formed by increasing the constant current density to in the range -250 mA/cm2 for approximately 0.5 -5 seconds. The second layer has porosity in the range from 30 to 60% and a layer thickness in the range 0.2-0.3 tim.
The epitaxial growth is initiated by ft-annealing for closing the upper pores of the first porous layer 2 to form a smooth surface and good starting poillt for the high quality epi-layer growth. The H2-annealing is performed at a temperature in the range from 900 to 1150°C for 0.5-15 minutes. It has been observed that during such a high temperature step, a transformation of the structure of the porous layer can occur. In order to achieve an optimum surface energy, the pores produced during etching of the outer porous layer tend to close on the surface of the porous layer. In this way, the porous layer may comprise a closed covering layer on its surface, which can serve as an ideal starting layer for the silicon thin film which is later to be deposited. The pores produced during etching of the inner porous layer tend to be transformed into larger cavities extending almost throughout the inner porous layer leaving very narrow bridges in between the donor wafer surface and the outer porous silicon layer. This transformation thereby results in the formation of a cleave layer.
The epitaxial growth of the silicon layers is obtained by chemical vapour deposition using one of silane, tetrachlorosilane, dichlorosilane or another silane based precursor gas at a temperature in the range of 900 -1200 °C and a gas pressure in the range from few 10 mbar to atmospheric pressure in the deposition chamber.
Actual pressure depends on reactor temperature, chamber geometry and reactor configuration. Epitaxial growth using trichlorosilane at 1120°C at atmospheric pressure gives a growth rate of 2 -4 jim/mm.
The first epitaxially grown layer is the emitter layer 3. The emitter layer will typically have thickness from 0.2 -2 jim and be doped to N -type conductivity by incorporating a concentration in the range from 5.1018 5 1019 cm3 of phosphorus atoms by using a precursor gas mixture of one of the silicon forming precursor gases mentioned above and a doping gas mixture ofphosphine (PU3), or other phosphorous doping sources diluted in ft at a temperature in the range of 900- 1200 °C and a gas pressure in the range from few 10 mbar to atmospheric pressure in the deposition chamber. Alternatively an arsine containing gas may be applied instead of phosphine. The second epitaxially grown layer is the base layer 4. The base layer will typically have thickness in the range of 20 -50 m, or more preferably in the range 30 -40 jim and be doped to P -type conductivity by incorporating a concentration in the range from 1.1016 -5.1016 cm3 of boron atoms by changing the precursor mixture to a mixture of silicon forming precursor gases mixed diborane (B2H6) or other boron containing doping sources diluted in H2 at a temperature in the range of 900 1200 °C and a gas pressure in the range from few mbar to atmospheric pressure in the deposition chamber. The third epitaxially grown layer is the front surface field layer 5, which typically will have a thickness of 1 -3 jim and be doped to a Nttype conductivity by incorporating a concentration of 1.1017 -sio18 cm3 boron atoms in the silicon.
As an alternative, the type doping of the emitter layer and the base layer may be interchanged, but with the doping levels and thicknesses indicated above maintained.
Figure 1 b) illustrates the three-layer epi-structure and the front side processing which is performed while the wafer is still attached to its donor wafer. The first process step is to form the surface texturing 6 on the front surface field layer 5. This may be obtained by for instance the method disclosed in Le Quandt et al. [3j, by conventional anisotropic etching, acidic etching, plasma etching, or reactive ion etching, laser structuring methods, etc. The front surface is then surface passivatcd by chemical vapour deposition at least one dielectric layer 7 with thickness of 5 -nm of one of the following dielectric materials: SiNX, SiO, A1203, or a combination of two or more of these layers. Then the anti-reflective coating is applied by chemical vapour deposition of a film of thickness of 50-100 nm of either SiNX or SiO,. Both the surface passivation layer(s) and the anti-reflective coating are deposited at vacuum conditions and a temperature in the range of 100 to 500 °C The surface passivation and anti-reflective coating is shown as one single layer 7 in Figures 1 b) and c).
One advantage with this approach is that if the plasma texture process and the surface passivation process are both done in vacuum, these processes can be implemented in two process chambers of the same equipment only separated by a load-lock. Additional advantage with this approach is that with a sufficiently shallow texture etching process there will be no need for a subsequent and separate diffusion step provided that the fiont surface field doping defined during the cpitaxial growth process has sufficient thickness being compliant with the texture etching process.
The next step of the method according to the example embodiment of the invention is to separate the epitaxially grown and semi-finished solar cell from the donor wafer 1 and to attach the front side of the wafer onto the front glass of the solar module in production. This is obtained by attaching a temporal chuck 9 to the surface of the front layer 5 including texturing 6, passivation film(s) 7, and anti-reflective coating 8, and then rip/tear/cleave through the porous layer 2 and lift off the semi-finished solar cell, as shown schematically in Figure 1 c. The temporal chuck may be of any known or conceivable chuck able to grip and hold a solar wafer, by i.e. vacuum suction, electrostatic clamping, etc. By use of a vacuum chuck, a maximum stress of the order of 10 N/cm2 may be created. A porous layer with the properties given above will typically tear when a stress in the range of 1 -5 N/cm2 is applied.
After lift-off, the remains of the porous layer 2 b need to be removed. This maybe achieved by chemical etching, or any known or conceivable method while the semi-finished solar cell is attached to the temporal transport chuck 9 (may also be removed by similar methods while the wafer has been attached to the front module glass, or attached to any other temporal substrate). Then the semi-finished solar cell 21 may be attached with its emitter side facing down onto a lamination substrate/table 20 at the intended position of the semi-finished solar cell in the resulting module, as shown schematically in Figure Id. The semi-finished solar cell 21 has of course the same layered structure and includes the same passivation film(s), texturing and anti-reflective coating as the cell shown in Figure Ib, but is for the cause of clarity only shown as a rectangle with one light layer (the emitter layer) and one dark layer encompassing all other layers of the semi-finished solar cell.
When the intended number of semi-finished solar cells are made and attached to the lamination board 20, the next step is to laminate the cells onto the front glass 22 in a layer of transparent glue or EVA 23 such that the gaps in-between the semi-finished solar cells 21 is filled with glue. This process is schematically indicated in Figures Ic and If. The lamination substrate/table employed in this example embodiment employs vacuum suction to hold the semi-finished solar cells and have a coating of Teflon® to make the surface non-adherent to the transparent glue or EVA in order to alleviate the removal of the lamination board after lamination. This stage of the manufacturing process completes the method according to the first aspect of the invention and is illustrated schematically in Figure 1g.
The remaining process steps to complete the back side of the semi-finished solar cells are back side surface passivation and formation of the electric current collectors and cell interconnects. This is obtained by processing the back side (the emitter side) of the semi-finished solar cells after lamination onto the front glass substrate of the solar module, and is obtained as follows: -forming an alternating p-type and n-type conductivity in an intcrdigitatcd pattern on the back side of each semi-finished solar cell in the solar module by locally removing the emitter layer (first epi-layer) by localized etching, laser ablation, or any other known method to expose the underlying type base layer (second epi-layer), -depositing by CVD one or more surface passivation layers on the back side of the solar module, -creating openings in the deposited surface passivation layers to expose the underlying p-type and n-type conductivity regions in all wafers, -depositing a metallic layer covering the entire back side of the solar module, and -creating openings in the deposited metallic layer such that electric insulated contacts with the doped regions on the back side of every semi-finished solar cell and the cell interconnects of the solar module are obtained.
Alternatively, the emitter surface of the semi-finished solar cell may be finished up to the point where the metallisation is to be done before being attached to the lamination board/substrate/table. These process steps are schematically illustrated in Figures 2a and 2b. The first step is to locally create openings 13 in the emitter layer 3 where the electric contacts to the p-doped base layer 4 is to be formed. Then the emitter layer 3 and the exposed surface of the base layer 4 is surface passivated by depositing in a per se known manner one or more passivation films 11 followed by creating local openings in the surface passivation layer 12, 14 where the electric contacts is to be formed. Then the electric contacts for both terminals and the cell interconnects may be formed by depositing a continuous metal layer in a per se known manner, and then partition the layer by i.e. laser ablation, localized etching or any other known metal patterning method to form separate electric contacts 14, IS as shown schematically in Figure 3. Alternatively, the module interconnection may be provided conventionally by soldering or gluing metal ribbons between metal contacts on adjacent cells.
The present methods has the advantage of considerable process simplification and thereby reduced cost in preparing high quality thin wafers by combining the formation and doping process during epitaxial silicon growth directly on a donor wafer and then process the wafers to photovoltaic cells, as may be seen from the diagram in Figure 4 which compares the manufacturing steps of a typical conventional manufacturing process of present industrial solar cell production with the manufacturing process according to the present invention. Another advantage of the invention is that it obtains a substantial reduction in the silicon consumption per peak Watt-power of the produced solar cell by one order of magnitude compared to conventional crystalline silicon solar cells.
Verification of the invention Improved epitaxial layer sequence demonstration A thin layer epitaxial growth process that incorporates the emitter doping layer and the front surface doping layer has been demonstrated by following process sequence; -Silicon donor substrate, p-type, B-doped (boron doped) -Electrochemical etching of porous silicon double layer in a mixture of HF, ethanol and water.
-Epitaxial growth at temperature 1120 °C using TCS as deposition gas; o Emitter layer (first layer), n-type, P-doping (phosphorous doping) concentration 1019 cm3, thickness 0.7 + 0.2 im o Base layer (second layer), p-type, B-doping concentration 3 1016 cm , thickness 30 + 3jim o Front Surface Field layer (third layer), n-type, P-doping concentration 1" - 510 cm, thickness 1.5 +1-0.3jtm -Lift-off thin layer cell from donor substrate by cleaving through the porous silicon layer The measured doping concentration versus distance from surface is shown in figures 5a-e, and shows that the deposition process corresponds well with targeted layer specifications. This verifies that the emitter layer can be introduced in the epitaxial layer process thereby significantly simplifying subsequent cell processing.
Cell process seQuence An interdigitated back-contacted cell has been fabricated from the demonstrated layer struclure by Following process sequence; -Silicon donor substrate, p-type, B-doped, resistivity 0.01 ohm-cm, diameter mm, thickness 675 jim, double-side polished, semiconductor grade quality. The silicon donor wafer is re-used several cycles.
-Electrochemical etching of porous silicon double layer in a mixture of HF, ethanol and water. Thickness and porosity of top layer is about 800 nm and -25 %, respectively. Thickness and porosity of bottom layer is about 300 nm and 35 -40 %, respectively.
-Epitaxial growth at temperature 1120 °C using TCS as deposition gas; o Emitter layer (bottom layer), n-type, P-doping concentration b'9 cm3, thickness 0.7 ± 0.2 am o Base layer, p-type, B-doping concentration 3.1016 cm3, thickness 30 + 3 jim o Front Surface Field layer (top layer), n-type, P-doping concentration 5.1017 cm3, thickness 1.5 +1-0.3 jim -Front surface plasma texture etching in a remote plasma etching chamber using a gas mixture of SF6 and N20. Average etching depth was 0.9 jim, and resulting reflectivity about 10 % (average reflectivity between 500 nm and SSOnm).
-Surface cleaning by standard wet RCA cleaning step.
-Front surface passivation and Anti-Reflect-Coating by depositing a double layer ofa:Si and SiNX in a PECVD process at 400 °C -Passivated front surface is then attached to 1 mm glass substrate using transparent silicone-based glue. This glass substrate now becomes the sunny side of the solar cell.
-Lilt-olIthin layer cell From donor substrate by cleaving through the porous silicon layer by using pure mechanical force. The silicon donor wafer is re-used several cycles.
-The remaining processing is done on the cleaved surface of the grown layer (defined as the bottom layer in the epitaxial growth process) to define the interdigitated back-contact pattern of the solar cell.
-Remove porous silicon residue layer from the cleaved surface by etching in KOH. Thickness of porous residue layer is about 0.8 jim.
-Deposit SiNX masking layer (etching barrier) by PECVD -Pattern S1NX masking layer in an interdigitated pattern by laser ablation using a green pico-second laser.
-Laser damage removal and through emitter etching to get access to base by KOH etching.
-Removc SiNX masking layer (etching barrier) by etching in HF -Surface cleaning by standard wet RCA cleaning step.
-Back surface passivation by depositing a double layer of a:Si/SiN in a PECYD process at 250 °C.
-Localized contact opening by laser ablation of the SiNX layer using a green pico-second laser.
-Evaporation of aluminium layer at thickness 15 jtm followed by evaporation ofSiO masking layer at thickness I tm in the same evaporation system.
-The SiO, masking layer (etching barrier) is removed in an interdigitated pattern by laser ablation using a nano-second laser.
-The aluminium layer is etched in the open areas not protected by the SiO, masking layer by using a standard wct chemical aluminium etching process.
-Finally, the Al/a:Si/Si contact is annealed at 250 °C for 10 minutes.
The characteristics of these cells are open circuit voltage at 653 my, short circuit currcnt at 33 mA!cm2, but not yct optimized, and cdl cfficicncy at about 14.5 %.
The cell efficiency potential for this cell configuration has been simulated to achieve more than 18 %. Simulations identified the base contact recombination as the limiting factor for cell efficiency, which can be improved by proper contact area layout. In addition this cdl is limited by high basc contact rcsistancc, high series resistance and various non-optimized parameters.
References 1. Keevers et. a!, "10% Efficient CSG Minimodules", 22nd European Photovoltaic Solar Energy Conference, Milan, September 2007 2. Beaucarne et al., "Etching, texturing and surface decoupling for the next generation of Si solar cells", Photovoltaics International, PVIOI-103, 2008.
3. Le Quang et al., "Dry Plasma Texturing -An Alternative Technique for Industrial Production of Thin mc-Si Solar CclIs", paper prcscntcd at 22nd European PV SEC, 3-7 Septcmbcr 2007 in Milan, Italy.
4. Kumaravelu et a!. "Surface Texturing for Silicon Cells Using Reactive Ion Etching", Photovoltaie Specialists Conference, 2002. Conference Record of the Twenty-Ninth IEEE, 19-24 May 2002.
Claims (11)
- C LA! MS 1. A method for manufacturing a back contacted back junction solar cell module, where the method comprises: -forming a plurality of semi-finished solar ce!ls, each on a respective donor wafer having at!cast one porous release layer, and -forming a plurality of scmi-finishcd solar cells on a donor wafer having at least one porous release!ayer, and -separating each of the semi-finished solar cells from their donor wafer by attaching a temporal chuck to the upper major surface of the semi-finished solar cell and cleaving the at least one porous release layer, and optionally -removing the remains of the at least one porous release layer on the separated semi-finished solar cells by chemical etching, and where -the formation of each semi-finished solar ce!l includes at!east the following process steps in successive order: i) employing a monocrystalline silicon donor wafer having a planar deposition surface into which at least one porous release layer is formed, ii) placing the donor wafer in a chemical vapour deposition chamber and epitaxially depositing a three layered structure of doped monocrystalline si!icon layers (epi-!ayers) onto the porous release!ayer of the deposition surface such that: a) the first epi-layer is given a thickness from 0.2 -5 jim and is doped to a concentration from 1.1016 -1.1020 cm3 of either an N-type or F-type doping e!ement, b) the second epi-layer is deposited directly onto the first epi-layer and is given a thickness from 10 to 65 jim and doped to a concentration from 1.1015 to 1.1017 cm3 of an doping element giving the opposite conductivity of the first epi-layer, and c) the third epi-layer is deposited direct!y onto the second epi-layer and is given a thickness from 0.2 -5 xm and doped to a concentration from 1.1016 to 1.1020 cm3 of either P-type or N-type doping element, iii) surface texturing the upper major surface of the last epi-layer deposited in step ii), and iv) depositing at least one surface passivation layer and optiona!!y at!cast one anti-reflective coating layer on the textured surface.
- 2. A method according to c!aim 1, wherein -the first!ayer of epitaxial!y grown silicon is deposited onto the at least one porous release layer of the donor wafer, where the first layer: -has a thickness in one of the following ranges; from 0.2-5 jim, from 0.3 -3 jim, from 0.3 -2 jim, or from 0.4 -1 jim, and -is doped to a concentration in one of the fol!owing ranges; from 1.1016 -11020 cm3, from 11017to 1.1020 cm3, from 1.1018_ 5.1019 cm3, or from 1.1019 -5.1019, of a N-type doping element, -the second layer of epitaxially grown silicon is deposited directly onto the first layer of epitaxially grown silicon, where the second layer: -has a thickness in one of the following ranges; from 10 to 65 lAm, from 20 to 50 pm, or from 30 to 40 pm, and -is doped to a concentration in one of the following ranges; from 1.1015 to l-10cm3,fi-om5l0'5to5-l0'6em3,orfroml1016to51016,ofa P-type doping element, and -thc third layer of epitaxially grown silicon is dcposited dircctly onto the sccond layer of epitaxially grown silicon, where the third layer: -has a thickness in one of the following ranges; from 0.5 -20 pm, from 1 -10 pm, from 1 -5 pm, or from 1 -3 pm, and -is doped to a concentration in one of the following ranges; from 1.1017 -1102°em3, from 5101'to 5.1019 cm, or from 1.1018 -1.1019 cni3, of either a P-or N-typc doping elcmcnt.
- 3. A method according to claim 1, wherein -the first layer of cpitaxially grown silicon is deposited onto the at least one porous release layer of the donor wafer, where the first layer: -has a thickness in one of the following ranges; fi-orn 0.2-5 pm, from 0.3 -3 pm, from 0.3 -2 pm, or from 0.4 -1 pm, and -is doped to a concentration in one of the following ranges; from 1.1016 -l1020cm3, from 11017to 1.1020 em3, from L1018-5-1019em3, or from 1.1019 -5.1019, of a P-type doping element, -the second layer of epitaxially grown silicon is deposited directly onto the first layer of epitaxially grown silicon, where the second layer: -has a thickness in one of the following ranges; from 10 to 65 pm, from 20 to 50 pm, or from 30 to 40 pm, and -is doped to a concentration in one of the following ranges; from 1.1015 to 1.1017 cm3, from 5.1015 to 5.1010 cm3, or from 1 1016to 51016, ofa N-type doping element, and -the third layer of epitaxially grown silicon is deposited directly onto the second layer of epitaxially grown silicon, where the third layer: -has a thickness in one of the following ranges; from 0.5 -20 pm, from I -10 pm, from 1 -5 pm, or from 1 -3 pm, and -is doped to a concentration in one of the following ranges; from11017-11020cm3,from5101'to510'9cm3,or from 1.1018 -1.1019 cm3, of either a P-or N-type doping element.
- 4. A method according to claim 1, 2 or 3, wherein the method also comprises dicing the wafer to form a number of electrically isolated regions after formation of the semi-finished solar cells and before separating the semi-finished solar cells from their donor wafer.
- 5. A method according to claim 4, wherein the dicing is obtained by forming a set of through-going scribes/notches/grooves which divides the epitaxially grown wafer into a set of electrically insulated silicon regions by one of the following techniques; laser cutting or ablation, chemical etching, plasma etching, reactive ion etching or diamond dicing wheel.
- 6. A method according to any of claims I -5, wherein the donor wafer has two porous layers formed in its deposition surface, where: -the first porous layer has a thickness in one of the following ranges; from 0.1 to 3 jim, or from 0.5 to 1.5 jim, and a porosity in one of the following ranges; from 10 to 50%, or from 20 to 30%, and -the second porous layer has a thickness in one of the following rages; from 0.1 to 1 jim, or from 0.2 to 0.5 jim, and a porosity in one of the following ranges; from 30 to 60% or from 40 to 50%.
- 7. A method according to any of claims 1 -6, wherein the surface texturing of the front side of the epitaxially grown wafer is obtained by either; laser structuring, anisotropic chemical etching, or plasma etching.
- S. A method according to claim 7, wherein the surface texturing is obtained by reactive ion etching (ME) with a gas mixture of one or more of the following; SF6, N20, Cl2, SF6, and 02 as plasma gases.
- 9. A method according to any preceding claim, wherein the surface passivation of the epitaxially grown silicon wafer is obtained by one of the following techniques; atmospheric pressure CVD (APCVD), low-pressure CVD (LPCVD), ultrahigh vacuum CVD (UHYCYD), aerosol assisted CYD (AACVD), microwave plasma-assisted CYD (MPCVD), plasma-Enhanced CYD (PECVD), remote plasma-enhanced CVD (RPECVD), atomic layer CVD (ALCVD), hot wire CVD (HWCVD), catalytic CVD (Cat-CVD), or hot filament CVD (EIFCVD), and where the precursor gases arc one or more of silanc, tetrachlorosilane, or dichlorosilanc.
- 10. A method according to any preceding claim, wherein the method also comprises the following process steps after formation and separation of the semi-finished solar cells: -attaching a number of the semi-finished solar cells with their lower major surface of the first deposited epi-layer facing down in a pattern defining the positions of the plurality of solar cells of the solar module onto a lamination board and removing the temporal chucks, and -laminating the back-side of a module front glass containing transparent adhesive onto the deposited semi-finished solar cells and removing the lamination board.
- ii. A method according to any claim from ito 9, wherein the method also comprises the following process step after formation and separation of the semi-finished solar cells: -depositing and laminating each semi-finished solar cells one by one onto the module front glass until the intended pattern of tessellated solar cells in the module is formed.I 2 A method according to claim 10 or 11, wherein the method also comprises the following process steps: -removing remains of the at least one porous release layer on the lower major surface of the first deposited epi-layer of each of the deposited semi-finished solar cells by chemical etching, -selectively removing portions of the first epi-layer to expose the underlying second deposited epi-layer for of each of the deposited semi-finished solar cells, -depositing at least one surface passivation layer covering the entire back side of the front glass including each of the laminated semi-finished solar cells, -forming electric contacts electrically connecting the N-type and P-type doped regions at the back side of each of the deposited solar semi-finished solar cells, -completing the processing to finished solar cells by forming interconnects connecting the solar cells of the module together, and -laminating a back side module substrate onto the back side of the front glass for protecting the deposited finished solar cells of the module.13. A method according to claim 12, wherein the electric contacts connecting the P-and N-type doped regions of each solar cell arc obtained by: -creating openings in the deposited surface passivation layers in a per se known manner to expose the underlying P-type and N-type conductivity regions in semi-finished solar cells, -depositing in a per se known manner a metallic layer covering the entire back side of the solar module, and -creating in a per sc kno\vn manner openings in the deposited metallic layer such that electric insulated contacts with the P-and N-type doped regions on the back side of every semi-finished solar cell of the solar module are obtained.14. A back contacted back junction solar module, wherein the module comprises: -a number of solar cells based on monocrystalline epitaxially grown silicon wafers having a stratified layered structure of doped silicon layers consisting of: -a first epitaxially grown layer (epi-layer) of thickness from 0.2 -5 pm doped to a concentration from 1.1016 -11020 cm3 of either an N-type or type doping element, -a second intermediate epi-layer of thickness from 10 to 65 jim doped to a concentration from 1.1015 to 1.1017 cm3 of an doping element of the opposite conductivity of thc first layer, and -a third epi-layer of thickness from 0.2 to 5 pm doped to a concentration from 1.1016 to 11020 cm3 of either P-type or N-type doping element, where each solar cell of the module is having: -a surface texturing, at least one surface passivation film, and optionally at least one anti-reflective coating on the major surface of the third cpi-laycr, -an interdigitated pattern of N-and P-type doped regions on the major surface of the first epi-layer made by locally removing portions of the first cpi-layer to expose the surface of the underlying second cpi-Iaycr, -at least one surface passivation film covering the back side, and -electric contacts electrically connecting the N-type and P-type doped regions of the back side of the cell, where the module further comprises: -electric interconnects serially connecting the electric contacts of the solar cells of the solar module together, -a front glass, and -a back cover, and where -each solar cell of the module is laminated to the front glass and back cover such that the cells arc forming a more or less tessellated pattern with the major surface of the third epi-layer facing the front glass.15. A solar module according to claim 14, whcrcin -the first epi-layer has a thickness of one of the following ranges; from 0.2 -5 pm, from 0.3 -3 pm, from 0.3 -2 pm, or from 0.4-1 pm, and is doped to a concentration in one of the following ranges; from 1.1016 -1.1020 cm3, from 1.1017 -iS 19 19 19 to UlO cm, from 110 -510 cmi, orfrom 110 -510, ofaN-type doping element, -the second epi-layer is deposited directly onto the first epi-layer and has a thickness of one of the following ranges; from 10 to 65 pm, from 20 to 50 jim, or from 30 to 40 pm, and which is doped to a concentration in one of the following ranges; from 1i01to 1.1017 cm3, from 5.1015 to 5-1016cn13, or from l1016to 5.1016, ofa P-type doping element, and -the third epi-layer is deposited directly onto the second epi-layer and has a thickness of one of the following ranges; from 0.5 -20 pm, from 1 -10 pm, from I -5 pm, or from I -3 pm, and which is doped to a concentration in one of the following ranges; from 1.1017 -11020cm, from 5lO17to 5.1019 cm, or from 1 io' -1.1019 cm3, of either a P-or N-type doping clement.16. A solar module according to claim 14, wherein -the first epi-layer has a thickness of one of the following ranges; from 0.2-5 pm, from 0.3 -3 pm, from 0.3 -2 pm, or from 0.4-1 pm, and is doped to a concentration in one of the following ranges; from 1.1016 -1 1020 cni3, from 1.1017 to L1020cm3, froml10'8-510'9cm3,orfroml10'9-510'9,ofaP-typedoping element, -the second epi-layer is deposited directly onto the first epi-layer and has a thickness of one of the following ranges; from 10 to 65 jim, from 20 to 50 jim, or from 30 to 40 jim, and which is doped to a concentration in one of the following ranges; from 1.1015 to 1.1017 cni3, from 5.1015 to 5.1016 cm3, or from 1.1016 to sol6, ofa N-type doping element, and -the third epi-layer is deposited directly onto the second epi-layer and has a thickness of one of the following ranges; from 0.5 -20 tim, from 1 -10 tim, from 1 -5 jim, or from 1 -3 jim, and which is doped to a concentration in one of the following ranges; from 1.1017 -Lb20 cm3, from 5.1017 to 5.1019 cm3, or from 1.1018 -1.1019 cm3, of either a P-or N-type doping element.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1208990.0A GB2502293A (en) | 2012-05-22 | 2012-05-22 | A method for manufacturing a back contacted back junction solar cell module |
| PCT/IB2013/053968 WO2013175354A2 (en) | 2012-05-22 | 2013-05-15 | A method for manufacturing a back contacted back junction solar cell module |
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| GB1208990.0A GB2502293A (en) | 2012-05-22 | 2012-05-22 | A method for manufacturing a back contacted back junction solar cell module |
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| GB2502293A true GB2502293A (en) | 2013-11-27 |
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| US20090227063A1 (en) * | 2008-03-08 | 2009-09-10 | Crystal Solar, Inc. | Integrated method and system for manufacturing monolithic panels of crystalline solar cells |
| US20100108130A1 (en) * | 2008-10-31 | 2010-05-06 | Crystal Solar, Inc. | Thin Interdigitated backside contact solar cell and manufacturing process thereof |
| WO2011072153A2 (en) * | 2009-12-09 | 2011-06-16 | Solexel, Inc. | High-efficiency photovoltaic back-contact solar cell structures and manufacturing methods using three-dimensional semiconductor absorbers |
| WO2011143449A2 (en) * | 2010-05-12 | 2011-11-17 | Applied Materials, Inc. | Method of manufacturing crystalline silicon solar cells using epitaxial deposition |
| US20120247560A1 (en) * | 2011-03-29 | 2012-10-04 | Seung Bum Rim | Thin Silicon Solar Cell And Method Of Manufacture |
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| US20100229928A1 (en) * | 2009-03-12 | 2010-09-16 | Twin Creeks Technologies, Inc. | Back-contact photovoltaic cell comprising a thin lamina having a superstrate receiver element |
| US20110056532A1 (en) * | 2009-09-09 | 2011-03-10 | Crystal Solar, Inc. | Method for manufacturing thin crystalline solar cells pre-assembled on a panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090227063A1 (en) * | 2008-03-08 | 2009-09-10 | Crystal Solar, Inc. | Integrated method and system for manufacturing monolithic panels of crystalline solar cells |
| US20100108130A1 (en) * | 2008-10-31 | 2010-05-06 | Crystal Solar, Inc. | Thin Interdigitated backside contact solar cell and manufacturing process thereof |
| WO2011072153A2 (en) * | 2009-12-09 | 2011-06-16 | Solexel, Inc. | High-efficiency photovoltaic back-contact solar cell structures and manufacturing methods using three-dimensional semiconductor absorbers |
| WO2011143449A2 (en) * | 2010-05-12 | 2011-11-17 | Applied Materials, Inc. | Method of manufacturing crystalline silicon solar cells using epitaxial deposition |
| US20120247560A1 (en) * | 2011-03-29 | 2012-10-04 | Seung Bum Rim | Thin Silicon Solar Cell And Method Of Manufacture |
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| GB201208990D0 (en) | 2012-07-04 |
| WO2013175354A2 (en) | 2013-11-28 |
| WO2013175354A3 (en) | 2014-05-22 |
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