GB2499266A - A method of manufacturing a digitiser, particularly a thin wire digitiser - Google Patents

Abstract

A method of manufacturing a digitizer includes the steps of ,applying a first conductive strip 305 (e.g. a copper busbar) along a first direction (e.g. Y) of an insulating substrate 303 (e.g. cardboard in the case of an opaque digitizer or whiteboard type or Poly Vinyl Butyral PVB or Ethyl Vnyl Acetate EVA sheet for a clear digitizer) arranging conductors 301 (e.g. tungsten, copper or aluminum wires) over the insulating substrate and extend along a second direction (e.g. X) that electrically connect at one end to the first conductive strip applying a second conductive strip (305, fig 62b) to the insulating substrate along the second direction (e.g. X) and arranging conductors (302, fig 62 b) over the insulating substrate that the extent in the first direction (e.g. Y) that electronically connects at one end the second substrate, and cutting, etching or otherwise breaking the first and second conductive strips to form separate conductive pads (315, fig 64) to allow connection of the conductors to electronics of the digitiser. The first and second conductors may be on opposite sides of the substrate. The conductors may form a wiggle pattern to reduce the production of moiré patterns. Alternately a second substrate may be used. A PVB sheet version may be sandwiched between two glass sheets. A number of different designs of digitiser are also disclosed

Description

Digitiser

The present invention relates to a digitiser for use in a position sensor and in particular, to a digitiser for use in a capacitive touch screen.

5

Computer devices are well known and significant research has been made into man machine interfaces that allow humans to interact with computer devices. For example, capacitive touch pads are well known and allow a user to move a cursor around the screen by moving their finger over the touch pad. Touch screens are also 10 well known in which an X-Y digitizer is mounted on or under the surface of a computer display and which allows the user to make selections directly on the display using either their finger or a conductive or an electromagnetic stylus. One type of digitiser commonly used in such touch screens has a grid of conductors arranged in perpendicular directions over the display screen and electronics arranged to measure 15 the change in mutual capacitance at each intersection point formed by the crossing X-Y conductors as a finger (and/or stylus) moves over the screen. Typically, the grid pitch (centre to centre distance between adjacent conductors) is between 5 mm and 20 mm, which provides a sensing resolution that is sufficient to detect a human finger anywhere over the grid. In many applications, the conductors are formed from indium 20 tin oxide (ITO) as these conductors are transparent. Copper is also commonly used to form the conductors of X-Y digitisers, although some users complain about being able to see the copper traces when used in smaller display screens.

Such a design of X-Y conductors is illustrated in Figure 1a. As shown, in Figure 1b, 25 when an excitation voltage is applied to an X conductor, it generates an electric field that couples with a Y conductor at the intersection point between the X-Y conductor pair. The amount of coupling defines the mutual capacitance between the two conductors. When a finger (or conductive stylus) is present over or near this intersection point, as shown in Figure 1c, some of the generated electric field couples 30 into the finger and thereby reduces the coupling (and hence mutual capacitance) between the X-Y conductor pair. Thus electronics coupled to the grid of conductors can sense the change of mutual capacitance and thereby the presence and location of the finger over the grid.

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When designing such X-Y digitisers for touch screen applications, there are a number of design challenges and tradeoffs. One challenge is that the mutual capacitance between each X-Y pair of conductors is relatively small and the change in mutual 5 capacitance due to the presence of the finger (or stylus) is smaller still. As a result, the measurements are often swamped by other signals, such as by switching noise associated with the switching of the LCD panel over which the X-Y conductors are placed and capacitive cross-talk between adjacent conductors of the X-Y grid. The digitiser has to be designed so that the measurements can be reliably performed at a 10 high enough update rate to support a natural drawing experience with the user's finger or stylus. The digitiser must do this whilst using low cost electronics in order to provide a low cost system for the consumer product market.

One of the major sources of unwanted error in the measurement signals is capacitive 15 cross-talk between adjacent grid conductors. In particular, when an excitation signal is applied to one excitation conductor, that excitation signal capacitively couples with adjacent excitation conductors. Similarly, signals coupled into one detection conductor will capacitively couple into the adjacent detection conductors as well. This can lead to significant cross-talk error in the signals being measured. This cross-talk can be 20 minimised by keeping the frequency of the excitation signal that is applied to the excitation conductor as low as possible. However, if the excitation frequency is too low, then it becomes difficult, or more expensive, to achieve the desired measurement update rate that will allow the tracking of the user's finger or stylus over time.

25 Further, the problems of measurement update rates and cross-talk get worse as the size of the grid increases. This is because with a larger grid, there will be more X-Y conductors (to achieve the same spatial resolution) and hence more intersection points to measure; and as each grid conductor becomes longer, its distributed resistance gets larger and the distributed mutual capacitance between adjacent wires 30 gets larger, which in turn increases the cross-talk error as a square of the diagonal size. Thus as the size of the grid gets larger, digitisers formed using ITO conductors face greater design challenges than those that use metallic based conductors (such as copper) because ITO has a much higher resistance than a metal conductors.

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A further problem with increasing size relates to the number of measurement channels that are used. In particular, in most digitiser systems, the signals from the detection conductors are multiplexed through a number (sometimes one) of separate 5 measurement channels before being processed by a microprocessor. However, as the display gets larger, the number of X-Y conductors increases to keep the same spatial resolution. Thus more measurements have to be made and this can result in the need to increase the number of measurement channels. However, this increases the cost of the digitiser.

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Figure 2 is a plot that shows how the power consumption and the cost of an ITO based digitiser and of a metallic conductor based digitiser increases with the size of the display. As shown, for small sized displays (diagonal size less than about 40cm), ITO provides the same performance as the metallic conductor based digitiser both in 15 terms of power consumption and cost. A metallic conductor based digitiser of such sizes can provide an update frequency well above the nominal 100Hz, but such performance is not required for man machine interfaces. However, with ITO based systems, the power consumption and the cost increase exponentially with increasing display size. This is because, the lower excitation frequency required by the ITO 20 based digitiser (to minimise capacitive cross-talk error) means that more measurement channels are needed to process the signals from the grid of conductors compared with a metallic conductor based digitiser. In particular, as metallic conductor based digitisers can use higher excitation frequencies, there is more time to multiplex the signals from more detection conductors through each measurement 25 channel - which helps to keep the cost and power consumption down. As shown in Figure 2, the thin metallic conductor based digitiser can be implemented with a relatively modest increase in the cost and power consumption for displays having a diagonal size up to 200cm (80"). The step change in both the cost and power consumption caused by the requirement of adding even more measurement channels 30 become evident for metallic wire digitisers having a diagonal size above 250cm.

Another challenge with large scale X-Y digitiser systems is the desire for the system to be able to measure simultaneously a large number of independent touches. For large

diagonal displays (over 100cm diagonal), the system might have to be able to detect over 10 different touches in order to enable a true multi-user interaction. This places further constraints on the design of the digitiser.

5 The inventor has designed a number of new digitisers (and parts thereof) that try to address one or more of the challenges and conflicting requirements described above. In so doing, the inventor has made a number of different inventions that are described and some of which are claimed herein. The new designs of digitiser can be used in touch screens or in separate touch pads. The digitisers that are described are ideally 10 suited for use with large scale display screens having diagonal sizes greater than, for example, 38cm (15") due to the ability of the algorithm to scale to large X-Y grids. For instance it allows to maintain about 100 Hz update rate for the accurate measurement of the mutual capacitance at each node of the 320X180 X-Y grid array. The inventor also provides the details of the manufacturing method for straightforward and cheap 15 integration of the dense thin metallic wire X-Y grid and the corresponding distributed sensing electronics for measuring mutual capacitance at each node of the grid.

According to one aspect, the present invention provides a digitiser comprising: a grid of conductors comprising a plurality of excitation conductors and a plurality of 20 detection conductors; excitation circuitry for applying excitation signals to selected excitation conductors; measurement circuitry for obtaining measurements from selected detection conductors; and processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of conductors. In one embodiment, the excitation circuitry is 25 arranged to operate in a cyclic manner to select each of the excitation conductors during an excitation cycle, wherein an excitation cycle comprises a sequence of excitation intervals during each of which a different pair of neighbouring excitation conductors is selected by the excitation circuitry and to which complementary excitation signals are applied, and wherein the excitation circuitry is arranged to 30 polarity modulate each excitation signal using a polarity control signal so that the polarity of the excitation signal applied to a selected conductor changes during a time that the excitation conductor is selected. The neighbouring conductors may be adjacent each other or there may be one or more (typically one or two) intervening

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conductors between the selected pair.

The grid of conductors may be formed from two sets of parallel conductors lying at an angle to each other (such as 90 degrees), although this is not essential as any grid 5 can be used.

The polarity control signal is preferably periodic and the time that an excitation conductor is selected is preferably an integer multiple of the period of the polarity control signal - so that the excitation signal applied to an excitation conductor has 10 equal amounts of positive excitation signal and negative excitation signal.

The excitation circuitry may be arranged to select neighbouring excitation conductors during plural consecutive excitation intervals in an overlapping manner such that during a first excitation interval a given selected excitation conductor is paired with a 15 first neighbouring excitation conductor and during a second excitation interval the given selected excitation conductor is paired with a second neighbouring excitation conductor. Such overlapping can facilitate the switching scheme used to control application of the excitation signals to the excitation conductors and simplifies the hardware design for the application of the polarity control signals to the excitation 20 circuitry. In combination with the polarity modulation, the overlapping also maximises the achievable update for the digitiser, as positive and negative measurements for each conductor can be obtained from measurements with different neighbours.

The excitation circuitry may also be arranged so that, during an initial excitation 25 interval of an excitation cycle, excitation conductors are selected without overlap with excitation conductors selected in a final excitation interval of a preceding excitation cycle. This helps to reduce the bandwidth requirements of the measurement circuitry, which in turn reduces the noise contained in the measurements.

30 In one embodiment the excitation circuitry is arranged to select the excitation conductors such that an excitation conductor selected during a last excitation interval of an excitation cycle neighbours an excitation conductor selected by the excitation circuitry during a first excitation interval of the excitation cycle. This can be achieved

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by scanning the excitation signal across the grid and back again one or more times.

The measurement circuitry may also be arranged to operate in a cyclic manner to select each of the detection conductors during a detection cycle, wherein a detection 5 cycle comprises a sequence of detection intervals during each of which a different combination of detection conductors is selected by the measurement circuitry. Preferably the measurement circuitry selects one or more pairs of neighbouring detection conductors during each detection interval. As before, the neighbouring conductors may be adjacent each other or there may be one or more (typically one or 10 two) intervening conductors between the selected pair. Preferably, the measurement circuitry determines differential measurements of signals obtained from each selected pair of neighbouring detection conductors.

The measurement circuitry may be arranged to select neighbouring detection 15 conductors during plural consecutive detection intervals in an overlapping manner such that during a first detection interval a given selected detection conductor is paired with a first neighbouring detection conductor and during a second detection interval the given selected detection conductor is paired with a second neighbouring detection conductor.

20

In one embodiment, each detection interval corresponds in duration to one excitation interval; and in an alternative embodiment, each excitation interval corresponds in duration to one detection cycle.

25 The measurement circuitry may comprise a plurality of measurement channels each arranged to obtain measurements from a different subset of the detection conductors. The subsets of conductors may share one or more of the detection conductors. Each measurement channel may be arranged to operate in a cyclic manner to select each of the detection conductors within the corresponding subset during a detection cycle 30 and typically the measurement circuitry will comprise sample and hold circuitry for sampling and holding measurements obtained from each measurement channel and an analogue to digital converter for converting measurements held by the sample and hold circuitry into corresponding digital values. In a preferred embodiment, the

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sample and hold circuitry comprises a plurality of first and second capacitors, each first and second capacitor being associated with a respective measurement channel, wherein the sample and hold circuitry is arranged such that during first measurement intervals, signals from the measurement channels are applied to the associated first 5 capacitors and during second measurement intervals, signals from the measurement channels are applied to the associated second capacitors, and wherein during the first measurement intervals the sample and hold circuitry is arranged to couple signals stored on the second capacitors to the analogue to digital converter for conversion into corresponding digital values and during the second measurement intervals the 10 sample and hold circuitry is arranged to couple signals stored on the first capacitors to the analogue to digital converter for conversion into corresponding digital values.

Typically, the digitiser will include control circuitry for generating control signals for controlling selection of the excitation conductors by the excitation circuitry and for 15 generating control signals for controlling selection of the detection conductors by the measurement circuitry. In this case, the control circuitry is preferably arranged to generate the control signals on a cyclic basis and in a free running manner independently of the processing circuitry and is arranged to send a signal to the processing circuitry each measurement cycle (such as at the end thereof) to inform 20 the processing circuitry that measurements are ready to be processed by the processing circuitry. The control circuitry is able to write measurement data into a memory (for example using Direct Memory Access techniques) that is shared with the processing circuitry.

25 In an alternative embodiment, instead of applying the polarity modulation on the excitation signal, it may be applied to the detection signals obtained from the detection conductors. In this alternative, the invention provides a digitiser comprising: a grid of conductors comprising a plurality of excitation conductors and a plurality of detection conductors; excitation circuitry for applying excitation signals to selected excitation 30 conductors; measurement circuitry for obtaining measurements from selected detection conductors; and processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of conductors. The measurement circuitry is arranged to operate in a cyclic

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mannerto select each of the detection conductors during a detection cycle, wherein a detection cycle comprises a sequence of detection intervals during each of which a different pair of neighbouring detection conductors is selected by the measurement circuitry, wherein the measurement circuitry is arranged to polarity modulate a 5 detection signal obtained from each selected detection conductor using a polarity control signal so that the polarity of the detection signal changes during a time that the detection conductor is selected.

Again, the polarity control signal may be periodic and the time that a detection

10 conductor is selected may be an integer multiple of the period of the polarity control signal. This ensures that the signals obtained from each detection conductor do not have significant low frequency content and allows the measurement circuitry to remove low frequency noise from the measurements.

15 In one embodiment, the measurement circuitry selects neighbouring detection conductors during plural consecutive detection intervals in an overlapping manner such that during one detection interval a given selected detection conductor is paired with a first neighbouring detection conductor and during a next detection interval the given selected detection conductor is paired with a second neighbouring detection

20 conductor. Such overlapping can facilitate the switching scheme used to control application of the detection signals through the measurement circuitry and simplifies the hardware design for the application of the polarity control signal to the measurement circuitry.

25 Preferably the measurement circuitry is arranged so that, during an initial detection interval of a detection cycle, detection conductors are selected without overlap with detection conductors selected in a final detection interval of a preceding detection cycle. This helps to reduce the bandwidth requirements of the measurement circuitry which in turn reduces the amount of noise in the obtained measurements.

30

The measurement circuitry may be arranged to select the detection conductors such that a detection conductor selected during a last detection interval of a detection cycle neighbours a detection conductor selected by the measurement circuitry during a first

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detection interval of the detection cycle. This may help to facilitate the subsequent processing of the obtained measurements.

In this alternative, the excitation circuitry may also be arranged to operate in a cyclic 5 manner to select each of the excitation conductors during an excitation cycle, wherein an excitation cycle comprises a sequence of excitation intervals during each of which a different pair of neighbouring excitation conductors is selected by the excitation circuitry. In this case, the excitation circuitry may select neighbouring excitation conductors during plural consecutive excitation intervals in an overlapping manner 10 such that during a first excitation interval a given selected excitation conductor is paired with a first neighbouring excitation conductor and during a second excitation interval the given selected excitation conductor is paired with a second neighbouring excitation conductor.

15 As before, each detection interval may correspond in duration to one excitation interval or each excitation interval may correspond in duration to one detection cycle.

The measurement circuitry is preferably arranged to determine differential measurements of signals obtained from the selected pairs of neighbouring detection 20 conductors, as this reduces noise and in particular common mode noise that may otherwise cause errors in the determined position information.

According to a second aspect, the invention provides a digitiser comprising: a grid of conductors comprising a plurality of excitation conductors and a plurality of detection 25 conductors; excitation circuitry for applying excitation signals to selected excitation conductors; measurement circuitry for obtaining measurements from selected detection conductors; and processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of conductors; wherein the measurement circuitry is arranged to operate in a 30 cyclic manner to select each of the detection conductors during a detection cycle, wherein a detection cycle comprises a sequence of detection intervals during each of which a different pair of neighbouring detection conductors is selected by the measurement circuitry, wherein the measurement circuitry is arranged to select

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neighbouring detection conductors during plural consecutive detection intervals in an overlapping manner such that during one detection interval a given selected detection conductor is paired with a first neighbouring detection conductor and during a next detection interval the given selected detection conductor is paired with a second 5 neighbouring detection conductor and wherein the measurement circuitry is arranged to determine differential measurements of signals obtained from the selected pairs of neighbouring detection conductors.

This aspect of the invention may be combined with the first aspect described above 10 and the alternatives discussed above also apply to this aspect.

According to a third aspect, the invention provides a digitiser comprising: a grid of conductors comprising a plurality of excitation conductors and a plurality of detection conductors; excitation circuitry for applying excitation signals to selected excitation 15 conductors; measurement circuitry for obtaining measurements from selected detection conductors; and processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of conductors; wherein the excitation circuitry is arranged to operate in a cyclic manner to select each of the excitation conductors during an excitation cycle, wherein 20 an excitation cycle comprises a sequence of excitation intervals during each of which a different pair of neighbouring excitation conductors is selected by the excitation circuitry and to which excitation signals with opposite polarity are applied, wherein the excitation circuitry is arranged to select neighbouring excitation conductors during plural consecutive excitation intervals in an overlapping manner such that during a first 25 excitation interval a given selected excitation conductor is paired with a first neighbouring excitation conductor and during a second detection interval the given selected excitation conductor is paired with a second neighbouring excitation conductor and wherein the excitation circuitry is arranged to select the excitation conductors such that an excitation conductor selected during a last excitation interval 30 of an excitation cycle neighbours an excitation conductor selected by the excitation circuitry during a first excitation interval of the excitation cycle. This arrangement helps to reduce electromagnetic interference generated by applying excitation signals to the excitation conductors of the grid whilst reducing the bandwidth requirements of

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the measurement circuitry.

This third aspect also provides a digitiser comprising: a grid of conductors comprising a plurality of excitation conductors and a plurality of detection conductors; excitation 5 circuitry for applying excitation signals to selected excitation conductors; measurement circuitry for obtaining measurements from selected detection conductors; and processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of conductors; wherein the measurement circuitry is arranged to operate in a cyclic 10 manner to select each of said detection conductors during a detection cycle, wherein a detection cycle comprises a sequence of detection intervals during each of which a different pair of neighbouring detection conductors is selected by the detection circuitry, wherein the detection circuitry is arranged to select the detection conductors sequentially and in an overlapping manner from a start detection conductor to an end 15 detection conductor and wherein the start detection conductor neighbours the end detection conductor within said grid.

According to a fourth aspect, the invention provides a digitiser comprising: a grid of conductors comprising a plurality of excitation conductors and a plurality of detection 20 conductors; excitation circuitry for applying excitation signals to selected excitation conductors; measurement circuitry for obtaining measurements from selected detection conductors; and processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of conductors; wherein the measurement circuitry comprises a plurality of 25 measurement channels each arranged to obtain measurements from a different subset of the detection conductors, wherein each measurement channel is arranged to operate in a cyclic manner to select each of the detection conductors within the corresponding subset during a detection cycle, wherein a detection cycle comprises a sequence of detection intervals during each of which a different pair of neighbouring 30 detection conductors is selected by the measurement circuitry; wherein the measurement circuitry comprises sample and hold circuitry for sampling and holding measurements obtained from each measurement channel, wherein the sample and hold circuitry comprises a plurality of first and second capacitors, wherein each

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measurement channel has an associated first and second capacitor, wherein the sample and hold circuitry is arranged such that during first measurement intervals signals from the measurement channels are applied to the associated first capacitors and during second measurement intervals signals from the measurement channels 5 are applied to the associated second capacitors, and wherein during the first measurement intervals the sample and hold circuitry is arranged to couple signals stored on the second capacitors to an analogue to digital converter for conversion into corresponding digital values and during the second measurement intervals the sample and hold circuitry is arranged to couple signals stored on the first capacitors to the 10 analogue to digital converter for conversion into corresponding digital values. This allows higher frequencies to be used, which in turn allows the digitiser to work with larger display areas having a larger number of measurement points to be processed.

According to a fifth aspect, the invention provides a digitiser comprising: a grid of 15 conductors comprising a plurality of excitation conductors and a plurality of detection conductors; excitation circuitry for applying excitation signals to selected excitation conductors; measurement circuitry for obtaining measurements from selected detection conductors; control circuitry for generating control signals for controlling selection of the excitation conductors by the excitation circuitry and for generating 20 control signals for controlling selection of the detection conductors by the measurement circuitry; and processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of conductors; wherein the control circuitry is arranged to generate the control signals on a cyclic basis and in a free running manner independently of the 25 processing circuitry and is arranged to send a signal to the processing circuitry each measurement cycle to inform the processing circuitry that measurements are ready to be processed by the processing circuitry. This allows the control circuitry and the processing circuitry to be able to function at high speed even for large digitiser sizes (above 38cm diagonal).

30

According to a sixth aspect, the invention also provides a method of manufacturing the digitisers, the method comprising the following steps: applying a first conductive strip to an insulating substrate along a Y-direction; arranging one or more conductors on

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th e insulating substrate that extend along an X-direction and that electrically connect at one end to the first conductive strip; applying a second conductive strip to the insulating substrate along the X-direction; arranging one or more conductors on the insulating substrate that extend along the Y-direction and that electrically connect at 5 one end to the second conductive strip; and cutting, etching or otherwise breaking the first and second conductive strips to form separate conductive pads to allow connection of the conductors to electronics of the digitiser.

For example, in one embodiment of this sixth aspect, the method comprises the 10 following steps: applying a first adhesive copper busbar strip to the PVB sheet along the Y-direction; using robotic arm thermally bonding a thin metallic wire into the predefined serpentine pattern along the X-direction of the PVB sheet perpendicular to the first copper busbar; applying an additional conductive adhesive copper busbar strip on the top of the first copper busbar in order to sandwich the thin metallic wire 15 between the two copper strips; turning over the PVB sheet and applying a second copper busbar strip to the PVB sheet along the X-direction, perpendicular to the first busbar; using robotic arm thermally bonding a thin metallic wire into the predefined serpentine pattern along the Y-direction of the PVB sheet perpendicular to the second copper busbar; cutting PVB material to the exact size; applying a much wider 20 conductive adhesive copper strip on the top of the second busbar and tucking in the remaining width of this copper foil underneath the PVB material to present the electrical contact surface for the second busbar on both surfaces of the PVB material; and punching through the copper busbar between adjacent arms of the thin wire in order to create electrically isolated contact pads for each wire belonging to the X-Y 25 wire grid; placing the PVB foil between two sheets of glass of slightly dissimilar size in such a manner that allows to leave exposed the PVB foil near the areas with the contact pads; applying a temporary adhesive strip to cover exposed areas of the PVB foil and the copper contact pads; carrying out the vacuum lamination of the glass at elevated temperature; removing after the lamination process the temporary adhesive 30 strip to expose contact pads; attaching a first and second PCBs on the top of the first and second busbar; soldering contact pads of the PCB to the contact pads at the PVB; and connecting the electric cable between the first and second PCB to supply control signals for the excitation channels.

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In another example of the sixth aspect, the method comprises the following steps: applying a first layer of double-sided mounting adhesive on a surface of the cardboard; applying a first adhesive copper busbar strip to the cardboard along the Y-5 direction; using robotic arm bonding a thin metallic wire into the predefined serpentine pattern along the X-direction of the cardboard perpendicular to the first copper busbar; applying a second double-sided mounting adhesive over the array of bonded thin wires but without covering the first copper busbar; applying a second adhesive copper busbar strip to the cardboard along the X-direction; using robotic arm bonding a thin 10 metallic wire into the predefined serpentine pattern along the Y-direction of the cardboard perpendicular to the second copper busbar; cutting cardboard to the exact size; applying wide conductive adhesive copper strip on the top of the first and second busbar and tucking in the remaining width of this copper foil underneath the cardboard to present the electrical contact surface for the first and second busbar on both 15 surfaces of the cardboard; punching through the copper busbar between adjacent arms of the thin wire in order to create electrically isolated contact pads for each wire belonging to the X-Y wire grid; applying third double sided mounting adhesive over the array of bonded wires also covering the first and second busbar; attaching cardboard with the integrated wire grid to the inner surface of the white board; attaching first and 20 second PCBs on the top of the first and second busbar; soldering contact pads of the PCB to the contact pads at the cardboard; and connecting the electric cable between the first and second PCB to supply control signals for the excitation channels.

In another example of the sixth aspect, the method comprises the following steps: 25 applying optically clear double-sided mounting adhesive on a surface of the protective glass; attaching first PCB along the Y-edge of the glass substrate: using robotic arm with multiple feeds for wires, bonding a regular array of thin metallic wires along the X-direction of the glass substrate perpendicular to the first PCB; terminating each wire from the created first array of thin wires at the first PCB using ultrasonic wedge 30 bonding to the gold plated copper based PCB pads; applying optically clear double-sided mounting adhesive over the array of bonded thin wires; attaching second PCB along the X-edge of the glass substrate; using robotic arm with multiple feeds for wires, bonding a regular array of thin metallic wires along the Y-direction of the glass

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substrate perpendicular to the second PCB; terminating each wire from the created second array of thin wires at the second PCB using ultrasonic wedge bonding to the gold plated copper based PCB pads; spraying optically clear UV curable liquid lamination over the second array of thin metallic wires in order to seal the free 5 adhesive surface and cure with UV light; applying extra conductive adhesive to pot the termination of thin metallic wires to PCB; attaching a flat cable between the second PCB and the first PCB to provide control signals for the excitation channels.

These and other aspects of the invention will become apparent from the following 10 detailed description of embodiments and alternatives that are described by way of example only, with reference to the following drawings in which:

Figure 1a schematically illustrates X and Y conductors forming part of a touch screen digitiser;

15

Figure 1b illustrates electric field lines that couple from an X conductor of Figure 1a with a Y conductor at a point of intersection between the conductors;

Figure 1c illustrates the field lines shown in Figure 1b in the presence of a user's 20 finger and illustrating the change in coupling between the X conductor and the Y conductor;

Figure 2 is a plot illustrating the rise in power consumption cost of the digitiser with the size of the display, for different conductor technologies;

25

Figure 3 is a schematic overview of an X-Y digitiser system illustrating the grid of X-Y conductors and the associated excitation and detection electronics;

Figure 4 schematically illustrates in more detail the excitation circuitry used to apply 30 excitation signals to excitation conductors (the x conductors) forming part of the grid shown in Figure 3;

Figure 5 illustrates in more detail switching multiplexors used to selectively apply

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excitation signals to the excitation conductors;

Figure 6 schematically illustrates a delay line used to generate a sequence of delayed enable signals used to control the multiplexors shown in Figure 5;

5

Figure 7 illustrates the control signals that are generated by the circuitry shown in Figure 6;

Figure 8 schematically illustrates a number of consecutive detection intervals during 10 which detections are made on adjacent detection conductors;

Figure 9 is a timing diagram illustrating in more detail the excitation signals that are applied sequentially to neighbouring excitation conductors at the end of one detection interval and the start of the next detection interval;

15

Figure 10 schematically illustrates detection conductors (Y conductors) forming part of the grid shown in Figure 3 and the way in which these detection conductors are coupled to measurement channels forming part of the detection circuitry;

20 Figure 11 schematically illustrates in more detail switching circuitry used to selectively connect pairs of detection conductors to amplification and filtering circuit;

Figure 12 is a timing diagram illustrating an overall measurement cycle in which a measurement is obtained for each conductor intersection point in the grid of 25 conductors shown in Figure 3;

Figure 13 is a circuit diagram illustrating preferred amplification and filtering circuit used to amplify and filter a differential measurement obtained from a selected pair of detection conductors;

30

Figure 14a schematically illustrates a spectrum of the signal obtained after demodulation that is to be amplified and filtered by the amplification and filtering circuit shown in Figure 13;

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Figure 14b illustrates a desired filter response for the amplification and filtering circuit shown in Figure 13 that can be used to filter the signal from the demodulator to remove the high frequency demodulation components whilst maintaining the signal 5 components that will vary with the presence of the user's finger;

Figure 15 illustrates the form of various control signals and the form of an output signal from the amplification and filtering circuit at the end of one detection interval and at the start of the next detection interval;

10

Figure 16 illustrates the form of various control signals and the form of an output signal from the amplification and filtering circuit when a user's finger is located over the grid of conductors;

15 Figure 17a is a block diagram illustrating in more detail the main components of sample and hold circuitry used to sample and hold the signals obtained from the amplification and filtering circuits for conversion into digital values by an analogue to digital converter;

20 Figure 17b is a signal diagram illustrating control signals used to control the sample and hold circuitry shown in Figure 17a and illustrating an analogue to digital converter trigger signal used to trigger the analogue to digital converter to make a conversion;

Figure 18 is a block diagram illustrating the main components of the excitation and 25 control signal logic shown in Figure 3;

Figure 19 is a flow chart illustrating a software routine used by a digital processing unit forming part of the digitiser electronics shown in Figure 3 that controls the way in which the digital values obtained from the analogue to digital converter are processed 30 during each measurement cycle;

Figure 20 illustrates exemplary circuit components used in the amplification and filtering circuit shown in Figure 13 to provide a desired pass band filter response;

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Figure 21 is a timing diagram illustrating the timing of the excitation signals applied to adjacent excitation conductors when no demodulation is performed;

5 Figure 22 illustrates voltages measured at different points of the circuitry shown in Figure 20 in an embodiment where no demodulation is performed on the signals obtained from the detection circuitry;

Figure 23 is a timing diagram illustrating the timing of the excitation signals applied to 10 adjacent excitation conductors when the excitation frequency is twice that of the polarity control signal;

Figure 24 illustrates voltages measured at different points of the circuitry shown in Figure 20 when the frequency of the excitation signal is twice the frequency of the 15 polarity control signal;

Figure 25 illustrates in the way in which alternate excitation conductors are connected to Vcc to facilitate generation of the excitation signals shown in Figure 23;

20 Figure 26 is a timing diagram illustrating the timing of the excitation signals applied to adjacent excitation conductors when the excitation frequency is three times that of the polarity control signal;

Figure 27 illustrates voltages measured at different points of the circuitry shown in 25 Figure 20 when the frequency of the excitation signal is three times the frequency of the polarity control signal;

Figure 28 is a timing diagram illustrating the timing of the excitation signals applied to adjacent excitation conductors when the excitation frequency is four times that of the 30 polarity control signal;

Figure 29 illustrates voltages measured at different points of the circuitry shown in Figure 20 when the frequency of the excitation signal is four times the frequency of the

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polarity control signal;

Figure 30 schematically illustrates alternative excitation circuitry used to apply excitation signals to the excitation conductors in which the polarity control signal is 5 applied to the excitation signals that are applied to the excitation conductors;

Figure 31 is a timing diagram illustrating the control signals used to control the application of the polarity modulated excitation signals to the adjacent excitation conductors;

10

Figure 32 is a timing diagram illustrating alternative control signals used to control the application of the polarity modulated excitation signals to the adjacent excitation conductors when alternate excitation conductors are held at Vcc using the circuitry of Figure 25;

15

Figure 33 illustrates the form of alternate switching circuitry used to switch and demodulate the signals from pairs of detection conductors for the embodiment where the excitation signals are polarity modulated;

20 Figure 34 illustrates the form of various control signals and the form of an output signal from the amplification and filtering circuit at the end of one detection interval and at the start of the next detection interval;

Figure 35 illustrates the form of various control signals and the form of an output 25 signal from the amplification and filtering circuit when a user's finger is provided over the grid of conductors;

Figure 36 is a block diagram illustrating alternative sample and hold circuitry for processing signals obtained from two amplification and filtering circuits;

30

Figure 37 is a signal diagram illustrating the control signals used to control the sample and hold circuitry shown in Figure 36 and illustrating an analogue to digital converter trigger signal used to control the triggering of the analogue to digital converter;

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Figure 38 illustrates alternative excitation circuitry used to excite the excitation conductors of the grid shown in Figure 3 in which there is no extra multiplexor input;

5 Figure 39 illustrates timing diagrams and signals applied to the excitation conductors with the circuitry shown in Figure 38 and showing the form of an output obtained from the amplification and filtering circuit;

Figure 40a is a spectrum plot illustrating a spectrum of a signal obtained from the 10 demodulator in this embodiment, showing an extra frequency component at the frequency corresponding to the excitation cycle;

Figure 40b illustrates a bandwidth of the amplification and filtering circuit required to filter the signal shown in Figure 40a in order to recover the desired signal whilst 15 filtering out high frequency components of the demodulation signal and illustrating the increased bandwidth of the circuitry over the corresponding bandwidth of the circuitry used in the first embodiment;

Figure 41 illustrates the control and excitation signals applied in this embodiment and 20 a signal obtained from one of the amplification and filtering circuits at the boundary between two detection intervals;

Figure 42 illustrates the same control and excitation signal shown in Figure 41, but showing the output from the amplification and filtering circuit in the presence of a 25 finger over the grid;

Figure 43 illustrates a further alternative way of applying the excitation signals to the excitation conductors that sweeps the excitation signal back and forth across the conductor grid during each excitation cycle;

30

Figure 44 illustrates a further alternative way of connecting the detection conductors through the detection switching blocks;

-21 -

Figure 45 illustrates the timing of control and excitation signals used in a further alternative embodiment in which the cyclic switching of the excitation conductors and the cyclic switching of the detection conductors are reversed;

5 Figure 46 is a timing diagram illustrating the control signals used to control the multiplexing of the excitation signals to the excitation conductors in this embodiment;

Figure 47a is a block diagram illustrating switching circuitry used in this alternative embodiment to control the switching of signals obtained from pairs of detection 10 conductors through the amplification and filtering circuit;

Figure 47b is a circuit diagram illustrating an alternative amplification and filtering circuit used to amplify and filter a differential measurement obtained from a selected pair of detection conductors according to the switching circuitry shown in the Figure 15 47a;

Figure 48 is a timing diagram illustrating the way in which the signals from the detection conductors shown in Figure 47 are switched through the switching circuitry and showing an output from the amplifier and filtering circuit;

20

Figure 49 is a diagram illustrating the way in which the signals from the detection conductors shown in Figure 45 are switched through the switching circuitry and showing an output from an amplifier and filtering circuit when a finger is provided adjacent the conductor grid;

25

Figure 50 is a timing diagram for a modification to the embodiment of Figures 45 to 49 in which there is no spare input to the detection switching block;

Figure 51a is a plot illustrating a spectrum of a signal output from a demodulator in the 30 alternative embodiment of Figure 50 which illustrates an additional peak in the spectrum of the measurement signal;

Figure 51b illustrates a plot of the bandwidth of the amplification and filtering circuits

-22 -

for filtering out the high frequency signals shown in Figure 51a in order to recover the desired signal whilst filtering out high frequency components of the demodulation signal and illustrating the increased bandwidth of the circuitry over the corresponding bandwidth of the circuitry used in the first embodiment;

5

Figure 52 is a circuit diagram illustrating the connection of detection conductors to switching multiplexers used in a switching block that is adjacent to the switching block shown in Figure 33;

10 Figure 53 is a timing diagram illustrating the timings when the signals from the different detection conductors are multiplexed through the switching block shown in Figure 52;

Figure 54 is a timing diagram illustrating the timings when the signals from the 15 different detection conductors are multiplexed through the switching block shown in Figure 33 in which the overlap of signals detected from adjacent detection conductors overlap for one period of the polarity modulation signal and showing an output from the amplification and filtering circuit when no finger is present;

20 Figure 55 is a timing diagram showing the same timing signals as shown in Figure 54 and the output from the amplification and filtering circuit when a user's finger is over the grid;

Figure 56 is a diagram illustrating switching circuitry used in an embodiment where a 25 single polarity of excitation signal is applied to a selected excitation conductor;

Figure 57 is a block diagram illustrating an alternative form of switching circuitry used to switch the signals obtained from the detection conductors through to the amplification and filtering circuit;

30

Figure 58 is a block diagram illustrating an alternative form of digitiser that can detect the position of one or more user fingers using capacitive sensing techniques and that can detect one or more styli using inductive sensing techniques;

-23 -

Figure 59 is a physical arrangement known from the prior-art for integrating sensing X-Y wire grid with an electronics unit;

5 Figure 60 is a physical arrangement of wires used for heated glass in the automotive windscreen manufacturing field;

Figure 61 is a flow chart illustrating manufacturing steps that can be used to manufacture the X-Y conductor grid structure for a glass screen overlay and for 10 integrating it with digitiser electronics;

Figure 62a schematically illustrates the laying of a first set of conductors over a PVB foil substrate;

15 Figure 62b illustrates the laying of a second set of conductors over the first set of conductors on the opposite side of the same PVB substrate;

Figure 63a and 63b illustrates the attachment of an additional conductive adhesive copper strip on both sides of the PVB foil along the edge with the second copper 20 busbar;

Figure 64 illustrates the process of electrically isolating individual wires in the X-Y grid of conductors and forming a set of contact pads out of the originally continuous first and second busbars via punching out narrow strips of copper material;

25

Figure 65a illustrates the physical arrangement of the top and bottom glass before the beginning of the lamination process;

Figure 65b illustrates the attachment of the first and second PCB to the PVB foil after 30 the lamination of the glass panel;

Figure 66a illustrates a cross-section through the laminated glass panel with integrated electronics and the X-Y grid of conductors and is specifically showing a

-24 -

solder joint connection between the contact pads;

Figure 66b illustrates the usage of an additional temporary non-stick support during the manufacturing process to allow having the same size of top and bottom glass 5 panels;

Figure 67a illustrates the concept of moulding the PVB tail at a substantial angle to the glass surface during the lamination process in order to reduce the size of the bezel around the screen in the finished interactive display system;

10

Figure 67b illustrates the attachment of the PCB with electronics to the PVB tail shaped at the angle to the glass surface;

Figure 68 illustrates the attachment of the PCB with electronics to the PVB at 90 15 degrees to the surface of the glass for a nearly zero width bezel interactive display mounting.

Figure 69 is a flow chart illustrating manufacturing steps that can be used to manufacture the X-Y conductor grid digitiser structure for a whiteboard application;

20

Figure 70a schematically illustrates the laying of a first set of conductors over a cardboard substrate;

Figure 70b illustrates the laying of a second set of conductors over the first set of 25 conductors on the cardboard substrate;

Figure 71a illustrates the process of electrically isolating individual wires in the X-Y grid of conductors and forming a set of contact pads out of the originally continuous first and second busbars via punching out narrow strips of copper material;

30

Figure 71b illustrates the attachment of the first and second PCBs to the cardboard substrate;

-25-

Figure 72 is a flow chart illustrating manufacturing steps that can be used to manufacture the X-Y conductor grid structure by bonding wires directly to the PCB;

Figure 73a schematically illustrates the laying of a first set of conductors on a 5 substrate;

Figure 73b illustrates the laying of a second set of conductors over the first set of conductors;

10 Figure 74a illustrates the way in which ends of the conductors are ultrasonically bonded to a printed circuit board; and

Figure 74b illustrates a cross-section through the X-Y grid of conductors made using the technique shown in Figure 73.

15

First Embodiment

Overview

Figure 3 is a schematic block diagram illustrating the main components of the X-Y digitiser 1 used in this embodiment to sense user inputs from one or more fingers or 20 from one or more conductive styli (not shown). The digitiser includes a grid 3 of excitation conductors 5-0, 5-1 ... 5-Xmax-1 and a plurality of detection conductors 7-0, 7-1 ... 7-Ymax. In this embodiment, as schematically illustrated in Figure 3, the excitation conductors 5 and the detection conductors 7 are arranged in orthogonal directions. When the digitiser 1 is used to form a touch screen, the excitation 25 conductors 5 and the detection conductors 7 are overlaid on top of the display screen (not shown).

The grid of conductors 3 is connected to a microcontroller 9 that controls the application of excitation signals to the excitation conductors 5 and that processes the 30 signals obtained from the detection conductors 7. A shown in Figure 3, the microcontroller 9 includes excitation and control signal logic 11 that generates the appropriate excitation and control signals used for controlling the operation of the digitiser 1 to obtain the measurements from the X-Y grid 3. The microcontroller 9 also

-26 -

includes an analogue to digital converter (ADC) 13 which converts the analogue measurements held by sample and hold circuitry 15 into digital values which are then stored in memory 17. The microcontroller 9 also includes a measurement processing unit 19 which processes the digital measurements stored in memory 17 to determine 5 the location(s) of any user touches over the grid 3 and which then reports these locations to a host device via a host interface unit 21. As will be explained in more detail below, during normal operation, the excitation and control signal logic 11 operates independently of the measurement processing unit 19 and updates the measurements obtained from the grid 3 at a defined measurement cycle rate. At the 10 end of each measurement cycle, the excitation and control signal logic 11 passes a frame reference signal 22 to the measurement processing unit 19 informing the measurement processing unit 19 that the next set of measurements have been stored in the shared memory 17 and are ready for processing. Whilst the excitation and control signal logic 11 is controlling the grid 3 to obtain the next set of measurements, 15 the measurement processing unit 19 processes the previous set of measurements obtained during the last measurement cycle.

In this embodiment, the X-Y digitiser 1 is arranged to determine measurements of the mutual capacitance between each excitation conductor 5 and each detection 20 conductor 7 at their intersection point (referred to below as the measurement points). To do this, the excitation and control signal logic 11 sequentially applies an excitation signal to selected excitation conductors until the excitation signal has been applied to each of the excitation conductors 5 along the grid 3. Excitation channels 23 are provided for controlling the selection of the excitation conductor(s) that are selected, 25 during a given excitation interval, to receive the excitation signal. Similarly, during a given detection interval, the excitation and control signal logic 11 arranges for the signals from selected detection conductors 7 to be measured whilst the selected excitation conductor(s) are being energised. In this embodiment, the excitation and control signal logic 11 selects the detection conductors 7 from which measurements 30 will be obtained and then controls the scanning of the excitation signal across all of the excitation conductors 5. The excitation and control signal logic 11 then selects the next set of detector conductors 7 from which measurements will be obtained and then again scans the excitation signal across all of the excitation conductors 5. Once this

-27-

processes has been completed for all of the detection conductors 7, the measurement cycle ends and the excitation and control signal logic 11 sends the frame reference signal 22 to the measurement processing unit 19 telling it that the next set of measurements are ready in memory 17; and the excitation and control signal logic 11 5 starts the measurement process again. As will become clear from the following description, the excitation and control signal logic 11 operates continuously in a free running manner using a number of free-running clock signals and PWM signals.

Excitation Channels

10 Figure 4 is a block diagram illustrating in more detail the multiplexing and control signal structure of the excitation channels 23 used in this embodiment. As shown in Figure 4, each of the excitation conductors 5 is connected to a respective input of one of the excitation switching blocks 50-0 to 50-Mmax. In this embodiment, each of the excitation switching blocks 50 has eight outputs each for connection to a respective 15 one of the excitation conductors 5, with the exception of the last output of the last excitation switching block 50-Mmax, which is not connected to an excitation conductor 5. The significance of this "missing" excitation conductor will become clear from the subsequent description.

20 The number of excitation conductors 5 and the number of multiplexors used in the excitation channels 23 depends on the size of the display screen (not shown) with which the grid 3 of conductors is designed. As an example, a screen having a diagonal dimension of about 203cm (80 inches) and with a 16:9 aspect ratio, has a dimension in the X direction of approximately 177cm and a dimension in the Y 25 direction of approximately 100cm. If thirty seven excitation switching blocks 50 are provided each having eight outputs, then this allows for connection of two hundred and ninety five excitation conductors (whilst keeping the last output un-connected). Two hundred and ninety five excitation conductors 5 arrayed evenly along the 177cm dimension, gives a spacing between adjacent excitation conductors 5 of 30 approximately 6mm, which is sufficient to sense a user's finger and/or conductive stylus with an accuracy of 1 mm over the whole surface of the display.

Figure 4 also shows the excitation and control signals output by the excitation and

-28 -

control signal logic 11 to the excitation channels 23. These signals include the following:

ex_clock - this is the signal that is used to form the excitation signal that is applied to 5 the selected excitation conductors 5. As shown in Figure 4, the ex clock signal is inverted by an inverter 53 to form two excitation signals: ex- and ex+, which are applied, via resistors 54-a and 54-b, to each excitation switching block 50. The resistors 54 act with capacitors (shown in Figure 5) that are attached to each excitation conductor 5 to filter out high frequency components of the excitation signal.

10

in1, in2, in1_shifted and in2_shifted - these are control signals used to select which of the multiplexor output terminals are connected to the multiplexor input terminals.

enable1_0 - this is an enable signal that is used to enable excitation switching block 15 50-0. As shown in Figure 4, the enable1_0 is delayed by respective delay line circuits 55-0 to 55-Mmax that are connected together in a serial manner. Each delay line circuit 55 outputs a shifted version of the input enable signal to the corresponding excitation switching block 50.

20 delayl & delay2 - these are control signals for controlling the delays introduced by the delay line circuits 55.

Excitation switching block

Figure 5 is a block diagram illustrating in more detail the content of each of the 25 excitation switching blocks 50. As shown in Figure 5, each excitation switching block 50 includes two one-input and four-output multiplexors 65-1 and 65-2. Multiplexor 65-1 receives at its input the positive excitation signal (ex+) and multiplexor 65-2 receives at its input the negative input signal (ex-). The output, to which the input of the multiplexors 65 is connected, is selected based on the selection signals - in1 and in2 30 for multiplexor 65-1 and inI shifted and in2_shifted for multiplexor 65-2. Additionally, the multiplexors 65 are arranged to be open circuit until they are enabled by a respective enable signal - enablel for multiplexor 65-1 and enable1_shifted for multiplexor 65-2. As discussed above, enable1_shifted is generated by delaying the

-29-

enablel signal by the associated delay line circuit 55.

In this embodiment, the control of the connection through each multiplexor 65 is defined by the following truth table:

5

in1/in1_shifted in2/in2_shifted

Selected o/p

0

0

1

0

1

2

1

0

3

1

1

4

Figure 5 also shows the way in which the excitation switching blocks 50 are connected to the excitation conductors 5 via suitable grounding resistors 61-0 to 61-7 and 10 grounding capacitors 63-0 to 63-7. Each capacitor 63 acts to filter out high frequency components of the excitation signals (ex+, ex-) switched through the multiplexors 65. These capacitors 63 also provide an efficient grounding of the excitation conductors 5 which are not selected by the multiplexor 65. This reduces any induced voltage in the non selected excitation conductors that would otherwise float when not connected to 15 the excitation input. Such induced voltage can be caused, for example, by the above described cross-talk between adjacent excitation conductors 5. The resistors 61 are provided in order to avoid any uncontrolled accumulation of static charge on the excitation conductors 5 which might otherwise destroy the electronics once the excitation conductor 5 is selected by the multiplexor 65. In particular, any DC charge 20 built up on the excitation conductors 5 will pass to ground through the resistor 61.

Delay Line Circuits

Figure 6 is a block diagram illustrating the components of two adjacent delay line circuits 55-m-1 and 55-m; and illustrating the way in which they are connected 25 together. As shown in Figure 6, each delay line circuit 55 includes a first latch 71-1 and a second latch 71-2. The output of the first latch 71-1 is connected to the input of the second latch 71-2; and the output from the second latch 71-2 is connected to the input of the first latch 71-1 of the next delay line circuit 55. The output of the first latch

-30-

71-1 provides the shifted enable signal to the corresponding excitation switching block 50. As shown, the first latches 71-1 are clocked by the delayl control signal and the second latches 71-2 are clocked by the delay2 signal. As will be explained in more detail below, the arrangement of the delay line circuits 55 and of the various control 5 signals allow the excitation signals (ex+ and ex-) to be applied sequentially to adjacent excitation conductors of the grid 3 in an overlapping manner.

Timing diagrams

Figure 7 is a timing diagram illustrating the timings of the control signals used in 10 Figure 6. In particular, Figure 7 shows the delayl control signal and the delay2 control signal that are used to clock the latches 71 within each delay line circuit 55. As shown, both delayl and delay2 are square wave signals, with delay2 being shifted in time by an amount At_e. Figure 7 also shows the enable1_(m-1) signal that is input to the first latch 71-1 of delay line circuit 55-m-1. This enable signal is latched through 15 the first latch 71-1 on the rising edge of delayl to generate the shifted enable signal enable1_shifted_(m-1). As shown, the enable1_shifted_(m-1) is then clocked through the second latch 71-2 by the rising edge of the delay2 signal to generate the input enable signal (enable1_m) for the next delay line circuit 55-m. Thus, as can be seen from Figure 7, each delay line circuit 55 operates to generate two enable signals: 20 enable1_shifted that is used to enable multiplexor 65-2 (shown in Figure 5) and the enable signal (enablel) for the next multiplexor/delay circuit. When an enable signal is low, the corresponding multiplexor 65 is enabled and when the enable signal is high, the corresponding multiplexor 65 is disabled. Therefore, each excitation switching block 50 will be enabled during the period T_mux shown in Figure 7.

25

It should be noted that there is a phase shift between the edges of the control signals and the excitation clock signal. It is preferable to select and deselect the excitation conductor 5 at a moment in time when the excitation signal is at the zero value. This makes the overall system less sensitive to the time shift of the excitation signals along 30 the length of the grid 3, which might exceed two meters. The overall phase shift can range from 25% to less than 5% of the excitation clock signal period.

Figure 8 shows the cyclic nature of each of the enable signals. In particular, as

-31 -

discussed above, for each set of detection conductors 7 that is selected, the excitation and control signal logic 11 sequentially applies the excitation signal across all of the excitation conductors 5. As shown in Figure 8, the period of this excitation cycle is given as T_ec. For the example size of display discussed above, where there are 5 thirty seven excitation switching blocks 50, the excitation cycle T ec will be thirty seven times the period T_mux during which each excitation switching block 50 is enabled in turn. Figure 8 shows a portion (corresponding to three consecutive excitation cycles) of the overall measurement cycle and shows the enable signals used to enable the first and last excitation switching blocks 50. In the first of the three 10 excitation cycles, detections are made with respect to detection conductors Ym and Ym+i; during the second of the three excitation cycles detections are made with respect to detection conductors Ym+2 and Ym+i; and during last of the three excitation cycles detections are made with respect to detection conductors Ym+2 and Ym+3. As shown, in each excitation cycle, the enable signals for the first excitation switching 15 block 50-0 are brought low at the start of the excitation cycle, followed by the enable signals for the second excitation switching block 50-1 etc, until the end of the excitation cycle when the enable signals for the last excitation switching block 50-Mmax are brought low.

20 Figure 9 is a timing diagram illustrating the way in which the excitation signals are sequentially applied to the excitation conductors 5 at a timing around the end of the first excitation cycle shown in Figure 8 and at the start of the second excitation cycle shown in Figure 8 (and labelled 79 in Figures 8 and 9). The time between each of the vertical dashed lines corresponds to the shift in time between the delayl and delay2 25 control signals (i.e. At_e) shown in Figure 7 and will be referred to in this embodiment as an excitation interval. As shown, during the excitation interval Atk-1_e, the enable signals for the last excitation switching block 50-Mmax are low and the multiplexor select signals in1 and in2 have values 1 and 0 respectively and in1_shifted and in2_shifted have values 1 and 1 respectively. As a result (c.f. the above truth table 30 and the multiplexor connection shown in Figure 5), excitation switching block 50-Mmax will output the positive excitation signal (ex+) to excitation conductor Xmax-1 and will output the negative excitation signal (ex-) to excitation conductor Xmax-2. In this way, two adjacent excitation conductors 5 on the grid 3 are driven with

-32-

complimentary (180° phase shifted) excitation signals, which helps to reduce electromagnetic interference caused by applying the excitation signals to the selected excitation conductors 5.

5 In the next excitation interval Atke (the last one in the present excitation cycle) the enable signals for the last excitation switching block 50-M are still low and the multiplexor select signals in1 and in2 remain unchanged. Therefore, the positive excitation signal (ex+) continues to be applied to the excitation conductor Xmax-1. However, in this excitation interval the multiplexor select signals in1_shifted and 10 in2_shifted now have values 1 and 0 respectively, which cause multiplexor 65-2 within excitation switching block 50-Mmax to connect the negative excitation signal (ex-) to output 3, which (as can be seen from Figures 4 and 5) is not connected to an excitation conductor. This "missing" excitation conductor is notionally labelled Xmax in Figure 4 and in Figure 9 for ease of explanation. As shown at the top of Figure 9, 15 the end of excitation interval Atk_e corresponds to the end of the excitation cycle during which detections are made with respect to detection conductors Ym+i and Ym+2. The excitation sequence then immediately begins again in the next excitation interval At1_e where the enable signal (enable 1_0) used to enable the first excitation switching block 50-0 is again set to a low value. As shown, the multiplexor select 20 signals in 1 and in2 both have value 0, which means that the positive clock signal (ex+) is applied to excitation conductor X0. During this first excitation interval of the excitation cycle, the shifted enable signal (enable1_shifted) is still high and therefore the second multiplexor 65-2 (shown in Figure 5) of excitation switching block 50-0 is not enabled and the negative excitation signal is not applied to any of the excitation 25 conductors 5. In the next excitation interval At2_e, the shifted enable signal (enable1_shifted) goes low which enables the second multiplexor 65-2 in the first excitation switching block 50-0. During this second excitation interval, the shifted multiplexor control signals (inl shifted and in2_shifted) both have value 0, and therefore the negative excitation signal (ex-) is applied to excitation conductor X1; and 30 the multiplexor select control signals in 1 and in2 have not changed and therefore, the positive excitation signal (ex+) is still applied to excitation conductor X0. Thus, during the excitation interval At2_e, the positive excitation signal is applied to excitation conductor X0 and the negative excitation signal is applied to the adjacent excitation

-33-

conductor X1. Similarly, during the third excitation interval At3_e, the positive excitation signal is applied to excitation conductor X2 and the negative excitation signal is applied to the adjacent excitation conductor X1; during the fourth excitation interval At4_e, the positive excitation signal is applied to excitation conductor X2 and 5 the negative excitation signal is applied to the adjacent excitation conductor X3; during the fifth excitation interval At5_e, the positive excitation signal is applied to excitation conductor X4 and the negative excitation signal is applied to the adjacent excitation conductor X3, etc. Thus, in this embodiment, excitation signals are applied to the excitation conductors sequentially and in an overlapping manner so that during each 10 excitation interval, except for the first and last intervals (At_1e and Atk_e) of an excitation cycle, positive and negative excitation signals are applied to adjacent conductors.

As those skilled in the art will appreciate from Figure 9, the reason that there are no 15 overlapping excitation signals during intervals At1_e and Atk_e is because the last output from the excitation switching block 50-Mmax is not connected to an excitation conductor. As will be explained later, this is advantageous because it helps to reduce the bandwidth requirements of the measurement channels used to process the signals from the detection conductors 7.

20

Measurement Channels

Figure 10 is a block diagram illustrating in more detail the switching and control signal structure of the measurement channels 25 used in this embodiment. As shown in 25 Figure 10, each of the detection conductors 7 (labelled Y0 to Ymax) is connected to a respective input of one of the detection switching blocks 80-0 to 80-Nmax. In this embodiment, each of the detection switching blocks 80 has eight inputs, each for connection to a detection conductor 7. As shown in Figure 10, the last detection conductor that is connected to one switching block 80-L is also connected to the input 30 of the next detection switching block 80-L+1. The significance of this shared detection conductor will become clear from the subsequent description.

The number of detection switching blocks 80 used in the measurement channels 23

-34-

depends on the number of detection conductors 7 (and hence on the size of the display screen) and the time available to switch the signals from the detection conductors 7 through each measurement channel. For the example screen discussed above having a dimension in the Y direction of approximately 100cm and 169 5 detection conductors 7 arrayed evenly along the Y direction (gives a spacing between adjacent detection conductors 7 of approximately 5.9mm) requires twenty four detection switching blocks 80 that have eight inputs each (because detection conductors are shared between adjacent detection switching blocks 80). Of course, fewer detection switching blocks 80 may be used if they each have more inputs or if 10 there are fewer detection conductors 7. For example, it is possible to use eleven detection switching blocks 80 with sixteen inputs each serving 166 detection conductors 7.

Figure 10 also shows that each detection switching block 80 has two outputs that are 15 input to a respective amplification and filtering circuit 83-0 to 83-Nmax. The outputs from the amplification and filtering circuits 83 are then input to the sample and hold circuitry 15 for sampling and subsequent conversion into digital values by the analogue to digital converter 13.

20 Figure 10 also shows the control signals output by the excitation and control signal logic 11 to control the measurement channels 25. These signals include the following:

in4, in3, in3_shifted and in4_shifted - these are control signals used to select which of the detection switching block input terminals (and hence which detection 25 conductors 7) are connected to the outputs of the detection switching block 80.

ex_clock_shifted - this is a clock signal having the same frequency as the excitation signal that is applied to the excitation conductors 5. The phase of this clock signal is shifted slightly compared to the phase of the excitation signal, to account for phase 30 delays introduced in the digitiser. This clock signal is used to demodulate the signal received on the selected detection conductors 7.

polarity - this is a control signal used to polarity modulate the signal from each

-35-

detection conductor 7.

Detection Switching Block

Figure 11 is a block diagram illustrating in more detail the content of one of the 5 detection switching blocks 80-L. The other detection switching blocks 80 used in this embodiment have the same structure. As shown in Figure 11, detection switching block 80-L includes two four-input and one-output multiplexors 91-1 and 91-2. As shown, input 1 of multiplexor 91-1 is connected to detection conductor Ym; input 2 of multiplexor 91-1 is connected to detection conductor Ym+2; input 3 of multiplexor 91-1 10 is connected to detection conductor Ym+6 and input 4 of multiplexor 91-1 is connected to detection conductor Ym+4. Similarly, input 1 of multiplexor 91-2 is connected to detection conductor Ym+i; input 2 of multiplexor 91-2 is connected to detection conductor Ym+3; input 3 of multiplexor 91-2 is connected to detection conductor Ym+7 and input 4 of multiplexor 91-2 is connected to detection conductor Ym+5. As shown in 15 Figure 11, detection conductor Ym and detection conductor Ym+7 are also connected to corresponding inputs of the multiplexors 91 in the adjacent detection switching blocks 80. Thus, detection conductor Ym is connected to input 3 of multiplexor 91-2 of detection switching block 80-L-1 and detection conductor Ym+7 is connected to input 1 of multiplexor 91-1 of detection switching block 80-L+1. Of course, the first and last 20 detection switching blocks 80-0 and 80-Nmax, will only share a detection conductor 7 with one other detection switching block 80.

The detection conductor 7 that is coupled through each of the multiplexors 91 is selected based on the selection signals - in3 and in4 for multiplexor 91-1 and 25 in3_shifted and in4_shifted for multiplexor 91-2. In this embodiment, the control of the connection through each multiplexor 91 is defined by the following truth table:

in3/in3_shifted in4/in4_shifted

Selected i/p

0

0

1

0

1

2

1

0

3

1

1

4

-36-

Figure 11 also shows that the detection switching blocks 80 are connected to the detection conductor 7 via suitable resistors 93-0 to 93-7 and capacitors 95-0 to 95-7. The capacitors 95 couple the detection conductor 7 directly to the mid-rail voltage level used in the measurement channels 25, which effectively grounds the detection 5 conductors 7 (as far as the measurement channels 25 are concerned) when they are not selected by the detection switching block 80. This helps to reduce measurement cross talk - when AC signals from an unselected detection conductor 7 capacitively couples into a selected detection conductor 7. The resistors 93 also connect the detection conductors 7 to the mid-rail voltage level to avoid electrostatic charge build 10 up on the grid 3.

The outputs from the two multiplexors 91, labelled A and B in Figure 11, are input to a respective trans-impedance amplifier 97-1 and 97-2. Amplifier 97-1 acts to convert the AC measurement current from output A into a corresponding analogue AC 15 voltage. Similarly, the amplifier 97-2 acts to convert the AC measurement current from output B into a corresponding analogue AC voltage. The voltage output by amplifier 97-1 is applied to terminals 1 and 4 of a demodulating switch 99 and the voltage output by amplifier 97-2 is applied to terminals 2 and 3 of the demodulating switch 99. The demodulating switch 99 acts to multiply a demod signal with each of the voltages 20 from amplifiers 97-1 and 97-2. As shown in Figure 11, the demod signal is obtained by combining (in this example using an exclusive OR (XOR) gate 100) the polarity control signal and the ex_clock_shifted control signal. Thus, the ex_clock_shifted signal acts to effectively demodulate the incoming signal to a "baseband" signal that depends on the mutual capacitance between the selected excitation conductor 5 and 25 the selected detection conductor 7; and the polarity control signal modulates this "baseband" signal up to a frequency corresponding to that of the polarity control signal. When the demod signal has a value of one, the output voltage from amplifier 97-1 passes through switch terminal 1 to the A* input of the amplification and filtering circuit 83; and the voltage output from amplifier 97-2 passes through switch terminal 3 30 to the B input of the amplification and filtering circuit 83. When the demod signal is zero the switch 99 changes position such that the output voltage from amplifier 97-1 passes through switch terminal 4 to the B* input of the amplification and filtering circuit 83; and the voltage output from amplifier 97-2 passes through switch terminal 2 to the

-37-

A* input of the amplification and filtering circuit 83. As will be explained in more detail below, the amplification and filtering circuit 83 amplifies the difference between A* and B*. Thus, the demodulating switch 99 and the amplification and filtering circuit 83 act to demodulate and amplify A-B or B-A, depending on the value (1 or 0) of the polarity 5 control signal. Hence positive and negative measurements can be obtained from each detection conductor.

Timing Diagrams

Figure 12 is a timing diagram illustrating the timings of the control signals used in 10 Figure 11 and showing which of the detection conductors 7 are selected through the switching block 80. Figure 12 also shows the enable1_0 signal shown in Figure 8. As shown, at the start of a measurement cycle (represented by the dashed line 101) the multiplexor selection signals in3, in4, in3_shifted and in4_shifted all have the value zero. Therefore, during a first detection interval labelled Ati_d (which, in this 15 embodiment, corresponds in duration to the above described excitation cycle, T_ec) detection conductor Ym will be connected through multiplexor 91-1 to output A and detection conductor Ym+i will be connected through multiplexor 91-2 to output B. In the next detection interval (labelled At2_d) the value of the multiplexor switching signal in4 changes to the value 1 and accordingly, multiplexor 91-1 connects detection 20 conductor Ym+2 to the output A. In the next detection interval (labelled At3_d) the value of the multiplexor select signal in4_shifted changes to 1 and as a result the multiplexor 91-2 connects detection conductor Ym+3 to the output B. This process continues until the end of a detection cycle when each of the detection conductors 7 has been selected by the multiplexors 91.

25

As shown in Figure 12, the connection of the adjacent detection conductors 7 through the detection switching blocks 80 is staggered and such that during each detection interval, the signals from two adjacent detection conductors 7 are passed through to the outputs A and B of the two multiplexors 91 of each detection switching block 80. 30 This allows differential measurements to be obtained from the signals from adjacent detection conductors. As shown in Figure 12, seven detection intervals are required in this embodiment to switch the signals from the eight detection conductors through the detection switching block 80. Only seven detection intervals are required because

-38-

there is no need to obtain differential measurements of the signals from detection conductors Ym and Ym+7 as detection conductors Ym and Ym+7 are separated too far apart along the grid 3 to provide useful position information.

5 Once all the detection conductors 7 that are connected to a detection switching block 80 have been switched through to the corresponding amplification and filtering circuit 83, the cyclic processing begins again. The period of this detection cycle is shown in Figure 12 and labelled T_dc and, in this embodiment, this period corresponds to the above described measurement cycle. As shown in Figure 12, at the end of the 10 detection cycle, the excitation and control signal logic 11 raises the frame reference signal 22 to signal to the measurement processing unit 19 that measurement data for the detection cycle that as just been completed will have been stored in memory 17 and is ready for processing.

15 Amplification and filtering circuit

Figure 13 is a circuit diagram illustrating the main components of the amplification and filtering circuits 83 that are used in this embodiment to amplify and filter the signals output from the associated detection switching block 80. As shown, the two inputs A* and B* are input to the positive and negative inputs of a differential amplifier 115 20 having a generic gain of R2/R1. In a traditional differential amplifier the top R2 resistor is connected directly to the output of the amplifier. In this embodiment, however, the top resistor R2 is connected to the output of an amplifier 117 that buffers a voltage that is voltage divided by the resistors R3 and R4 from the output of the differential amplifier 115. This arrangement allows a higher than normal gain for the 25 first stage of the differential amplifier 115 given by:

GAIN = R2/R1 *(R3+R4)/R3

The two capacitors 119-1 and 119-2 introduced in the R3:R4 divider modify the gain of 30 the differential amplifier 115 to its generic value of R2/R1 at high and low frequencies, thus allowing to achieve the higher gain only for the signals having frequencies falling within the pass band of interest.

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The capacitors C connected at the node between resistors R1 and R2 at the input side of the differential amplifier 115 are used to achieve initial filtering of high frequency components in the signals obtained from the detection switching block 80. However, the corner frequency of this filter should be set to a higher value (than the 5 overall corner frequency of the amplification and filtering circuit 83) in order to maintain high rejection of common node signals in the main pass band. The main filtering of the high frequency signals is achieved with the third amplifier 121 which is configured as a second-order multiple feedback (MFB) low pass filter. The capacitor 123 and the resistor 125 provide a high pass filter in order to filter out low frequency 10 noise and eliminate any DC offsets of the amplifiers at the output of the application and filtering circuit 83.

Frequency Spectrum and Filter Response

Figure 14a illustrates the spectrum of the signals output by the detection switching 15 blocks 80. Most of the desired signal components are around the frequency corresponding to the polarity control signal. The higher frequency components correspond to the high frequency demodulation harmonics generated by the demodulating switch 99.

20 Figure 14b illustrates the desired frequency response of the amplification and filtering circuit 83 shown in Figure 13 to filter the signals obtained from the detection switching block 80. As shown, the high corner frequency of the filtering circuit 83 can be kept quite close to the frequency of the polarity signal. In this embodiment, the high corner frequency has been set at 1.5 times the frequency of the polarity signal. This allows 25 the amplification and filtering circuit 83 to filter out almost all the high frequency harmonics generated by the demodulator switch 99. The low corner frequency of the filtering circuit 83 cannot be set very close to the frequency of the polarity signal. This is evident from the spectrum of the input signal shown in Figure 14a, which contains quite a long tail at the low frequency end; and filtering out this part of the spectrum will 30 alter substantially the measured signal output. In this embodiment, the low corner frequency of the amplification and filtering circuit 83 has been set at 100 times lower than the high corner frequency. This still allows the amplification and filtering circuit 83 to filter out most of the unwanted low frequency noise caused by the measurement

-40 -

circuitry 25 (and the display screen electronics) and allows for a well defined gain for the measured signals within the pass band of the filtering circuit 83.

Timing Diagrams

5 Figures 15 and 16 are timing diagrams which illustrate the timing of various control signals used in this embodiment and showing the way in which the output from one of the amplification and filtering circuits 83 (AF_out) varies during each excitation interval. Figure 15 shows the situation when there is no finger (or stylus) in the vicinity of the crossover point between the selected detection conductors 7 and the selected 10 excitation conductors. As shown, the output from the amplification and filtering circuit 83 varies slightly about the mid rail voltage level. Figure 16 shows the situation when there is a finger (or stylus) in the vicinity of the crossover point between the selected detection conductors 7 and the selected excitation conductors. As shown in Figure 16, the output from the amplification and filtering circuit 83 builds up in amplitude from 15 excitation interval Atn_e until it reaches a peak negative value at the end of excitation interval Atn+2_e. The output signal then inverts in polarity as the scanning of the excitation signal across the gird of excitation conductors 5 passes the user's fingers or the stylus, and the amplitude then decreases over subsequent excitation intervals as the scanning of the excitation signal to the excitation conductors 5 moves away from 20 the user's finger (or stylus). Therefore, the measurement processing unit 19 can process the amplitudes of the signals output by the amplification filtering circuits 83 to identify the locations of users' fingers or other objects that affect the mutual capacitance between the excitation and detection conductors.

25 Sample and Hold Circuitry

Figure 17a is a circuit diagram illustrating the main components of the sample and hold circuitry 15 used in this embodiment. In the exemplary size of screen mentioned above, having a diagonal of about 203cm and having 169 detection conductors 7 that are multiplexed through twenty four detection switching blocks, there will of course, be 30 twenty four amplification and filtering circuits 83 that will feed their outputs to the sample and hold circuitry 15. However, for ease of illustration and explanation, the sample and hold circuitry 15 illustrated in Figure 17a receives inputs from four amplification and filtering circuits 83-0 to 83-3. As shown, the outputs from the

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amplification and filtering circuits 83 are input to a respective switch 151-0 to 151-3. Each switch 151 has two output terminals (labelled 1 and 2). The position of each switch 151 is controlled by a sample switch control signal that is generated by the excitation and control signal logic 11. The sample switch control signal is shown in 5 the timing diagram of Figure 17b. As shown, it has the same frequency as, although phase shifted from, the polarity modulation signal (polarity). When the sample switch signal is at a high value, each of the switches 151 connects its input to the output terminal labelled 1. This means that the signals output by the amplification and filtering circuits 83 are applied to the capacitors labelled C1. As a result, charge accumulates 10 on the C1 capacitors until the sample switch signal goes low. At this point, the switches 151 switch the signals received from the amplification and filtering circuits 83 to their output terminal 2 so that the signals then start to charge up the capacitors labelled C2. As can be seen from Figure 17b, the time that the sample switch signal is at a high level or a low level corresponds to one excitation interval (Atn_e).

15

As shown in Figure 17a, each of the C1 capacitors is connected to a respective input of a first multiplexor 155-1 and each of the C2 capacitors is connected to a respective input of a second multiplexor 155-2. The multiplexor 151-1 is enabled by the sample switch signal and the multiplexor 155-2 is enabled by the inverse of the sample switch 20 signal. The multiplexors 155 are enabled when its enable signal is at a low value. Therefore, when the output from the amplification and filtering circuits 83 are being charged onto the C1 capacitors, the multiplexor 155-1 connected to the C1 capacitors is open circuit and thus will not affect the charging of the C1 capacitors. Similarly, when the signals from the amplification and filtering circuits 83 are being charged onto 25 the C2 capacitors, the multiplexor 155-2 connected to the C2 capacitors is open circuit.

As shown in Figure 17a, the outputs from the two multiplexors 155 are input to the switch 157 which switches between the outputs from the two multiplexors. As shown 30 in Figure 17a, the switch 157 is also controlled by the sample switch signal and when the sample switch signal is high, the switch 157 connects the output from multiplexor 155-2 through to the input of the analogue to digital converter 13. When the sample switch signal is at a low value, the switch 157 connects the output from multiplexor

-42 -

155-1 through to the input of the analogue to digital converter 13.

Figures 17a and 17b also show the multiplexor control signals (in5 and in6) used to select which input of the multiplexors 155 is passed through to the output of the 5 multiplexor 155. As shown, the following table shows the relationship between the values of these control signals to the selected multiplexor input.

In5/in5_shifted in6/in6_shifted

Selected i/p

0

0

1

0

1

2

1

0

3

1

1

4

The operation of the sample and hold circuitry 15 shown in the Figure 17a will now be 10 explained with reference to Figure 17b. During a first excitation interval (Atn+1_e) the excitation signals are applied to excitation conductors Xn-1 and Xn. During this excitation interval, the outputs from the amplification and filtering circuits 83 are stored onto the C1 capacitors. At the end of this excitation interval (defined by the falling edge of the polarity signal) the sample switch signal also changes (after a short 15 delay). This causes the switches 151 to switch the output from the amplification and filtering circuits 83 to start to charge up the C2 capacitors. Whilst the C2 capacitors are being charged during the next excitation interval (Atn+2_e) the voltages stored on the C1 capacitors are sequentially passed through multiplexor 155-1 to the ADC 13 for conversion into corresponding digital values. Therefore, as shown in Figure 17b, 20 during the second excitation interval (Atn+2_e) measurements are made for the signals obtained when excitation conductors Xn.-i and Xn were energised during excitation interval Atn+1_e. In the third excitation interval (Atn+3_e), the switches 151 switch again so that the C1 capacitors are charged again and the voltages on the C2 capacitors are sequentially output through multiplexor 155-2 and switch 157 to the 25 ADC 13. In this way, the signals obtained from the different measurement channels at the end of each excitation interval can be converted by the ADC 13 whilst in parallel the signals for the next excitation interval are collected.

-43 -

Figure 17b also shows the ADC trigger signal used to trigger the analogue to digital converter 13 to convert the output from the sample and hold circuitry 15 into a corresponding digital value. As shown, in this illustration as there are four amplification and filtering circuits 83 connected to the sample and hold circuitry 15, the 5 ADC trigger signal has four pulses spaced during the relevant measurement interval so that the signal from each amplification and filtering circuit 83 will be sampled in turn.

Excitation and Control Signal Logic 10 As mentioned above, the excitation and control signal logic 11 operates independently of the measurement processing unit 19 and operates cyclically in a free running manner to produce the same control signals - measurement cycle after measurement cycle. Figure 18 is a block diagram that illustrates the main components of the excitation and control signal logic 11 used in this embodiment. As shown, the 15 excitation and control signal logic 11 includes nineteen free running timers that are each clocked by a master clock signal and that each output one of the above described control signals. Some of the timers are just counters that output a suitably frequency reduced version of the master clock frequency, whereas other timers output a Pulse Width Modulated (PWM) signal (in particular the timers used to generate the 20 enable signals and the multiplexor select signals used in the detection switching blocks).

Measurement Processing Unit

Figure 19 is a flow chart illustrating the way in which the measurement processing unit 25 19 operates to process the measurement data stored in memory 17. This process is typically software controlled. As shown, in step s1, the measurement processing unit 19 waits to receive the next frame reference signal 22 from the excitation and control signal logic 11. When the frame reference signal 22 is received, the processing proceeds to step s3, where the measurement processing unit 19 reads the new ADC 30 data from memory 17. This data will include a measurement for each cross-over point between the excitation conductors 5 and the detection conductors 7. In step s5, the measurement processing unit 19 subtracts a background value from each of these measurements. The measurement processing unit 19 maintains a respective

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background value for each cross-over point. After the background values have been subtracted from the measurements; the measurement processing unit 19 processes the adjusted measurements to determine if there are any areas of the digitiser 1 that have been touched, for example, by a user's fingers (or a stylus). If no areas have 5 been touched then the processing proceeds to step s9, where the measurement processing unit 19 updates the background value for each cross-over point. In this way, changes in the measurements obtained because of slowly varying changes of the circuit components overtime will be removed by the measurement processing unit 19.

10

If at step S7, the measurement processing unit 19 determines that there are areas of the digitiser 1 that have been touched, then the processing proceeds to step s11 where the measurement processing unit 19 determines if a current touched area relates to a touch by a small separate object (such as a finger or a stylus) or a touch 15 by a large object (such as the palm of a user's hand or closely located multiple fingers). The measurement processing unit 19 then calculates position data for a small separate object in step s13 or calculates position data for a large object in step s15 depending on the determination made at step s11. Areas of touch by small objects will be characterised by signals similar to those illustrated in Figure 16. Large 20 objects, like a palm or multiple fingers, will produce larger signal levels in a much larger array of adjacent measurement nodes (cross-over points). Typically, the signals from large objects can be processed using an algorithm that aims for more crude position information compared with the algorithms used for determining the position of smaller separate objects, which typically should be positioned with 1mm 25 accuracy. The algorithms used for such position calculations from the measurement data stored in memory 17 will be familiar to those skilled in the art and will not be described in further detail here. Distinguishing between small and large objects allows the digitiser 1 to report the different types of touches that have been detected which therefore allows a host processor (not shown) to take different control actions 30 depending on whether or not the detected object is a small separate object or a large object. For example, if the host processor is running a drawing program, then detection of the large object can be used as an "eraser" function in the drawing program. In this way, the user experience of the electronic digitiser can be made

-45-

similar to the normal use of a conventional "white board".

Once the position data for the current touched area has been calculated, the processing proceeds to step s17, where the measurement processing unit 19 5 determines if there are any additional areas of the digitiser 1 that have been touched. If there are, then the processing returns to step s11 as before. Once position data has been obtained for each of the touched areas, the processing proceeds to step s9 where the measurement processing unit 19 updates the background values associated with the areas that have not been touched. The processing then proceeds

10 to step s19 where the measurement processing unit 19 reports the position data to the host processor (not shown) via the host interface unit 21. The processing then returns to step s1 where the measurement processing unit 19 awaits the next frame reference signal 22 indicating that the next set of measurements have been stored in the memory 17 and are ready to be processed.

15

Advantages of Embodiment

1) The excitation and control logic 11 operates autonomously with respect to the measurement processing unit 19; and in a "free running" manner. Thus the excitation and control logic can be configured with simple clock circuits that can

20 generate the required control signals in the required cyclic manner, without software processor control.

2) Adjacent excitation conductors are energised in an overlapping manner so that during each excitation interval two adjacent excitation conductors are driven with complementary (180° phase shifted) excitation signals, allowing for a

25 reduction in electromagnetic emissions by the digitiser grid 3 that might cause interference to other nearby electronic circuits.

3) Detection conductors are sequentially switched through the measurement channels such that during the detection intervals, the signals from two detection conductors are passed through each detection switching block, from

30 which differential measurements can be obtained - allowing for a reduction in noise picked up from the LCD screen or another external noise source.

4) Each excitation conductor is energised during one period of the polarity signal, which cancels low frequency components in the signals measured with the

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amplification and filtering circuits. This also allows measurements to be obtained from each detection conductor for both polarities and together with the overlapping selection of the excitation conductors allows for optimum measurement update rates.

5 5) The excitation electronics are arranged so that at the end of one detection interval (excitation cycle) and at the start of the next detection interval, there are no overlapping excitation signals - as this helps to reduce the bandwidth requirements of the amplification and filtering circuit(s) used to amplify and filter the signals obtained from the detection conductors, which in turn reduces the 10 noise contained in the final measurements.

Excitation Frequency

A description will now be given of the operation of the above embodiment for a specific implementation of the amplification and filtering circuit 83 (shown in Figure 20) 15 that has a pass band between 2kHz and 200kHz, for different excitation frequencies. Figures 21 and 22 illustrate the case where the frequency of the excitation signal is the same as the frequency of the polarity control signal (i.e. 135kHz); Figures 23 and 24 illustrate the operation when the frequency of the excitation signal is twice the frequency of the polarity control signal (i.e. 270kHz); Figures 26 and 27 illustrate the 20 case where the excitation frequency is three times the frequency of the polarity control signal (i.e. 405kHz); and Figures 28 and 29 illustrate the situation where the excitation frequency is four times the frequency of the polarity control signal (i.e. 540kHz).

Figure 21 illustrates the way in which the excitation signals are applied sequentially to 25 the adjacent excitation conductors X0, X1, X2, etc. As shown, at the end of each excitation interval (Ati_e). The excitation signal applied to one excitation conductor transitions from a one to a zero and the excitation signal applied to an adjacent excitation conductor transitions from a zero to a one. In this way, complimentary excitation signals are still being applied to adjacent excitation conductors. This is true 30 for all excitation intervals except for the transitions at the start and end of the last excitation interval (Atk_e) of a given excitation cycle. As discussed above, this is because there is no excitation conductor Xmax connected to the last excitation switching block 50-Mmax.

-47-

Figure 22 illustrates the voltages V1 to V4 generated in the amplification and filtering circuit 83 shown in Figure 20 (with voltages V1 and V2 multiplied by 240 and with voltage V3 multiplied by 2.5 - for ease of visualising the signals). As shown in Figure 5 20, the voltage V1 corresponds to the A* input to the amplification and filtering circuit 83 and the voltage V2 corresponds to the B* input to the amplification and filtering circuit 83. In this embodiment, because the excitation frequency is the same as the frequency of the polarity control signal, the output from the XOR gate 100 shown in Figure 11 will be a constant and therefore switch 99 will not change position (i.e. there 10 is no demodulation in this example). For the purposes of the following discussion, it will be assumed that the switch 99 is set in the position shown in Figure 11 such that the output from amplifier 97-1 will be passed to the A* input of the amplification and filtering circuit 83 and so that the output from amplifier 97-2 is passed through to the B* input of the amplification filtering circuit 83. Further, to simplify the discussion of 15 later examples, (where the excitation frequency is greater than the frequency of the polarity control signal) it will be assumed that there is no signal coming from amplifier 97-2.

As shown in Figure 22, for the case where the excitation frequency is the same as the 20 frequency of the polarity signal (=135kHz), the input signal V1 appearing at the A* input of the amplification and filtering circuit 83 will rise to a peak positive value with the rising edge of the clock signal (excitation signal) and will then decay until the falling edge of the clock signal at which point it will go to a peak negative voltage and then decay over time. This V1 voltage is amplified and filtered by the first stage of the 25 amplification circuitry to generate the voltage V3. This V3 voltage is then amplified and filtered again through the remaining amplification and filtering circuit to generate the output voltage V4 that is a smoother sinusoidal voltage at the frequency of the polarity control signal (135kHz). Figure 22 also shows the sample switch signal used to control the sampling of the signals by the sample and hold circuitry 15. As shown, 30 the sample switch signal is phase shifted from the polarity and the excitation signals so that the voltage V4 is sampled closer to its peak values during the corresponding excitation intervals.

-48 -

As those skilled in the art will appreciate, because there is no demodulation being performed in this example, the rejection of external noise is not optimum as all noise signals within the range 2kHz to 200kHz will pass through the amplification and filtering circuit 83. This can be disadvantageous especially when the digitiser 1 is for 5 use with an LCD display where it is not uncommon to have LCD switching noise at approximately 30kHz and power supply switching noise at approximately 100kHz.

Figures 23 and 24 illustrate the signals obtained when the excitation frequency is twice the frequency of the polarity control signal. As can be seen from Figure 23, in 10 order to maximise the number of opposite polarity transitions of the excitation signals in adjacent excitation conductors, the odd numbered conductors have been held at Vcc when not selected for excitation. Therefore, when the excitation signal that is applied to excitation conductor X0 transitions from zero to one at the end of excitation interval Ati_e the excitation signal applied to the adjacent excitation conductor X1 15 transitions from a one to a zero. If excitation conductor X1 had not been held at Vcc, then the only opposing transition would occur in the middle of the excitation interval At2_e.

Figure 24 illustrates the voltages V1, V2, V3 and V4 for this case where the excitation 20 frequency is twice that of the polarity control signal. The dashed vertical lines shown in Figure 24 correspond to the transitions of the excitation signal. As shown, when the excitation signal (ex_clock) transitions from a low level to a high level, the voltage V1 increases in amplitude and then decays during the first half of the clock period. However, on the falling edge of the ex_clock_shifted signal that is used to generate 25 the demod control signal for the demodulating switch 99, the voltage output from amplifier 97-1 is switched onto the B* input to the amplification and filtering circuit 83 and therefore appears at V2. Subsequently, when the excitation signal transitions from a high level to a low level, a negative voltage will appear at V2 that will decay over time. When the ex_clock_shifted signal changes from a low level to a high level, 30 the demod signal used to control the position of the demodulating switch 99 will remain the same because at this time instant the polarity signal also changes from a high level to a low level. Therefore, on the rising edge of the excitation signal, a positive peak appears at V2 which decays over time until the falling edge of the

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ex_clock_shifted signal. At this time, the position of the demodulating switch 99 changes again such that the voltage output from the amplifier 97-1 is passed through the A* input to the amplification and filtering circuit 83 and thus appears at V1.

5 Figure 24 also shows the filtered signal V3 obtained by amplifying and filtering the difference between V1 and V2; and V4 shows the further amplified and filtered signal at the output of the amplification and filtering circuit 83. As shown in Figure 24, the output signal V4 is still a substantially sinusoidal signal at a frequency corresponding to the polarity control signal. Figure 24 also shows the sample switch control signal 10 used to control the sampling of the signal output from the amplification and filtering circuit 83. As shown, the sample switch signal is shifted relative to the polarity signal so that the output V4 is sampled close to its peak value.

As mentioned above, in this example, where the frequency of the excitation signal is 15 twice that of the polarity control signal, the odd numbered excitation conductors are held at Vcc when the excitation signal is not being applied to them. Figure 25 illustrates a modified version of Figure 5 showing one way in which this can be achieved.

20 Because of the demodulation used in this embodiment, the frequencies that will pass through the amplification and filtering circuit 83 include those between 70kHz and 470kHz (+-200kHz around 270kHz). Therefore, noise at a frequency of 100kHz will still pass through the amplification and filtering circuit 83.

25 Figures 26 and 27 illustrate the operation when the excitation frequency is three times the frequency of the polarity control signal. As shown in Figure 26, in this case, there is no need to hold the odd numbered excitation conductors at Vcc. This is true in all cases where there is an even number of transitions in the excitation signal during each excitation interval (Ati_e). Therefore, with this excitation frequency, there is no 30 need to change the biasing scheme and the circuitry shown in Figure 5 can be used.

With this excitation frequency, the frequencies that will pass through the amplification and filtering circuit 83 include those between 205kHz and 605kHz (+-200kHz around

-50-

405kHz). Therefore, with this excitation frequency the 100kHz interfering signal will be filtered to a certain extent by the amplification and filtering circuit 83.

Figure 28 and 29 illustrate the operation when the excitation frequency is four times 5 the frequency of the polarity control signal. In this case, as shown in Figure 28, the odd numbered excitation conductors 5 should (preferably) be held at Vcc to maximise the number of opposing transitions of the excitation signal on adjacent excitation conductors.

10 In this case, the pass band of the amplification and filtering circuit 83 corresponds to 340kHz to 740kHz (+-200kHz around 540kHz). In this case, sources of external noise at about 100kHz will be efficiently filtered out by the amplification and filtering circuit 83.

15 The frequency of the excitation signal may be any integer multiple of the frequency of the polarity control signal. The integer chosen depends on the particular application and the noise sources that may be present. The inventor has found that an optimum ratio for the multiplexing strategy used in this embodiment is where the excitation frequency is about seven times the frequency of the polarity control signal. This gives 20 an excitation frequency of 945kHz for the case where the polarity signal has a frequency of 135kHz. When the excitation and detection conductors are formed from copper (or other low resistance material) operation of the digitiser at 945kHz is practical even for digitisers designed for use with large diagonal screens (having for example a diagonal of 203cm (80inches) or more). However, with ITO based 25 digitisers 1, such high excitation frequencies can only be used in digitisers designed for use with much smaller display screens. In particular, with an ITO based digitiser, the excitation frequency should be restricted to about 70kHz for screens having a diagonal of about 75cm (30inches) to keep the amount of cross talk noise below 10%. As the size of the display screen is increased, the excitation frequency for such ITO 30 based digitisers has to decrease further. However, reducing the excitation frequency also has the effect of reducing the amplitude of the signals that are being measured. This can be seen by comparing the amplitudes of the V4 signal shown in Figures 22, 24, 27 and 29. As shown, as the excitation frequency increases (relative to the

-51 -

frequency of the polarity control signal), the amplitude of the V4 signal increases. As those skilled in the art will appreciate, this is because the measured signal caused by the mutual capacitive depends linearly on the excitation frequency. Of course, whilst it is possible to reduce the frequency of the polarity control signal (in order to reduce the 5 bandwidth of the filtering circuit which will also reduce the noise), doing so reduces the rate at which the new measurements can be obtained. As discussed above, the measurement update rate must be sufficient to allow the tracking of objects over the digitiser 1 and therefore, the frequency of the polarity control should be kept as high as possible - especially for large sized digitisers 1.

10

Alternative Embodiments and Modifications

A detailed description has been given above of a digitiser 1 that can be implemented over a wide range of sizes and that can be used with or without an associated display screen. A number of modifications to the above described digitiser will now be 15 described.

In the above embodiment, a polarity control signal was applied to (multiplied with) the signal obtained from each selected detection conductor. This polarity control signal was applied by the demodulating switch 99. In an alternative embodiment, the polarity 20 control signal may be applied to the excitation signal before it is applied to each excitation conductor 5. Figure 30 illustrates one way in which this may be achieved. As shown in Figure 30, the positive excitation signal (ex+) is formed by taking the exclusive-or (XOR) of the polarity control signal and the ex_clock signal. Similarly, the negative excitation signal (ex-) is obtained by taking the exclusive-or of the inverted 25 polarity signal and ex_clock.

Figure 31 illustrates the form of the excitation signals applied to the selected excitation conductors. Like in the first embodiment described above, the excitation signal is applied to each excitation conductor in turn and in an overlapping manner. Also, like 30 in the first embodiment described above, the excitation signal applied to each excitation conductor is applied for two consecutive excitation intervals (Ati_e and Ati+i_e). Further, the polarity of the excitation signal applied to each excitation conductor is inverted between the two excitation intervals. This inversion of the

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excitation signal is caused by the use of the polarity control signal in the excitation circuitry.

Figure 31 illustrates the case where there are 16 excitation periods per period of the 5 polarity control signal. However, due to the polarity control signal being applied on the excitation side, one excitation pulse is lost and so only 15 pulses are applied to each excitation conductor. Therefore, in this sense, applying the polarity control signal on the excitation side is less efficient than applying it on the detection side. Figure 32 illustrates the case where there are 17 periods per polarity period, but due to the 10 polarity signal, one excitation pulse is lost and so only 16 pulses are actually applied. As shown in Figure 31, as there are an odd number of transitions in the excitation signal applied during each excitation interval, there is no benefit in holding any of the excitation conductors to Vcc when they are not being energised. On the other hand, in Figure 32 there is an even number of transitions in the excitation signal applied 15 during each excitation interval and therefore, in order to maximise the number of opposing pulses applied to adjacent excitation conductors, each of the odd numbered excitation conductors is held at Vcc when not being energised.

Figure 33 illustrates the detection switching block 80 used in this alternative 20 embodiment. As shown in Figure 33, there is no polarity control signal that is combined with the ex_clock_shifted signal. Instead, as shown in Figure 34, the demod signal corresponds to the ex_clock_shifted signal of the first embodiment. As can be seen from Figures 34 and 35, the output from the amplification and filtering circuit 83 is the same as in the first embodiment for a case where there is a user's 25 finger and where there is no finger present adjacent the conductors being interrogated. Therefore, the polarity control signal can be applied either on the detection side or on the excitation side of the circuitry, without materially affecting the operation of the embodiment.

30 In the above embodiment, the outputs from four amplification and filtering circuits were passed through a sample and hold circuit 15. As shown in Figure 18, the ADC_trigger signal causes the ADC to sample the output from the sample and hold circuitry 15 at regularly spaced intervals during the excitation intervals. Figures 36 and 37 illustrate

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an alternative embodiment where there are fewer amplification and filtering circuits and where the ADC_trigger signal causes the ADC 13 to convert the output from the sample hold circuitry 15 at the beginning of each excitation interval. As shown in Figure 36, in this alternative embodiment, the C1 and C2 capacitors are connected to 5 different inputs of a 4-input 1-output multiplexor 155. As shown in Figure 36, the ADC_trigger signal is generated by the trigger_clock signal that is selectively switched via the switch 156; and the position of the switch 156 is controlled by the in7 control signal.

10 In the first embodiment the last excitation switching block 50-Mmax had one output that was not connected to an excitation conductor. As explained above, this reduces the width of the pass band required for the amplification and filtering circuit 83. The reason for this will now be explained with reference to Figures 38 to 40. In particular, Figure 38 illustrates an alternative embodiment where the missing excitation 15 conductor Xmax is included and connected to the last excitation switching block 50-Mmax. As shown in Figure 38, in this embodiment, the polarity control signal is applied on the excitation side of the digitiser electronics rather than on the detection side as per the first embodiment. However, as explained above, where the polarity control signal is applied does not affect the operation of the embodiment.

20

As can be seen from Figure 39, during the last and first excitation intervals (Atk_e and Ati_e) of an excitation cycle, the excitation signal is applied to the conductor Xmax (whereas in the first embodiment there was no Xmax conductor to be energised). Therefore, whilst this embodiment offers the advantage that during each excitation 25 interval (Ati_e) there are two conductors that are energised with excitation signals of opposite polarity, during the first excitation interval (Ati_e) of each excitation cycle conductors at opposite ends of the digitiser (conductors X0 and Xmax) are energised. As these conductors are not adjacent each other, the signals will not combine to reduce the electromagnetic emissions of the digitiser during this interval. Further, 30 since the positive and negative polarity of the excitation signal applied to excitation conductor Xmax (for the same configuration of detection conductors) are applied at the start and at the end of the excitation cycle, an additional frequency component is introduced to the signal output from the detection switching blocks 80 that

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corresponds to the frequency of the excitation cycle. This additional component 189 is illustrated in Figure 40a at a frequency corresponding to the frequency of the excitation cycle (1/T_ec). As a result of this additional frequency component 189, the amplification and filtering circuits 83 have to be designed with a wider pass band.

5 Figure 40b illustrates, with the solid line 191, the pass band that will allow this additional frequency component 189 to pass through the amplification and filtering circuits 83. Figure 40b also illustrates, by the dashed line 193, the bandwidth of the amplification and filtering circuits 83 used in the first embodiment. As can be seen from Figure 40b, the additional excitation conductor connected in the manner shown 10 in Figure 38 results in a significant increase in the bandwidth of the amplification and filtering circuits 83, which in turn increases the amount of noise that will pass through the amplification and filtering circuits and into the measurements that are obtained.

One way that can be used to avoid this additional frequency component is to keep the 15 excitation and polarity control signals at the same frequency but to half the frequency of the other control signals used for the excitation circuitry (such as the enable control signals and the multiplexor select control signals). As a result, each excitation conductor will receive twice the number of excitation pulses and during each excitation interval (Ati_e) each excitation conductor that is energised will be energised with both 20 positive and negative versions of the excitation signal. Figure 41 is a timing diagram illustrating the operation of such an embodiment. As shown in Figure 41, the enable control signals and the multiplexor select signals (in 1, in2, inl shifted and in2_shifted) have half the frequency than those used in the first embodiment. Therefore, during the first excitation interval (Ati_e) and during the last excitation interval (Atk_e) for the 25 same configuration of detection conductors, the signal applied to conductor Xmax has both positive and negative versions of the excitation clock signal. As a result, the frequency spectrum of the signals obtained in this embodiment correspond with those shown in Figure 14a and therefore, amplification and filtering circuits 83 having narrower pass bands can be used. However, as those skilled in the art will 30 appreciate, with this modification, the update rate of the system is reduced by two without any sizeable improvement in the signal to noise ratio. Figures 41 and 42 show that during each excitation interval (Ati_e) the system is now measuring an AC type of signal, with both a positive and negative voltage level per configuration of excitation

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and detection conductors. This is more clearly seen in Figure 42 - which shows the output from the amplification and filtering circuit 83 in the presence of a user's finger.

In the above embodiments, during each excitation cycle, the excitation signal is 5 scanned along the excitation conductors 5 from one side of the grid 3 to the other side. This is because the XO conductor is located at one side of the grid 3 and the Xmax (or Xmax-1) conductor is located at the opposite side of the grid 3. In an alternative embodiment, during each excitation cycle, the excitation signal may be scanned across the gird two or more times. Figure 43 illustrates an embodiment 10 where the excitation signal is scanned from right to left across the grid from conductor XO to conductor Xi and is then scanned from left to right from conductor Xi+1 to conductor Xmax. As shown in Figure 43, when scanning the excitation signal from excitation conductor XO to excitation Xi, the excitation signals are applied to every alternate excitation conductor and when scanning from left to right, the excitation 15 signal is applied to the excitation conductors that were not scanned in the first stage. With this arrangement, because the first and last excitation conductors that are energised during each excitation cycle are physically adjacent each other, the problem of extra electromagnetic interference emitted by the digitiser 1 can be reduced because the excitation signal applied to conductor Xmax will cancel, to a certain 20 extent, the excitation signal applied to conductor XO during the first excitation interval (Ati_e) of each excitation cycle. As those skilled in the art will appreciate, the same is true if the excitation signal is swept from one side of the digitiser to the other side any integer number of times per excitation cycle.

25 Although Figure 43 shows the excitation switching blocks 50 on each side of the excitation conductors 5, this is shown for ease of illustration. In a preferred embodiment, the excitation circuitry that is used to apply the excitation signals to the excitation conductors 5 is preferably provided on one side of the excitation conductors 5, like the arrangement shown in Figure 3.

30

In a similar manner, the processing of the signals from the detection conductors may also be scanned from one end of the array of detection conductors to the other and then back to the starting end. This is illustrated in Figure 44, where the detection

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conductors YO to Yk are scanned first followed by conductors Yk+1 to Ymax. This arrangement may be particularly useful when combined with the alternative illustrated in Figure 43 in order to simplify the post-processing of measured signals.

5 In the above embodiments, a pair of detection conductors 7 was selected by each detection switching block 80 and then the excitation signals were sequentially applied in the above described overlapping manner to the excitation conductors 5. Once all of the excitation conductors have been energised, the excitation cycle ends and the next pair of detection conductors for each detection switching block were then selected. In 10 an alternative embodiment, the excitation signals may be applied to a selected pair of excitation conductors and the pairs of detection conductors 7 may be sequentially switched through the detection switching blocks 80 before changing to the next pair of excitation conductors and cycling through the detection conductors 7 again. Timing diagrams illustrating the operation of such embodiment are shown in Figures 45 and 15 46. As before, the excitation interval is given by Ati_e. During each excitation interval, the excitation signals (ex+ and ex-) are applied to the same selected pair of excitation conductors (in this example conductors Xn and Xn+i). Each excitation interval is divided into a number of detection intervals (Atj_d) - in this case eight detection intervals, during each of which a different pair of detection conductors is selected by 20 each detection switching block 80. Once all of the pairs of detection conductors have been selected through the detection switching blocks 80, at the end of a detection cycle (T_dc), the configuration of the excitation conductors is changed (in this case so that the excitation signals are applied to excitation conductor Xn+i and excitation conductor Xn+2) and the cyclic selection of the detection conductors 7 begins again. 25 Figure 45 shows excitation performed with an excitation switching block shown in the Figure 25, which allows to pull excitation wires sequentially either to the ground or to the voltage rail in order to achieve the timing diagram of Figure 45. Figure 46 shows that once all the pairs of excitation conductors 5 have been selected for excitation, at the end of the excitation cycle (T_ec), the frame reference signal 22 is generated and 30 then the processing begins again.

Figure 47a illustrates a preferred form of the detection switching block 80 used in this embodiment. As can be seen from a comparison of Figure 46 with Figure 11, the

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structure of the detection switching block 80 is similar to the detection switching block structure used in the first embodiment except that input 3 (which was connected to conductor Ym+7 in Figure 11) is now held at the mid-rail voltage level. Further, each detection switching block 80 only has seven input conductors Ym to Ym+6, with 5 conductor Ym and conductor Ym+6 being shared with the adjacent detection switching blocks 80. Therefore, in this embodiment, twenty eight detection switching blocks 80 would be required to process the signals from one hundred sixty nine detection conductors 7.

10 Figure 47a also illustrates the possible modification to the analogue circuitry of the switching block 80. This modification can provide a much better rejection of external common mode noise source and allows to reduce the overall power consumption of the analogue circuitry due to the simplification of the amplification and filtering block 83 as discussed below. The new fully differential amplifier 97 is used to amplify the 15 differential current between the terminals A and B. The common mode current in terminals A and B is grounded via the set of capacitor 95 as the virtual resistance of the fully differential amplifier for the common mode current is infinitely high. The virtual input resistance to the differential current is quite low (the differential input voltage is almost zero for the amplifier with a high open loop gain) thus the differential current is 20 mainly flowing via the feedback resistors R with only small amount of current diverted to the ground via the set of capacitors 95. As a result of the differential current via the feedback resistors R the highly symmetrical differential voltage is created at the output of the amplifier. By using a fully differential amplifier with a relatively high gain bandwidth product it is possible to maintain very low virtual impedance at the input of 25 the fully differential amplifier for the differential current in spite of using relatively large nominal values for the feedback resistor R. The highly symmetrical voltage at the output of the fully differential amplifier 97 can be multiplexed via the multiplexor 99-1 using the same digital demod signal as before into the single ended analogue signal C which is provided as an input to the modified amplification and filtering circuitry 83-1. 30 The new amplification and filtering circuitry 83-1 is shown in the Figure 47b. The circuitry provides a band pass filter with amplification based on the simplified version of the third-order MFB low-pass filter coupled with the second-order high pass filter. The modified amplification and filtering circuitry requires only two amplifiers compared

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with a previous version which was based on three amplifiers.

Figure 48 illustrates the way in which the signals are switched through the switching blocks 80. As shown and as mentioned above, in this embodiment, each detection 5 cycle (T_dc) is split into eight detection intervals (Ati_d to At8_d). As shown in Figure 48, each of the detection conductors Ym to Ym+6 is connected through the detection switching block 80 for two consecutive detection intervals and in an overlapping manner. As can be seen from the top of Figure 48, one detection interval corresponds to half the period of the polarity control signal. As discussed above, the polarity 10 control signal is either used on the excitation side or on the detection side to invert the polarity of the received signal. Therefore, since each detection conductor 7 is switched through the detection switching block 80 for two consecutive detection intervals, a measurement can be obtained from each detection conductor for both polarities. It is desirable that the signals obtained from each detection conductor 7 15 include both polarities so that no low frequency components are introduced into the measured signals from each detection conductor 7.

In the first embodiment described above, it was possible to switch the signals from the detection conductors in just seven detection intervals (as shown in Figure 12); 20 because during each detection interval the excitation signals were being cycled through all of the excitation conductors with both polarities. Therefore, there is no low frequency component caused by only switching conductor Ym and conductor Ym+7 through the detection switching block 80 during one detection interval (Ati_d in the case of conductor Ym and At7_d in the case of conductor Ym+7). This is not the case in 25 this embodiment, and each detection conductor 7 should be connected through the detection switching block for two detection intervals with opposite polarities to avoid introducing low frequency components being introduced into the measurement signals.

30 Figure 48 also shows the output from the associated amplification and filtering circuit 83 when there is no finger or object adjacent the selected excitation and detection conductors; and Figure 49 shows a similar plot to that shown in Figure 48, except showing a typical response that will be obtained from the output of the amplification

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and filtering circuits 83 when there is a finger or other object adjacent currently selected excitation and detection conductors. As explained above, each detection switching block will switch seven detection conductors through the same filtering circuit. As these conductors are relatively closely spaced, it is likely that the presence 5 of a finger will affect the signals obtained from the conductors connected to the same detection switching block 80. In the example illustrated in Figure 49, the finger is likely to be centered over detection conductor Ym+3, corresponding to the peak signal that is generated and also corresponding to the conductor where the polarity of the output signal changes.

10

It is worth to mention that the average of all signals measured during the single detection cycle T_dc shown in the Figure 49 is equal to the value of the midrail voltage irrespective of the presence of the targets on a surface of the digitiser. This feature can be used to automatically trace the actual value of the midrail voltage during the 15 measurement cycle in order to remove the overall sensitivity to its perturbation and long term drift. As a result the measurement processing algorithm shown in Figure 19 will use the actual deviation of the measured signals from the exact instantaneous value of the midrail voltage obtained as an average value for all voltage values measured during one cycle of the detection T_dc.

20

The reason for holding the third input of multiplexor 91-2 at the mid-rail voltage level will now be explained. In particular, if this third input had been connected to the detection conductor Ym+7 (as per the first embodiment), then as indicated in Figure 50 it would be connected through the demodulation switching block 80 during detection 25 intervals Ati_d) and At8_d). As a result, an additional frequency component will be added into the measurements at a frequency corresponding to one over the period of the detection cycle (i.e. 1/T_dc). This additional frequency component 201 is illustrated in Figure 51a. This additional frequency component 201 is much closer in frequency to the frequency of the polarity control signal (compared to the additional 30 frequency component 189 shown in Figure 40a) because there are only four periods of the polarity control signal within each detection cycle. This in turn is because there are fewer detection conductors 7 and these are being multiplexed through parallel detection switching blocks 80. Therefore, as shown in Figure 51b, if all of the

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multiplexor inputs of the detection switching blocks 80 are connected to detection conductors, then the amplification and filtering circuits 83 will require a frequency response 203 that has a wider pass band than the filter response 193 required when one of the multiplexor inputs of the detection switching blocks 80 is held at the mid-rail 5 voltage level. Therefore, as those skilled in the art will appreciate, holding one of the inputs into the detection switching block to the mid-rail voltage level is analogous to the "missing" conductor of the last excitation switching block 50-Mmax of the first embodiment. The main difference is that in the first embodiment, only one output from the last excitation switching block 50-Mmax was not connected to an excitation 10 conductor. Whereas in this embodiment, one of the inputs to each of the detection switching blocks 80 should be connected to the mid-rail voltage if the additional frequency component 201 is to be avoided.

Of course, as the frequency of the additional frequency component 201 is relatively 15 close to the main peak of the desired signal at the frequency of the polarity signal, it may be preferable to connect the detection conductors through the detection switching blocks 80 in the manner shown in Figure 33 (if the polarity signal is being applied on the excitation side) or Figure 11 (if the polarity signal is being applied on the detection side); as such an arrangement will reduce the number of detection switching blocks 80 20 and amplification filtering circuits 83 required to connect to the same number of detection conductors 7. However, in such an embodiment, care has to be taken in the design of adjacent detection switching blocks 80 so that detection switching blocks 80 that are connected to the same detection conductor 7 do not switch the signal from that detection conductor 7 through both detection switching blocks 80 during the same 25 detection interval. For example, detection conductor Ym shown in Figure 33 is shared with the previous detection switching block 80-L-1 and if both detection switching blocks 80 are connected in the same way, then during the first detection interval (Ati_d) conductor Ym will be connected to the A output of multiplexor 91-1 in switching block 80-L and will be connected to the B output of multiplexor 91-2 in detection 30 switching block 80-L-1. As those skilled in the art will appreciate, such a dual connection through two detection switching blocks 80 will cause erroneous measurements to be obtained from conductor Ym. Consequentially, in such an embodiment, adjacent detection switching blocks 80 should be configured differently

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so that the same detection conductor is not switched through two switching blocks at the same time. Figure 52 is a block diagram illustrating the way in which this can be achieved for a preceding detection switching block 80-L-1 which connects to detection conductors Ym to Ym.7; and Figure 53 is a timing diagram illustrating the timing of when 5 the signals from the detection conductors Ym to Ym.7 are connected through the detection switching block 80-L-1 during one detection cycle. As shown in Figure 53, detection conductor Ym is now connected through detection switching block 80-L-1 during detection intervals Atj_d and At5_d and this does not conflict with the connection of conductor Ym through detection switching block 80-L (shown in Figure 10 33 or 11).

Figure 54 illustrates an alternative way to solve the problem of additional frequency components in the measurement signals and that allows all of the detection switching blocks 80 to have the same configuration. In this alternative, the frequency of the 15 multiplexor select signals (in3, in4, in3_shifted and in4_shifted) has been reduced compared to those shown in Figure 49. The frequency of these multiplexor select switches is such that during each detection interval (AtLd) the polarity control signal cycles through one period and therefore, the detection signals received during each detection interval will include both polarities and will not, therefore, include the above 20 described low frequency component that would be present if there is only one polarity. Therefore, in this embodiment, like in the first embodiment shown in Figure 12, it is possible to use the signal from conductors Ym and Ym+7 during a single detection interval without adding a low frequency offset; and consequently it is possible to cycle through the eight detection conductors Ym to Ym+7 in only seven detection intervals 25 (Ati_d to At7_d) as opposed to the eight detection intervals required in the embodiments illustrated with reference to Figures 49 and 50. With this arrangement, it is also possible to have the same configuration in adjacent detection switching blocks 80 as the adjacent switching blocks do not pass the signal from the shared detection conductor through the switching blocks during the same detection interval. 30 The downside with this embodiment is the same as the downside with the embodiment illustrated in Figures 41 and 42 - namely the update rate of the system is reduced without any notable improvement in the signal to noise ratio. In particular, as more clearly shown in Figure 55 (showing the outputs obtained in the presence of a

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user's finger), the output obtained from each detection conductor now forms a quasi AC signal and the detection circuitry will sample both a positive voltage level and a negative voltage level for each configuration of the excitation and detection conductors, when only one measurement is needed. This therefore halves the 5 measurement update rate that can be achieved in this embodiment.

In the above embodiments, positive and negative excitation signals were applied to adjacent (or neighbouring) excitation conductors on the digitiser grid 3. As those skilled in the art will appreciate, this is not essential and a single polarity of excitation 10 signal may be applied instead. The excitation circuitry used in such an embodiment is illustrated in Figure 56. In particular, Figure 56 shows a single excitation signal (ex+) that is selectively applied to the detection conductors via the multiplexor 65.

In the above embodiments, the measurement channels were arranged to obtain 15 measurements of the difference in signals obtained from adjacent (or neighbouring) detection conductors. As those skilled in the art will appreciate, this is not essential as the measurement electronics may measure the signal obtained from each detection conductor separately. Figure 57 is a block diagram of a detection switching block 80 that may be used in such an embodiment. As shown, in this alternative, the detection 20 switching block 80 includes one multiplexor 91 that selectively couples one of the four input detection conductors through to the trans-impedance amplifier 97 and the demodulating switch 99.

In the above embodiments, the digitiser 1 was arranged to detect objects that affect 25 the mutual capacitance between the selected excitation and detection conductors. In an alternative embodiment, the digitiser 1 may also be arranged to detect objects that inductively couple with the conductors in the digitiser. Such a dual capacitive and inductive digitiser embodiment preferably operates where the detection intervals are shorter than the excitation intervals - i.e. where the excitation signals are fixed and 30 the detection conductors are multiplexed through the detection switching blocks before the excitation conductors are changed and the multiplexing of the detection conductors starts again. This is because inductive based digitisers tend to require a relatively stable excitation signal to be applied to the excitation conductors in order to

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energise an inductive object in the vicinity of the digitiser. Additionally, in order to function in this dual capacitive and inductive mode of operation, the excitation conductors and detection conductors need to be able to be connected together to form conductor loops with which inductive signals can couple. Figure 58 illustrates 5 that this can be achieved by adding chains of multiplexors 211 and 213 to the excitation and detection conductors, that can selectively connect and disconnect selected excitation and detection conductors together to form the desired conductor loops. In operation, after (or before) the measurement channels have selectively scanned the detection conductors through the measurement channels for capacitive 10 sensing, the excitation and control signal logic 11 can configure the chain of multiplexors 211 and 213 to make the desired connections for inductive sensing. The way in which such a dual inductive and capacitive digitiser operates will be familiar to those skilled in the art and a further description will not be given here.

15 In the above embodiments, missing excitation conductors or non-connected inputs to the measurement channels were used to reduce the bandwidth requirements of the amplification and filtering circuitry. A similar effect can be achieved without these "missing connections" by controlling the multiplexors using more complex control signals - that achieves the same switching timings approach with reduced low 20 frequency harmonics in the received signals as illustrated in the Figures. However, such an embodiment is not preferred as it requires more complex excitation and control signal logic that uses more PWM signals, digital switches and logic gates to form the desired control signals.

25 Method of Manufacture of thin wire digitiser

It is well known in the prior art to manufacture digitisers using transparent ITO conductors. The typical resistivity of the ITO conductors is of the order of several hundred ohms per centimetre. This restricts the utility of ITO technology to small diagonal sizes only. For large diagonal size digitisers the resistance of ITO traces 30 becomes comparable to the mutual impedance caused by capacitive coupling between the adjacent lines even at very low measurement frequencies of a few tens of kHz.

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It is known in the prior art to make the conductors of X-Y digitisers using thin copper wires with a diameter of about 10 microns for designing digitisers with diagonal size above 30" and up to 100", although existing technical solutions are not yet appropriate for cheap mass production. Figure 59 shows a typical physical arrangement for the 5 sensing wires used in the currently available commercial digitisers based on using thin copper wires. The plurality of thin copper wires forming the X-Y grid are typically laminated between two thin sheets of plastic and can be further laminated to the glass screen or between two sheets of glass. The virtual flat cables 288 and 286 are arranged by routing thin wires to the same region of the plastic sheet where the 10 sensing wires are terminated at the flexible PCB. The flexible PCB flat cables 288 and 286 are in turn connected to the rigid PCB 290 with the measurement electronics via a standard ZIF connector 289 and 287. The cost of routing all thin copper wires in order to form the virtual flat cable 286 and 288 and an extra cost of terminating each individual wire at the rigid PCB 290 forms a major part of the cost of the total build. As 15 a compromise all available commercial providers are forced to use about 20 mm separation between adjacent wires for large diagonal digitisers - which reduces the number of required individual electrical terminations. Such a large separation between adjacent conductors in the X-Y grid restricts the achievable accuracy of the commercially available copper wire based digitisers to about 5 mm for measuring the 20 exact location of a finger or a conductive stylus. It is highly desirable to reduce the separation between adjacent wires in the X-Y grid to about five to six millimetres in order to provide an improved accuracy and thus an improved user experience, especially when using a conductive stylus for drawing applications. However a fourfold increase in the required wiring density cannot be achieved economically without the 25 development of radically new and cheaper methods for interconnecting the wire grid and the sensing electronics.

Another disadvantage of the common geometry of the sensing grid shown in Figure 59 is related to the increased length of wires, especially for wires which are close to 30 the corners of the screen. As discussed above, the mutual capacitance between the adjacent wires imposes a major limitation for the excitation frequency which can be used to measure signals from the X-Y digitiser. With thin copper wires this limitation becomes important with diagonal sizes above 40" and is indeed a major limiting factor

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with diagonal sizes of about 80". The inventor has realised, therefore, that it is highly desirable to use a concept of distributed electronics arranged around the periphery of the digitiser in order to shorten the active length of the individual wires in the X-Y array.

5

Additionally, the inventor has realised that one possible technology that could be used to make the large format digitisers described above may be taken from the automotive windscreen industry. In particular, an existing technology using thin metallic wires laminated in glass is known in the automotive industry for providing heated 10 windscreens. It has been developed during the last decade for heated automotive windscreens. In this technique specialised automated machinery lay thin (nearly invisible to the naked eye) tungsten wires 294 (see Figure 60) and heat them to attach onto the surface of an insulating PVB (Poly Vinyl Butyral) interlayer 292. PVB is a random copolymer of vinyl alcohol and vinyl butyral (VB) moieties synthesised by 15 reacting poly vinyl alcohol (PVA) with butyraldehyde in an acid medium. The typical thickness of the PVB foil interlayer used in the windscreen glass lamination is 0.030 in. (0.76 mm); a larger thickness of 0.060 in. (1.52 mm) is used for burglar resistance architectural glass. The PVB foil with a thickness of 0.015 in. (0.38mm) is used predominantly for less demanding safety glass applications. The minimum thickness 20 of the tungsten wires used for the heated glass is about 17 microns; the standard thickness is about 22 microns. The tungsten wires are typically coated in black to reduce their visibility in reflected light against a dark background. Straight sections of wire 294 might become highly visible due to the moire effect caused by the intersection of the straight wire with the nearly parallel features present in the field of 25 view of the driver (e.g fencing bars). This moire effect is substantially reduced by laying out the wire 294 in a wiggle pattern as shown in the Figure 60 with sinusoidal modulation with amplitude ranging from ±0.5mm up to ±1.5mm and a period of about 5mm. The set of wires 294 is closely wound with a distance of about 4 mm between adjacent arms of the wire. The wires are wound between two copper busbar 296 and 30 298 which are served as electrical terminals (see Figure 60). The standard copper busbar is made out of 50 or 75 |jm thick copper foil, with the most common width of 3, 5, 6 and 9 mm. The copper busbar has a conductive adhesive layer on the top surface which allows a good ohmic contact between the busbar and the heated

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tungsten wires 294 to be obtained during the process of laying out the wires between the two busbar 296 and 298. Additional busbars 296-1 and 298-1 (not shown in Figure 60) with an adhesive conductive layer are attached on top of each of the two initial copper busbar 296 and 298 in order to seal the electrical connection between the 5 busbar and the tungsten wires. The PVB foil 292 is finally laminated between two glass sheets. The glass lamination is carried out at an elevated temperature of about 130 °C, which is just above the PVB melting point, for a period of about 60 minutes. When laminated under these conditions, the PVB interlayer 292 becomes optically clear and binds the two panes of glass together. In the finished product two separate 10 copper busbars 296 and 298 stick out of the laminated glass windscreen and are connected to the source of electrical energy. By applying a voltage between the busbars 296 and 298 electric current flows through the integrated wires 294 and the glass is heated in order to control condensation, de-mist and de-icing of the automotive windscreen to improve visibility and safety.

15

The inventor has found that the above automotive manufacturing process for heated laminated glass is useful for the production of cheap digitizer systems. However several changes are required due to the dissimilarity between the physical arrangement for the automotive heated windscreen and the digitiser conductors. 20 Usually a digitiser for an interactive display will have a flat glass while the windscreen will be typically use curved glass. The heated windscreen illustrated in Figure 60 is based on a nearly parallel set of wires but a digitiser functions using an X-Y array of intersecting wires (see Figure 1) to establish crossing nodes distributed over the whole surface. In contrast to a digitiser, the heated windscreen application requires 25 only two electrical connections to send the electrical current through the set of the wires connected in parallel to each other in order to heat the glass. Thus the main difference comes from the necessity to establish individual connections to each wire in the X-Y array for the digitiser and the desire to connect distributed sensing electronics to each individual wire of the X-Y sensing wire grid. The novel methods described 30 below for connecting distributed electronics individually to each section of wire in the X-Y grid help to develop a large volume manufacturing technology for the digitiser.

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Method of Manufacture for glass overlay digitiser

A preferred method for manufacturing the digitiser grid using thin metallic wires having a diameter between 10 micron and 30 micron integrated in a glass LCD display screen with a diagonal size ranging from 12" to 120" will now be described with 5 reference to Figures 61 to 66.

As shown, in step S301 (see Figure 61) a first adhesive copper busbar strip 305 is applied to the PVB sheet 303 along the Y-direction. In step S303 a thin 20 micron tungsten wire 309 is bonded onto the surface of the PVB sheet (see Figure 62a) using 10 heat source with a temperature of about 130 °C which is sufficient to locally melt the surface of the PVB foil. Using robotic arm 308 the wire 301 is laid along the predefined serpentine pattern along the X-direction of the PVB sheet 303 substantially perpendicular to the first copper busbar 305. Straight sections of wire 301 might become highly visible due to the moire effect caused by the intersection of the straight 15 wire with nearly parallel vertical or horizontal edges of the pixels of the LCD display. This moire effect can be substantially reduced by laying out the wire 301 in a undulating pattern with sinusoidal modulation of the order of about ±0.5mm or larger and a period of about 5mm. Preferably the spacing between adjacent conductors of the X-Y grid should be equal to the period of the sinusoidal undulations or should be 20 an integer multiple of it to reproduce the geometry of the intersecting set of wires 301 and 302 at each node of the X-Y grid. The most appropriate conductor spacing for the X-Y grid ranges from five to six millimetres in order to provide better than one millimetre accuracy for the location of various targets ranging from a large diameter adult finger to a narrow tip of the conductive stylus.

25

In step S305 an additional conductive adhesive copper busbar strip 305-1 is applied on the top of the first copper busbar 305 in order to sandwich the thin tungsten wire between two copper strips.

30 In step S307 the PVB sheet 303 is turned over in order to expose the opposite surface of the PVB foil. A second copper busbar strip 306 is attached to the PVB sheet along the X-direction, substantially perpendicular to the first busbar 305 (see Figure 62b). In step S309 using robotic arm 308 a tungsten wire 302 is thermally bonded onto the

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PVB sheet 303 into the predefined serpentine pattern along the Y direction substantially perpendicular to the second copper busbar 306. In order to keep Figure 62b more readable the first set of wires 301 are represented in the Figure as straight dotted lines ignoring the original undulating pattern.

5

In step S311 the PVB sheet 303 is cut to the desired size. The PVB is preferably cut flush to the edges of the first and second copper busbars. In step S313 a wider conductive adhesive copper strip 307 (see Figure 63b) is applied on the top of the second busbar 306 and the remaining width of this wider copper strip is tucked in 10 underneath the PVB sheet 303 to present an electrical contact surface for the second busbar 306 on both surfaces of the PVB material. Thus Figure 63a shows that both sets of wires 301 and 302 can be electrically contacted via the busbar 305 and 307 on the same side of the PVB foil 303.

15 In step S315 the individual wires from the set of wires 301 and 302 are electrically insulated (isolated) from their neighbours by physically removing narrow strips of the copper busbar between adjacent arms of the thin wire 301 and 302 (see Figure 64). This can be done, for example, by punching through the PVB foil 303 with an appropriate dice or using a laser cutter or suitable etching or the like. As a result of 20 this procedure a set of electrically isolated contact pads 315 and 317 is created - this way a dedicated contact pad is made for each individual wire belonging to the X-Y wire grid.

In step S317 the PVB foil 303 is placed between two sheets of glass of slightly 25 dissimilar size in such a manner that the PVB foil is left exposed near the areas with the contacts pads 315 and 317 created out of the first and second busbars 305 and 307. The bottom glass 311 shown in the Figure 65a has a size similar to the size of the PVB foil 303 itself. The top glass 310 is slightly undersized to leave sufficient space for the placement of the first and second PCB 312 and 313 above the contact 30 pads 315 and 317 after the lamination step. The glass thickness for glass 310 and glass 311 is typically chosen from 3mm or 4mm; larger thicknesses are undesirable as they increase the overall weight of the laminated glass screen. In this embodiment, the bottom glass is for placement facing the LCD display (not shown) and the top

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glass is provided for the user touch screen.

In step S319 a temporary adhesive strip is applied to conceal the exposed areas of the PVB foil and the exposed contact pads 315 and 317. The strip is made from a 5 material like polyimide which will not bond permanently to the PVB at elevated temperatures used during the lamination process. Following this step the whole assembly is placed in a vacuum bag and air is evacuated from it. The micro-rough surface of the PVB foil 303 provides efficient channels for evacuating air from the inside of the sandwiched construction. The assembly is heated and after the holding 10 time at the elevated temperature, the glass is cooled down and the temporary adhesive strip is removed exposing contact pads 315 and 317. This heating step melts the PVB and bonds the glass panels 310 and 311 together sandwiching the wires 301 and 302 in place.

15 In step S321 first and second digitiser PCBs 312 and 313 (carrying digitiser electronics) are attached on the top of the contact pads 315 and 317 (see Figure 65b). The contact pads 315 and 317 are soldered to corresponding contact pads 322 and 323 of the first and second PCBs 312 and 313, as illustrated in more detail for one of the PCBs (313) in Figure 66a. In order to facilitate the soldering procedure the PCB 20 313 is prepared with contact pads 323 on both surfaces of the PCB with the copper plated though hole 321 of about 1mm in diameter arranged in the middle of the contact pads 323. The PCB is then cut to size through the middle of the holes 321 thus opening up the vertical conductive strips at each solder joint location. The other PCB 312 is prepared is a similar way. The solder joints between the PCB and the X-Y 25 wire grid are created by soldering the contact pads 315 and 317 to the first and second PCBs 312 and 313 (respectively) with the main solder joint established between the vertical surfaces of the half-hole 321 and the edge of the corresponding contact pad 315 or 317. The electronic components carried by the PCBs are soldered to one side of the first and second PCBs 312 and 313.

30

Finally, in step S321, a cable connector 319 is attached between the second PCB 313 and the first PCB 312 to provide a path for digitiser control signals (see Figure 65b). It is preferable to keep the microcontroller physically on the same PCB as is connected

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to the set of wires used for the detection conductors in order to avoid using the cable 319 to carry the analogue measurement signals to the microcontroller for analogue to digital conversion (to avoid noise being introduced through the connector 319). Typically, the detection conductors will be connected along the shorter dimension of 5 the screen as it is preferable to have fewer detection conductors than there are excitation conductors on a typical interactive display. Preferably, the detection PCB also has an additional generic host connector (such as a USB connector) in order to provide a communication path to the host computer.

10 Modifications of Method of Manufacture for glass overlay digitiser

A detailed description has been given above of a manufacturing method for a digitiser that can be implemented over a wide range of digitiser sizes. A number of modifications to the manufacturing method for the above described digitiser will now be described.

15

In the above described method of manufacture, a tungsten wire was used to form the excitation and detection conductors 301 and 302. Tungsten wire is preferred because of its low electrical resistance and high mechanical strength. The ultimate tensile strength (the maximum stress that a material can withstand while being stretched or 20 pulled before necking) for tungsten is about seven times larger than for copper, while its resistivity is only about three times higher than that of a copper wire. However for very large diagonal displays with a diagonal size exceeding 80" it might be preferable to start using a 20 micron thick copper wire to reduce the limitation in excitation frequency caused by the mutual cross-talk. The increase in crosstalk for long wires is 25 caused by the increasing ratio between the self resistance of the wires and the frequency dependant impedance caused by the mutual capacitance between adjacent parallel wires.

In the embodiments described above conductors were arranged in perpendicular 30 regular arrays. As those skilled in the art will appreciate, the excitation and detection conductors do not have to be provided in such regular and perpendicular arrays. The spacing between the conductors may be non-uniform; and/or one or more of the conductors may have one or more curves along their lengths; and/or the conductors

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may lie at an angle other than 90 degrees to each other. Provided the grid of conductors defines intersection points between the excitation and detection conductors over the desired measurement area of the digitiser, the processing electronics can determine the desired locations.

5

In the main method of manufacture discussed above a single length of PCB was used for each of the first and second PCBs 312 and 313. However each of these PCBs might be made of several pieces connected together via a suitable connector. This indeed might be practically required for large diagonal sizes of digitiser where the total 10 length of each of the first and second PCB 312 or 313 might exceed one meter.

In the main method of manufacture discussed above, the top 310 and bottom 311 glass panels had different sizes in order to provide support for the exposed area of the PVB film with the contact pads 315 and 317. This support for the PVB film is required 15 during the lamination step and the attachment of the first PCB 312 to the contact pads 315 and the attachment of the second PCB 313 to the contact pads 317. The embodiment shown in Figure 66b shows that during such manufacturing steps it is possible to use a temporary support structure 325, for example made of non-stick material. The non-stick support 325 can be manufactured from material like polyimide 20 which does not bond to the PVB material at elevated temperatures of about 130 °C used during the lamination process. The support 325 can then be removed after the whole system is assembled leaving rigid PCBs 312 and 313 on a free standing PVB film 303 which retains enough flexibility and mechanical stability after the lamination process. This allows glass panels of the same size to be used for the top and bottom 25 in the manufacture of the digitiser.

For an interactive display with a reduced bezel, it is possible to mount the PCBs 312 and 313 at a relatively large angle to the surface of the glass. In order to provide a larger bending radius for the PVB material it might be advantageous to mould the PVB 30 at an angle to the glass surface during the lamination step. Figure 67a shows the arrangement for forming the large bending radius for the PVB foil using top support 327 and the bottom support 326. The top support 327 is removed after the lamination step and the first PCB 312 is attached and soldered to the contact pads 315, while the

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second PCB 313 is attached and soldered to the contact pads 317. Following this step the bottom support 326 is removed and the first PCB 312 and the second PCB 313 can be moved further to their mounting position inside the display mechanical support structure (not shown).

5

For a nearly zero width bezel around the finished interactive display, the PCBs 312 and 313 can be mounted perpendicular to the surface of the glass. Figure 68 shows the preferred geometry for this arrangement. The second PCB 313 shown in this Figure is soldered directly to the contact pads 317. In this particular case the liquid 10 solder material will be pulled by surface tension into the copper cavity formed by the walls of the copper plated half-hole 321 and the surface of the contact pad 317. An extra mass of solder material will also help to make the electrical contact between the contact pads 317 and 323. The provision of the copper plated half-hole at the edge of the PCB during soldering provides an optimum mechanical and electrical contact 15 between the contact pads 323 located on the PCB and the contact pads 317 located on the PVB. With this modification the surface of the bottom glass 311 will provide a surface for interacting with a user finger and the surface of the top glass 310 will be facing the LCD matrix display (not shown).

20 In the main method of manufacture discussed above, the set of wires 301 and 302 forming the X-Y grid structure were laid down on opposite surfaces of the same PVB foil 303. However, in an alternative embodiment two separate PVB foils may be used, each carrying its own set of wires - set 301 or set 302. The two PVB foils can then be mounted on top of each other during the lamination process so that the sets of wires 25 301 and 302 can be placed orthogonally to each other. Such construction is very similar to the one shown in the Figures 63, 64 and 65 but can be implemented without using the wide busbar 307 which was used to provide electric contacts on both sides of the single PVB foil 303. However this modification is likely to result in higher overall costs due to the need to double the amount of the utilised PVB material.

30

In the main method of manufacture discussed above the bottom glass 311 was facing an active LCD matrix. The array of X-Y wires (actively grounded through the capacitors 63 (see Figure 5) and 95 (see Figure 11)) provides some electrostatic

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shielding for the electrical noise originated in the driving circuitry of the LCD matrix. For dense X-Y grid digitisers with wire separation of the order of 5 to 6 mm such virtual electrostatic screening by several hundred grounded wires should be efficient enough to provide a reasonable signal to noise ratio when detecting individual fingers 5 located close to the surface of the top glass 310. However, it is possible to improve the electrostatic screening by covering the free surface (the lower surface shown in the Figures) of the bottom glass 311 with a homogeneous layer of transparent ITO film. Such a step, while reducing the coupled noise, nevertheless might result in reduced sensitivity of the projective capacitive X-Y grid to the presence of a finger and 10 thus might be unattractive for digitisers which need to work with the gloved fingers. The actual signal to noise ratio in this case can be improved by increasing the thickness of the bottom glass 311 compared to the thickness of the top glass 310. Even better results can be obtained by placing an ITO film on a separate thin glass or plastic layer and by introducing a small air gap of the order of one to five millimetres 15 between this new sheet with ITO film and the free surface of the bottom glass 311.

In the main method of manufacture discussed above the PVB foil 303 was sandwiched between the top glass 310 and the bottom glass 311. However in other embodiments only one glass panel may be used. For example, during the lamination 20 process a non-stick support 326 may be used instead of the bottom glass 311 or a non-stick support 325 may be used instead of the top glass 310. The non-stick support is removed after the lamination and the attachment of the first and second PCBs 312 and 313 to the contact pads 315 and 317. By substituting one of the glass sheets with a removable non-stick support it is possible to achieve a twofold reduction 25 in the overall weight of the interactive screen. This approach is specifically suited for applications for smaller diagonal size digitisers which do not require high levels of vandal proof performance.

In the main method of manufacture discussed above, a PVB foil 303 was used as an 30 interlayer for the lamination process. Other lamination materials could be used instead of PVB, including thermoplastic glass lamination materials such as EVA (Ethyl Vinyl Acetate) and TPU (thermoplastic Polyurethane). EVA has emerged as a good alternative to PVB. The strong affinity to moisture makes PVB film difficult to be stored

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and processed without particular concerns on humidity. Unlike PVB material, EVA adhesive film is non-sticky and inert to water moisture. Thus production equipment and relevant processes for EVA glass lamination may, in some cases, be easier and simpler than conventional PVB lamination.

5

Method of Manufacture for front-projected (whiteboard) digitiser The main method of manufacture discussed above is specific to the manufacturing of the digitiser in the form of a transparent interactive glass screen overlay. Another example of the required digitiser includes interactive whiteboard digitisers connected 10 to a computer. Typically a projector mounted on the ceiling projects the computer's desktop display onto the whiteboard's surface where users control the computer using a finger, stylus, or other device. The white surface of the board could be made out of a sheet of formica, melamine or polycarbonate with a typical thickness of less than 1.25mm. A thin sheet digitiser can be mounted underneath the white surface of the 15 board.

A preferred method for manufacturing the digitiser grid for use in an interactive whiteboard with a diagonal sizes ranging from 20" to 200" will now be described with reference to Figures 69 to 71.

20

As shown, in step S323 (see Figure 69) a first layer of double-sided mounting adhesive is applied on a surface of cardboard. The cardboard with a thickness of about 0.9mm is served as a support for the wire grid and electronics and is chosen for its low cost. It is preferred to use brown kraft paper slip sheets due to their non-25 porous, moisture and bacteria resistance properties. The double-sided mounting adhesive with a thickness of about 25|jm is a standard product widely used for the lamination of the printed materials.

In step S325 (see Figure 70a) a first conductive adhesive copper busbar strip 355 is 30 applied to the cardboard 353 along the Y-direction. The busbar used in this embodiment is of the same type as was described previously for the heated glass automotive windscreen technology. In step S327 a thin copper wire 359 with a diameter of approximately 50|jm is placed on a surface of the adhesive by a robotic

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arm 358 into a predefined serpentine pattern along the X-direction of the cardboard 353 substantially perpendicular to the first copper busbar 355. There is no need to use the undulating pattern shown for the transparent glass overlay digitiser in the Figure 62 as the wire grid pattern of the whiteboard digitiser is completely concealed 5 underneath the opaque surface of the whiteboard. The capability of using straight sections of the wire 351 simplifies the laying process by pulling the wire 351 between the posts 362 and 364 as shown in the Figure 70a. After bonding the wire 351 to the first adhesive layer the cardboard 353 with the bonded wires 351 can be pulled out of the manufacturing rig with integrated posts 362 and 364 and a new sheet of the 10 cardboard 353 can be inserted in the rig for wiring the next digitiser.

In step S329 a second double-sided mounting insulating adhesive is applied over the array of bonded thin copper wires 351, whilst avoiding to cover the first copper busbar 355. In step S331 a second conductive adhesive copper busbar strip 356 is applied to 15 the cardboard 353 along the X-direction (see Figure 70b). In step S333 a thin copper wire 359 is placed on a surface of the second adhesive by the robotic arm 358 into the predefined serpentine pattern along the Y-direction of the cardboard 353 perpendicular to the second copper busbar 356. Preferably the wire 352 is pulled between the posts 366 and 368 as shown in the Figure 70b. After bonding the wire 20 352 to the second adhesive layer the cardboard 353 with the bonded wires 351 and 352 can be pulled out of the manufacturing rig with the integrated posts 366 and 368 and a new sheet of the cardboard 353 can be inserted between the posts for wiring the next digitiser.

25 In step S335 the cardboard 353 is cut to the desired size, thereby simultaneously separating originally continuous wires 351 and 352 onto individual pieces of straight wire. In step 337 a couple of wider conductive adhesive copper strips 355-1 and 356-1 are applied on the top of the first and second busbars 355 and 356 respectively. The remaining width of these wider copper strips are then tucked in underneath the 30 cardboard to present electrical contact surfaces for the first and second busbars 355 and 356 on both surfaces of the cardboard 353. This step is similar to the step S313 discussed above and is illustrated in Figure 63b.

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In step S339 the first and second copper busbars 355 and 356 are punched through (or otherwise cut/etched) between adjacent arms of the thin wires 351 and 352 with an appropriate dice in order to create electrically isolated contact pads 365 and 367 for each wire belonging to the X-Y wire grid (see Figure 71a).

5

In step S341 a third double sided mounting adhesive film is applied over the array of bonded wires, this time also covering the contact pads 365 and 367. The cardboard 353 with integrated X-Y wire grid is then attached to the inner surface of the whiteboard 360 in the step S343. In step S345 the first and second PCBs 362 and 363 10 are attached on the top of the cardboard over the contact pads 365 and 367 (see Figure 71b). The contact pads of the PCB are soldered to the contact pads 365 and 367 using the same approach as was described previously with reference to Figure 66a. In this approach the copper plated half-hole at the edges of the PCBs 362 and 363 serve as additional vertical contact pads for soldering to the contact pads 365 and 15 367 of the X-Y grid.

In step S345 an electric cable 369 is connected between the first and second PCBs to supply control signals for operating the digitiser. As discussed above, preferably, the detection PCB carries the microcontroller and also has an additional generic host 20 connector (such as a USB connector) in order to provide a communication path to the host computer.

Modifications of Method of Manufacture for front-projected (whiteboard) digitiser A detailed description has been given above of a manufacturing method for a 25 whiteboard digitiser that can be implemented over a wide range of sizes. A number of modifications to this manufacturing method will now be described.

In the above method of manufacturing the whiteboard, a copper wire with diameter of approximately 50|jm was used to form the excitation and detection conductors 351 30 and 352. It is possible to use copper wire with either larger (e.g. 125 |jm) or smaller diameter; however special care should be taken for large diagonal digitisers as using larger diameters of wire can increase unwanted capacitive coupling between adjacent

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wires. Other materials like tungsten can also be used instead of copper; however it is likely that copper wire will be the cheapest wire for manufacturing such digitisers.

The cardboard used in the above embodiment had a thickness of about 0.9mm.

5 Other thicknesses up to 5mm can be easily used. Other non-conductive substrates like plastic film can be used instead of cardboard; however this might result in increased difficulties in handling the assembled digitiser and/or increase the cost of its manufacture.

10 In the above method of manufacturing the whiteboard digitiser, the wide conductive adhesive copper strip 355-1 was attached to the first busbar 355 in the step S337 simultaneously with a similar wide conductive copper strip 356-1 attached to the second busbar 356. However it might be easier to attach the copper strip 355-1 to the first busbar 355 at the end of the step S327. In such case the second double sided 15 mounting adhesive can be applied to the whole surface of the cardboard 353 including the surface of the first busbar 355-1 thus simplifying the manufacturing process.

In a modification to the above embodiment, an extra spacer layer may be provided between the sets of wires 351 and 352 in order to make their mutual self-capacitance 20 (without the presence of the target) more reproducible across the surface of the X-Y digitiser. Such an extra spacer layer may be made of plastic with a thickness of about 0.4mm and can be applied to the surface of the first adhesive just before step S329, in which the second double-sided mounting adhesive is applied over the first set of wires 351. It is also possible to use the cardboard 353 as a spacer between the wires in the 25 X-Y grid. In such case the wires 351 and 352 would be bonded to opposite surfaces of the cardboard 353 in a manner similar to the one described for the main manufacturing method illustrated in the Figure 61. However in this modification the cardboard thickness should be restricted to about 1mm. In this case, the set of detection wires are preferably mounted on the surface of the cardboard 353 which 30 closest to the writing surface of the whiteboard 360.

By using an optically clear plastic film instead of the cardboard 353 and by using an optically clear double-sided mounting adhesive film it is possible to construct an

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optically transparent thin digitiser with integrated X-Y wire grid and electronics. It is then possible to mount this thin film digitiser onto a rear-projection (diffusion) film in order to create a thin rear-projection digitiser which can be mounted on any glass surface - for instance it can be placed on a store window to transform the window into 5 an Interactive Digital Signage. In this case the opposite surface of the window glass can be used by the general public to interact with the image displayed using a finger. For such an embodiment using a thin transparent digitiser the thickness of the conductive wires are preferably reduced to about 20 microns to make them practically invisible to the naked eye. Depending on the user experience, it might be desirable to 10 modify the straight lines of the X-Y grid into the undulating pattern shown in Figure 62. However with the rear-projection film placed in front of the digitiser, the X-Y grid will be efficiently concealed and the remaining shadow from the wires will be watered down thus reducing the visibility of any moire pattern even if using straight wires.

15 Alternative Method of Manufacture

An alternative method for manufacturing the digitiser grid using thin metallic wires having a diameter between 10micron and 20micron will now be described with reference to Figures 72 to 73. A shown, in step s101 a clear double-sided mounting adhesive 221 is applied to the surface of a protective glass substrate 223. In step 20 s103 a first printed circuit board (PCB) 225 is attached along the Y edge of the glass substrate 223. In step s105, a robotic arm 227, with multiple feeds of wires 229, bonds a regular (uniform) array of thin copper wires 230 along the X-direction of the glass substrate, perpendicular to the first PCB 225. In step s107, each wire from the created first array of thin wires is terminated at the first PCB using an ultrasonic 25 wedge bonder 231 to cut and bond the wire 230 to a gold plated copper based PCB pad 233. Each copper wire 230 is glued along the X-direction of the glass substrate by the adhesive layer 221.

Ultrasonic bonding is a process that involves the use of force, time and ultrasonics to 30 join two materials. The wire is pressed against the surface (both at ambient temperature) at low force and vibrated for a limited period of time to achieve the bond. Ultrasonic energy, when applied to the metal to be bonded, renders it temporarily soft and plastic. This causes the metal to flow under pressure. The acoustic energy frees

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molecules and dislocates them from their pinned positions and that allows the metal to flow under the low compressive forces of the bond. Thus heat at the bond site becomes a bi-product of the bonding process and so external heat is not necessary. Such ultrasonic bonding is also called a "cold weld". There are two types of ultrasonic 5 bonding: wedge bonding and tape automated bonding (TAB). Either may be used although in this embodiment, a wedge bonder 231 is preferred as there is more control over the placement of the wires by the robotic arm 227 (in TAB bonding, the wire is already pre-aligned over the pad to which it is to be bonded).

10 Once all the required wires 230 have been bonded to the first PCB 225, the processing proceeds to step s109 where another optically clear double-sided mounting adhesive 237 is applied over the array of bonded wires 230. In step s111 a second PCB 239 is attached along the X edge of the glass substrate 223. In step s113 the robotic arm 227 is again used to create a second array of thin wires 241 that 15 extend along the Y-direction perpendicular to the second PCB 239. The second array of wires 241 is held in place by the adhesive layer 237. In step s115, each wire in the second array of wires 241 is terminated at the second PCB 239 using the ultrasonic wedge bonder 231 onto a gold plated copper based PCB pad 233. In step s117 an optically clear UV curable liquid lamination 245 is sprayed over the second array of 20 thin copper wires 241 in order to seal the exposed adhesive layer 237. This UV curable laminate layer is then cured with UV light to form a smooth clear optical surface for the display screen. In step s119 extra adhesive is provided around the termination points that terminate the arrays of conductor wires to the first and second PCBs 225 and 239. Finally, in step s129, a cable connector 243 is attached between 25 the second PCB 239 and the first PCB 225 to provide a path for the control signals for the excitation channels. It is preferable to keep the microcontroller physically on the same PCB as the wires used for the detection conductors 7 in order to avoid using the cable 243 to carry the analogue measurement signals to the microcontroller for analogue to digital conversion (in order to avoid noise being introduced through the 30 connector 243). Typically, the detection conductors will extend along the shorter dimension of the screen and therefore will be connected to the first PCB 225 (as it is preferable to have fewer detection conductors than there are excitation conductors on a typical television screen). Preferably, the first PCB 225 also has an additional

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generic host connector (such as a USB connector) in order to provide a communication path to the host computer.

In the above described embodiment, copper wire was used to form the excitation and 5 detection conductors. Copper wire is preferred because of its low electrical resistance and therefore its ability to be used at higher excitation frequencies for large digitiser dimensions. However, ultrasonic bonding with copper wire can be troublesome due to heavier oxidation of the surface of the copper wire and unwanted material build up on the wedge bonder caused by these residuals sticking to the surface of the wedge 10 bonder. Therefore, instead of using thin copper wires, thin aluminium wires may be used instead. Preferably, the aluminium wires have diameters between 10microns and 20microns so that they are practically invisible to the human eye at a distance exceeding 10cm.

In the above described embodiment ultrasonic bonding was used to attach a piece of 15 wire to the contact pads of the PCB. It might be advantageous to use ultrasonic soldering instead. Ultrasonic bonding uses ultrasonic energy to join parts without adding any kind of filler material while ultrasonic soldering uses a filler material, namely solder, to form a joint. An intensified ultrasonic beam generates micro vibrations with a 'brushing effect', which results in a complete removal of the oxide 20 layer for immediate wetting with the solder alloy on the surface of the substrate. This means that the use of any 'flux' is no longer required. Ultrasonic soldering can be assisted by tinning the contact pads of the PCB before attaching PCBs 225 and 239 to the substrate 223. It is possible to use a low temperature melting solder to simplify the process, such as Indalloy 1E (Indium-tin eutectic 52% In 48% Sn ) with a melting point 25 of about 118 °C. By using the Field's alloy (eutectic alloy of bismuth, indium, and tin: 32.5% Bi, 51% In, 16.5% Sn) with a melting point of about 62 °C it might be possible to make a solder joint using mainly frictional self-heating of the solder junction caused by the dissipation of the ultrasonic energy.

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Claims (1)

1. Claims:

   1. A digitiser comprising:

   5 a grid of conductors comprising a plurality of excitation conductors and a plurality of detection conductors;

   excitation circuitry for applying excitation signals to selected excitation conductors;

   measurement circuitry for obtaining measurements from selected detection 10 conductors; and processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of conductors;

   wherein the excitation circuitry is arranged to operate in a cyclic manner to 15 select each of said excitation conductors during an excitation cycle, wherein an excitation cycle comprises a sequence of excitation intervals during each of which a different pair of neighbouring excitation conductors is selected by the excitation circuitry and to which complementary excitation signals are applied, and wherein the excitation circuitry is arranged to polarity modulate each excitation signal using a 20 polarity control signal so that the polarity of the excitation signal applied to a selected conductor changes during a time that the excitation conductor is selected.

   2. A digitiser according to claim 1, wherein the polarity control signal is periodic and wherein the time that an excitation conductor is selected is an integer multiple of

   25 the period of the polarity control signal.

   3. A digitiser according to claim 1 or 2, wherein the excitation circuitry is arranged to select neighbouring excitation conductors during plural consecutive excitation intervals in an overlapping manner such that during a first excitation interval a given

   30 selected excitation conductor is paired with a first neighbouring excitation conductor and during a second excitation interval the given selected excitation conductor is paired with a second neighbouring excitation conductor.

   4. A digitiser according to claim 3, wherein the excitation circuitry is arranged so

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   that, during an initial excitation interval of an excitation cycle, excitation conductors are selected without overlap with excitation conductors selected in a final excitation interval of a preceding excitation cycle.

   5 5. A digitiser according to any of claims 1 to 4, wherein the excitation circuitry is arranged to select the excitation conductors such that an excitation conductor selected during a last excitation interval of an excitation cycle neighbours an excitation conductor selected by the excitation circuitry during a first excitation interval of the excitation cycle.

   10

   6. A digitiser according to any of claims 1 to 5, wherein the measurement circuitry is arranged to operate in a cyclic manner to select each of said detection conductors during a detection cycle, wherein a detection cycle comprises a sequence of detection intervals during each of which a different pair of neighbouring detection conductors is

   15 selected by the measurement circuitry.

   7. A digitiser according to claim 6, wherein the measurement circuitry is arranged to select neighbouring detection conductors during plural consecutive detection intervals in an overlapping manner such that during a first detection interval a given

   20 selected detection conductor is paired with a first neighbouring detection conductor and during a second detection interval the given selected detection conductor is paired with a second neighbouring detection conductor.

   8. A digitiser according to claim 6 or 7, wherein the measurement circuitry is 25 arranged to determine differential measurements of signals obtained from the selected pairs of neighbouring detection conductors.

   9. A digitiser according to any of claims 6 to 8, wherein each detection interval corresponds in duration to one excitation interval or wherein each excitation interval

   30 corresponds in duration to one detection cycle.

   10. A digitiser according to any of claims 1 to 9, wherein the measurement circuitry comprises a plurality of measurement channels each arranged to obtain

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   measurements from a different subset of the detection conductors, wherein each measurement channel is arranged to operate in a cyclic manner to select each of the detection conductors within the corresponding subset during a detection cycle, wherein the measurement circuitry comprises sample and hold circuitry for sampling 5 and holding measurements obtained from each measurement channel and an analogue to digital converter for converting measurements held by the sample and hold circuitry into corresponding digital values, wherein the sample and hold circuitry comprises a plurality of first and second capacitors, each first and second capacitor being associated with a respective measurement channel, wherein the sample and

   10 hold circuitry is arranged such that during first measurement intervals, signals from the measurement channels are applied to the associated first capacitors and during second measurement intervals, signals from the measurement channels are applied to the associated second capacitors, and wherein during the first measurement intervals the sample and hold circuitry is arranged to couple signals stored on the

   15 second capacitors to the analogue to digital converter for conversion into corresponding digital values and during the second measurement intervals the sample and hold circuitry is arranged to couple signals stored on the first capacitors to the analogue to digital converter for conversion into corresponding digital values.

   20 11. A digitiser according to any of claims 1 to 10, comprising control circuitry for generating control signals for controlling selection of the excitation conductors by the excitation circuitry and for generating control signals for controlling selection of the detection conductors by the measurement circuitry.

   25 12. A digitiser according to claim 11, wherein the control circuitry is arranged to generate said control signals on a cyclic basis and in a free running manner independently of said processing circuitry and is arranged to send a signal to the processing circuitry each measurement cycle to inform the processing circuitry that measurements are ready to be processed by the processing circuitry.

   30

   13. A digitiser comprising:

   a grid of conductors comprising a plurality of excitation conductors and a plurality of detection conductors;

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   excitation circuitry for applying excitation signals to selected excitation conductors;

   measurement circuitry for obtaining measurements from selected detection conductors; and

   5 processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of conductors;

   wherein the measurement circuitry is arranged to operate in a cyclic manner to select each of said detection conductors during a detection cycle, wherein a detection 10 cycle comprises a sequence of detection intervals during each of which a different pair of neighbouring detection conductors is selected by the measurement circuitry, wherein the measurement circuitry is arranged to polarity modulate a detection signal obtained from each selected detection conductor using a polarity control signal so that the polarity of the detection signal changes during a time that the detection conductor 15 is selected.

   14. A digitiser according to claim 13, wherein the polarity control signal is periodic and wherein the time that a detection conductor is selected is an integer multiple of the period of the polarity control signal.

   20

   15. A digitiser according to claim 13 or 14, wherein the measurement circuitry is arranged to select neighbouring detection conductors during plural consecutive detection intervals in an overlapping manner such that during a first detection interval a given selected detection conductor is paired with a first neighbouring detection

   25 conductor and during a second detection interval the given selected detection conductor is paired with a second neighbouring detection conductor.

   16. A digitiser according to claim 15, wherein the measurement circuitry is arranged so that, during an initial detection interval of a detection cycle, detection

   30 conductors are selected without overlap with detection conductors selected in a final detection interval of a preceding detection cycle.

   17. A digitiser according to any of claims 13 to 16, wherein the measurement

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   circuitry is arranged to select the detection conductors such that a detection conductor selected during a last detection interval of a detection cycle neighbours a detection conductor selected by the measurement circuitry during a first detection interval of the detection cycle.

   5

   18. A digitiser according to any of claims 13 to 17, wherein the excitation circuitry is arranged to operate in a cyclic manner to select each of said excitation conductors during an excitation cycle, wherein an excitation cycle comprises a sequence of excitation intervals during each of which a different pair of neighbouring excitation

   10 conductors is selected by the excitation circuitry.

   19. A digitiser according to claim 18, wherein the excitation circuitry is arranged to select neighbouring excitation conductors during plural consecutive excitation intervals in an overlapping manner such that during a first excitation interval a given selected

   15 excitation conductor is paired with a first neighbouring excitation conductor and during a second excitation interval the given selected excitation conductor is paired with a second neighbouring excitation conductor.

   20. A digitiser according to claim 18 or 19, wherein each detection interval 20 corresponds in duration to one excitation interval or wherein each excitation interval corresponds in duration to one detection cycle.

   21. A digitiser according to any of claims 13 to 20, wherein the measurement circuitry is arranged to determine differential measurements of signals obtained from

   25 the selected pairs of neighbouring detection conductors.

   22. A digitiser according to any of claims 13 to 20, wherein the measurement circuitry comprises a plurality of measurement channels each arranged to obtain measurements from a different subset of the detection conductors, wherein each

   30 measurement channel is arranged to operate in a cyclic manner to select each of the detection conductors within the corresponding subset during a detection cycle, wherein the measurement circuitry comprises sample and hold circuitry for sampling and holding measurements obtained from each measurement channel and an

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   analogue to digital converter for converting measurements held by the sample and hold circuitry into corresponding digital values, wherein the sample and hold circuitry comprises a plurality of first and second capacitors, each first and second capacitor being associated with a respective measurement channel, wherein the sample and 5 hold circuitry is arranged such that during first measurement intervals, signals from the measurement channels are applied to the associated first capacitors and during second measurement intervals, signals from the measurement channels are applied to the associated second capacitors, and wherein during the first measurement intervals the sample and hold circuitry is arranged to couple signals stored on the

   10 second capacitors to the analogue to digital converter for conversion into corresponding digital values and during the second measurement intervals the sample and hold circuitry is arranged to couple signals stored on the first capacitors to the analogue to digital converter for conversion into corresponding digital values.

   15 23. A digitiser according to any of claims 13 to 22, comprising control circuitry for generating control signals for controlling selection of the excitation conductors by the excitation circuitry and for generating control signals for controlling selection of the detection conductors by the measurement circuitry.

   20 24. A digitiser according to claim 23, wherein the control circuitry is arranged to generate said control signals on a cyclic basis and in a free running manner independently of said processing circuitry and is arranged to send a signal to the processing circuitry each measurement cycle to inform the processing circuitry that measurements are ready to be processed by the processing circuitry.

   25

   25. A digitiser according to any preceding claim, wherein the neighbouring conductors are adjacent conductors of the grid.

   26. A digitiser comprising:

   30 a grid of conductors comprising a plurality of excitation conductors and a plurality of detection conductors;

   excitation circuitry for applying excitation signals to selected excitation conductors;

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   measurement circuitry for obtaining measurements from selected detection conductors; and processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of 5 conductors;

   wherein the measurement circuitry is arranged to operate in a cyclic manner to select each of said detection conductors during a detection cycle, wherein a detection cycle comprises a sequence of detection intervals during each of which a different pair of neighbouring detection conductors is selected by the measurement circuitry, 10 wherein the measurement circuitry is arranged to select neighbouring detection conductors during plural consecutive detection intervals in an overlapping manner such that during a first detection interval a given selected detection conductor is paired with a first neighbouring detection conductor and during a second detection interval the given selected detection conductor is paired with a second neighbouring 15 detection conductor and wherein the measurement circuitry is arranged to determine differential measurements of signals obtained from the selected pairs of neighbouring detection conductors.

   27. A digitiser according to claim 26, wherein the measurement circuitry is 20 arranged to polarity modulate a detection signal obtained from each selected detection conductor using a polarity control signal so that the polarity of the detection signal changes during a time that the detection conductor is selected.

   28. A digitiser according to claim 27, wherein the polarity control signal is periodic 25 and wherein the time that a detection conductor is selected is an integer multiple of the period of the polarity control signal.

   29. A digitiser according to any of claims 26 to 28, wherein the measurement circuitry is arranged so that, during an initial detection interval of a detection cycle,

   30 detection conductors are selected without overlap with detection conductors selected in a final detection interval of a preceding detection cycle.

   30. A digitiser according to any of claims 26 to 29, wherein the measurement

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   circuitry is arranged to select the detection conductors such that a detection conductor selected during a last detection interval of a detection cycle neighbours a detection conductor selected by the measurement circuitry during a first detection interval of the detection cycle.

   5

   31. A digitiser according to any of claims 26 to 30, wherein the excitation circuitry is arranged to operate in a cyclic manner to select each of said excitation conductors during an excitation cycle, wherein an excitation cycle comprises a sequence of excitation intervals during each of which a different pair of neighbouring excitation

   10 conductors is selected by the excitation circuitry.

   32. A digitiser according to claim 31, wherein the excitation circuitry is arranged to select neighbouring excitation conductors during plural consecutive excitation intervals in an overlapping manner such that during a first excitation interval a given selected

   15 excitation conductor is paired with a first neighbouring excitation conductor and during a second excitation interval the given selected excitation conductor is paired with a second neighbouring excitation conductor.

   33. A digitiser according to claim 31 or 32, wherein each detection interval 20 corresponds in duration to one excitation interval or wherein each excitation interval corresponds in duration to one detection cycle.

   34. A digitiser according to any of claims 26 to 33, wherein the measurement circuitry comprises a plurality of measurement channels each arranged to obtain

   25 measurements from a different subset of the detection conductors, wherein each measurement channel is arranged to operate in a cyclic manner to select each of the detection conductors within the corresponding subset during a detection cycle, wherein the measurement circuitry comprises sample and hold circuitry for sampling and holding measurements obtained from each measurement channel and an 30 analogue to digital converter for converting measurements held by the sample and hold circuitry into corresponding digital values, wherein the sample and hold circuitry comprises a plurality of first and second capacitors, each first and second capacitor being associated with a respective measurement channel, wherein the sample and

   -89-

   hold circuitry is arranged such that during first measurement intervals, signals from the measurement channels are applied to the associated first capacitors and during second measurement intervals, signals from the measurement channels are applied to the associated second capacitors, and wherein during the first measurement 5 intervals the sample and hold circuitry is arranged to couple signals stored on the second capacitors to the analogue to digital converter for conversion into corresponding digital values and during the second measurement intervals the sample and hold circuitry is arranged to couple signals stored on the first capacitors to the analogue to digital converter for conversion into corresponding digital values.

   10

   35. A digitiser according to any of claims 26 to 34, comprising control circuitry for generating control signals for controlling selection of the excitation conductors by the excitation circuitry and for generating control signals for controlling selection of the detection conductors by the measurement circuitry.

   15

   36. A digitiser according to claim 35, wherein the control circuitry is arranged to generate said control signals on a cyclic basis and in a free running manner independently of said processing circuitry and is arranged to send a signal to the processing circuitry each measurement cycle to inform the processing circuitry that

   20 measurements are ready to be processed by the processing circuitry.

   37. A digitiser comprising:

   a grid of conductors comprising a plurality of excitation conductors and a plurality of detection conductors;

   25 excitation circuitry for applying excitation signals to selected excitation conductors;

   measurement circuitry for obtaining measurements from selected detection conductors; and processing circuitry for processing measurements obtained by the

   30 measurement circuitry to detect one or more objects positioned adjacent the grid of conductors;

   wherein the excitation circuitry is arranged to operate in a cyclic manner to select each of said excitation conductors during an excitation cycle, wherein an

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   excitation cycle comprises a sequence of excitation intervals during each of which a different pair of neighbouring excitation conductors is selected by the excitation circuitry and to which excitation signals with opposite polarity are applied, wherein the excitation circuitry is arranged to select neighbouring excitation conductors during 5 plural consecutive excitation intervals in an overlapping manner such that during a first excitation interval a given selected excitation conductor is paired with a first neighbouring excitation conductor and during a second detection interval the given selected excitation conductor is paired with a second neighbouring excitation conductor and wherein the excitation circuitry is arranged to select the excitation 10 conductors such that an excitation conductor selected during a last excitation interval of an excitation cycle neighbours an excitation conductor selected by the excitation circuitry during a first excitation interval of the excitation cycle.

   38. A digitiser according to claim 37, wherein the excitation circuitry is arranged to 15 polarity modulate each excitation signal using a polarity control signal so that the polarity of the excitation signal applied to a selected conductor changes during a time that the excitation conductor is selected.

   39. A digitiser according to claim 38, wherein the polarity control signal is periodic 20 and wherein the time that an excitation conductor is selected is an integer multiple of the period of the polarity control signal.

   40. A digitiser according to any of claims 37 to 39, wherein the excitation circuitry is arranged so that, during an initial excitation interval of an excitation cycle, excitation

   25 conductors are selected without overlap with excitation conductors selected in a final excitation interval of a preceding excitation cycle.

   41. A digitiser according to any of claims 37 to 40, wherein the excitation circuitry is arranged to select the excitation conductors such that an excitation conductor

   30 selected during a last excitation interval of an excitation cycle neighbours an excitation conductor selected by the excitation circuitry during a first excitation interval of the excitation cycle.

   -91 -

   42. A digitiser according to any of claims 37 to 41, wherein the measurement circuitry is arranged to operate in a cyclic manner to select each of said detection conductors during a detection cycle, wherein a detection cycle comprises a sequence of detection intervals during each of which a different pair of neighbouring detection

   5 conductors is selected by the measurement circuitry.

   43. A digitiser according to claim 42, wherein the measurement circuitry is arranged to select neighbouring detection conductors during plural consecutive detection intervals in an overlapping manner such that during a first detection interval

   10 a given selected detection conductor is paired with a first neighbouring detection conductor and during a second detection interval the given selected detection conductor is paired with a second neighbouring detection conductor.

   44. A digitiser according to claim 42 or 43, wherein the measurement circuitry is 15 arranged to determine differential measurements of signals obtained from the selected pairs of neighbouring detection conductors.

   45. A digitiser according to any of claims 42 to 44, wherein each detection interval corresponds in duration to one excitation interval or wherein each excitation interval

   20 corresponds in duration to one detection cycle.

   46. A digitiser according to any of claims 37 to 45, wherein the measurement circuitry comprises a plurality of measurement channels each arranged to obtain measurements from a different subset of the detection conductors, wherein each

   25 measurement channel is arranged to operate in a cyclic manner to select each of the detection conductors within the corresponding subset during a detection cycle, wherein the measurement circuitry comprises sample and hold circuitry for sampling and holding measurements obtained from each measurement channel and an analogue to digital converter for converting measurements held by the sample and 30 hold circuitry into corresponding digital values, wherein the sample and hold circuitry comprises a plurality of first and second capacitors, each first and second capacitor being associated with a respective measurement channel, wherein the sample and hold circuitry is arranged such that during first measurement intervals, signals from the

   -92-

   measurement channels are applied to the associated first capacitors and during second measurement intervals, signals from the measurement channels are applied to the associated second capacitors, and wherein during the first measurement intervals the sample and hold circuitry is arranged to couple signals stored on the 5 second capacitors to the analogue to digital converter for conversion into corresponding digital values and during the second measurement intervals the sample and hold circuitry is arranged to couple signals stored on the first capacitors to the analogue to digital converter for conversion into corresponding digital values.

   10 47. A digitiser according to any of claims 37 to 46, comprising control circuitry for generating control signals for controlling selection of the excitation conductors by the excitation circuitry and for generating control signals for controlling selection of the detection conductors by the measurement circuitry.

   15 48. A digitiser according to claim 47, wherein the control circuitry is arranged to generate said control signals on a cyclic basis and in a free running manner independently of said processing circuitry and is arranged to send a signal to the processing circuitry each measurement cycle to inform the processing circuitry that measurements are ready to be processed by the processing circuitry.

   20

   49. A digitiser comprising:

   a grid of conductors comprising a plurality of excitation conductors and a plurality of detection conductors;

   excitation circuitry for applying excitation signals to selected excitation

   25 conductors;

   measurement circuitry for obtaining measurements from selected detection conductors; and processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of

   30 conductors;

   wherein the measurement circuitry is arranged to operate in a cyclic manner to select each of said detection conductors during a detection cycle, wherein a detection cycle comprises a sequence of detection intervals during each of which a different pair

   -93-

   of neighbouring detection conductors is selected by the detection circuitry, wherein the detection circuitry is arranged to select the detection conductors sequentially and in an overlapping manner from a start detection conductor to an end detection conductor and wherein the start detection conductor neighbours the end detection conductor 5 within said grid.

   50. A digitiser comprising:

   a grid of conductors comprising a plurality of excitation conductors and a plurality of detection conductors;

   10 excitation circuitry for applying excitation signals to selected excitation conductors;

   measurement circuitry for obtaining measurements from selected detection conductors; and processing circuitry for processing measurements obtained by the 15 measurement circuitry to detect one or more objects positioned adjacent the grid of conductors;

   wherein the measurement circuitry comprises a plurality of measurement channels each arranged to obtain measurements from a different subset of the detection conductors, wherein each measurement channel is arranged to operate in a 20 cyclic manner to select each of the detection conductors within the corresponding subset during a detection cycle, wherein a detection cycle comprises a sequence of detection intervals during each of which a different pair of neighbouring detection conductors is selected by the measurement circuitry; wherein the measurement circuitry comprises sample and hold circuitry for sampling and holding measurements 25 obtained from each measurement channel, wherein the sample and hold circuitry comprises a plurality of first and second capacitors, wherein each measurement channel has an associated first and second capacitor, wherein the sample and hold circuitry is arranged such that during first measurement intervals signals from the measurement channels are applied to the associated first capacitors and during 30 second measurement intervals signals from the measurement channels are applied to the associated second capacitors, and wherein during the first measurement intervals the sample and hold circuitry is arranged to couple signals stored on the second capacitors to an analogue to digital converter for conversion into corresponding digital

   -94-

   values and during the second measurement intervals the sample and hold circuitry is arranged to couple signals stored on the first capacitors to the analogue to digital converter for conversion into corresponding digital values.

   5 51. A digitiser comprising:

   a grid of conductors comprising a plurality of excitation conductors and a plurality of detection conductors;

   excitation circuitry for applying excitation signals to selected excitation conductors;

   10 measurement circuitry for obtaining measurements from selected detection conductors;

   control circuitry for generating control signals for controlling selection of the excitation conductors by the excitation circuitry and for generating control signals for controlling selection of the detection conductors by the measurement circuitry; and 15 processing circuitry for processing measurements obtained by the measurement circuitry to detect one or more objects positioned adjacent the grid of conductors;

   wherein the control circuitry is arranged to generate said control signals on a cyclic basis and in a free running manner independently of said processing circuitry 20 and is arranged to send a signal to the processing circuitry each measurement cycle to inform the processing circuitry that measurements are ready to be processed by the processing circuitry.

   52. A method of determining the location of an object over a measuring area 25 characterised by using a digitiser according to any of claims 1 to 51 to locate the object above the grid.

   53. A method of making a transducer for use in a digitiser, the method comprising: applying a first adhesive layer on a substrate;

   30 attaching a first printed circuit board along a first edge of the substrate;

   laying a first set of conductors on the first adhesive layer perpendicular to the first edge;

   using an ultrasonic bonder to bond ends of the conductors of the first set to the

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   first printed circuit board;

   applying a second adhesive layer on the first set of conductors;

   attaching a second printed circuit board along a second edge of the substrate; laying a second set of conductors on the second adhesive layer perpendicular 5 to the second edge; and using an ultrasonic bonder to bond ends of the conductors of the second set to the second printed circuit board.

   54. A method of manufacturing a transducer for use is a digitiser, the method

   10 comprising:

   applying a first conductive strip to an insulating substrate along a Y-direction; arranging one or more conductors over the insulating substrate that extend along an X-direction and that electrically connect at one end to the first conductive strip;

   15 applying a second conductive strip to the insulating substrate along the X-

   direction;

   arranging one or more conductors over the insulating substrate that extend along the Y-direction and that electrically connect at one end to the second conductive strip; and

   20 cutting, etching or otherwise breaking the first and second conductive strips to form separate conductive pads to allow connection of the conductors to electronics of the digitiser.

   25

   Amendments to the claims have been made as follows:

   96

   Claims:

   1. A method of manufacturing a transducer for use is a digitiser, the method 5 comprising:

   applying a first conductive strip to an insulating substrate along a Y-direction;

   arranging one or more conductors over the insulating substrate that extend along an X-direction and that electrically connect at one end to the first conductive strip;

   10 applying a second conductive strip to the insulating substrate along the X-

   direction;

   arranging one or more conductors over the insulating substrate that extend along the Y-direction and that electrically connect at one end to the second conductive strip; and

   15 cutting, etching or otherwise breaking the first and second conductive strips to form separate conductive pads to allow connection of the conductors to electronics of the digitiser.

   20

   •.'????.• INTELLECTUAL

   *.*. .V PROPERTY OFFICE

   97

   Application No: GB1208319.2 Examiner: Dr Russell Maurice

   Claims searched: 1 Date of search: 20 September 2012

   Patents Act 1977: Search Report under Section 17

   Documents considered to be relevant:

   Category

   Relevant to claims

   Identity of document and passage or figure of particular relevance

   A

   -

   EP 0034976 A1

   (TELEDIFFUSION FSE) see e.g. the abstract

   A

   -

   US 2011/279408 A1

   (PANASONIC CORP) see e.g. the abstract

   A

   -

   'Analog Data Tablet', Hevesi; JF, IP.COM Journal, ISSN 1533-0001

   Categories:

   X

   Document indicating lack of novelty or inventive

   A

   Document indicating technological background and/or state

   step

   of the art.

   Y

   Document indicating lack of inventive step if

   P

   Document published on or after the declared priority date but

   combined with one or more other documents of

   before the filing date of this invention.

   same category.

   &

   Member of the same patent family

   E

   Patent document published on or after, but with priority date

   earlier than, the filing date of this application.

   Field of Search:

   Search of GB, EP, WO & US patent documents classified in the following areas of the UKC :

   International Classification:

   Subclass

   Subgroup

   Valid From

   G06F

   0003/047

   01/01/2006

   G06F

   0003/041

   01/01/2006

   G06F

   0003/044

   01/01/2006

   Intellectual Property Office is an operating name of the Patent Office www.ipo.gov.uk