GB2498946A

GB2498946A - Fast start-up circuit for phase locked loop (PLL)

Info

Publication number: GB2498946A
Application number: GB201201606A
Authority: GB
Inventors: Joaquim Machado; Peter Hunt
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 2012-01-31
Filing date: 2012-01-31
Publication date: 2013-08-07
Also published as: GB201201606D0

Abstract

An improved phase locked loop circuit is provided that has a conventional primary feedback loop comprising a feedback divider circuit for enabling multiplication of a reference frequency to the output frequency. The circuit further includes a secondary control loop for monitoring a voltage control signal at the charge pump / loop filter and, from this signal, generating a digital control word for regulating the frequency of the voltage controlled oscillator (VCO). This arrangement provides a fast automatic calibration method for a low Kv, digitally trimable VCO based PLL, by using the analogue loop control voltage to control the automatic calibration logic. The effect is to reduce the calibration time from >lms to <10ps.

Description

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FAST STARTUP CIRCUIT FOR PLL

FIELD OF THE INVENTION

The present invention relates to electronic circuits, and more particularly, to phase locked loop circuits and improvements thereto for providing a fast startup.

BACKGROUND OF THE INVENTION

Phase locked loop (PLL) circuits are commonly used to synchronize an output clock signal with an input reference signal. The lock time of a PLL circuit is the duration between the time when the PLL receives all input and control signals and the time when the output clock signal is locked into phase with the input reference signal. Typical PLL circuits may exhibit lock times having durations that are unsuitable for specific applications.

The present invention mitigates against the long startup times required to calibrate certain circuits contained in certain PLL topologies. The circuits used in PLLs have certain parameters such as currents or frequency for example, that need to be adjusted because of variations in the environmental conditions in which they are used, such as pressure, voltage, temperature PVT, and to enable the PLL to operate quickly and efficiently.

SUMMARY OF THE INVENTION

According to the present invention there is provided a control circuit for an improved PLL performance, as well as an improved PLL that comprises a secondary loop that works in conjunction with a primary loop of the PLL in order to achieve lock in a considerably faster time than with conventional PLL.

According to a first aspect of the invention there is provided control circuit comprising: a comparator circuit having

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an output and a plurality of inputs; and a digital control circuit having an output couplable to a VCO and an input coupled to the output of the comparator circuit, said digital control circuit operable to provide a digital control word to the VCO on the basis of a signal received from the output of the comparator circuit; the comparator circuit having a first input for receiving a voltage control signal from a loop filter circuit for regulating the frequency of the VCO, a second input for receiving a first reference voltage, and a third input for receiving a second reference voltage, and wherein the comparator circuit is adapted to compare the voltage control signal with the first and second reference voltages, and to generate: a down signal if the voltage control signal is greater than the first reference voltage, an up signal if the voltage control signal is less than the second reference voltage, both an up signal and a down signal if the voltage control signal lies between the first reference voltage and the second reference voltage.

Preferably, the control circuit has a potential divider circuit for generating the first and second reference voltages provided to the second and third inputs, respectively, of the comparator circuit.

A second aspect provides an improved phase locked loop PLL circuit comprising: a primary feedback loop comprising a feedback divider circuit for enabling multiplication of a reference frequency to the output frequency; a secondary control loop for monitoring a voltage control signal and generating a digital control word for regulating the frequency of a voltage controlled oscillator, said secondary control loop comprising a digital control circuit according to the first aspect.

The invention advantageously provides a fast automatic calibration method for a low Kv digital trimable VCO base PLL, by using the analogue loop control voltage to control the automatic calibration logic thereby reducing the calibration time from >lms to <10]js.

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An advantage of the invention is that it allows the correct setting to be determined for certain parameters (for example, current or frequency) that need to be adjusted differently according to environmental conditions (pressure, voltage, temperature, PVT) in a quick and efficient manner with minimum complexity.

Examples of the invention will now be described, with reference to the accompanying drawings, of which:

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a block diagram of a typical phase locked loop (PLL) circuit;

Figure 2 is a block diagram of an example system, in accordance with the present invention, for providing a fast startup for a PLL circuit;

FIG. 3 is a graph illustrating a operation of the comparator circuitry and analogue response of the digital control loop of the system of FIG. 2; and

FIG. 4 illustrates an example operation of the comparator circuitry of the system of FIG. 2.

DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

FIG. 1 is a block diagram of an example system according to the present invention for reducing the lock time of a PLL circuit. The example PLL circuit includes a phase frequency detector coupled to a charge pump, and a loop filter coupled between the charge pump and a voltage controlled oscillator (VCO) . A feedback divider is coupled between an output of the VCO and an input to the phase frequency detector forming a primary feedback loop.

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The phase frequency detector is operable to detect a phase error between an input reference signal and a feedback clock signal. The phase frequency detector may, for example, be a linear or non-linear phase detector circuit. The output of the phase frequency detector indicates whether the phase of the feedback clock signal is leading or lagging the phase of the input reference signal. For example, in the case of a non-linear phase frequency detector/charge pump circuit, the phase frequency detector may include an "UP" output to indicate that the feedback clock signal is lagging the input reference signal and a "DOWN" input to indicate that the feedback clock signal is leading the input reference signal.

The loop filter converts the output of the phase frequency detector/charge pump into a control input to the VCO, which instructs the VCO to either increase or decrease the frequency of the output clock signal.

The charge pump converts the output of the phase frequency detector into an analogue signal to control the frequency of the VCO. The output clock signal is fed back to the feedback divider which divides the output clock signal by the divide ratio to generate the feedback clock signal.

Fig 1 shows a standard analogue PLL with a digitally trimable VCO. The VCO has a low KV (Voltage to Frequency control factor) and a very limited tuning range. This is overcome by having a digitally adjustable centre frequency for the analogue loop. A standard method for trimming involves a binary search to find a lock point. This can take a few milliseconds to achieve as each iteration of the search requires you to wait for the full lock time of the PLL.

A preferred embodiment of the invention involves up-ramping the digital trimming through its control codes and observing the control voltage. If you start at one end of the trimming range the analogue control voltage will be at one extreme (either min

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or max) as you the ramp the digital trimming code the control voltage changes from min to max, or max to min, at the correct operating point for the PLL. When the control voltage is close to the middle, the VCO is trimmed to the correct centre frequency and the counter is stopped as shown in Figure 2.

Figure 3 shows a preferred embodiment of the invention. Depending on the control voltage three possible actions can occur. When the control voltage is low the counter counts in one direction and when it is high it counts in the opposite direction. In the region between VL and VU the counter is stopped. The values of VL and VU are provided by a simple resistor divider across the supplies. These references are connected to a pair of comparators to produce an up or down signal to a simple counter. When there is no up or down signal the counter stops. The direction of the count is such that there is negative feedback around the digital loop.

The dead band or voltage between VL and VU indicated on Figures 2 & 3 is to stop the digital loop from jittering by one code. To achieve this there must be at least two frequency steps in the "dead zone". This implies:

(VU-VL) x Kv > 2 x (trimming step size)

The trimming step size is:

Trimming range / Number of steps Kv = Hz/Volts of the VCO tuning

Usually the step is slightly smaller.

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It is important that the analogue bandwidth of the PLL tracks the digital trimming rate of the PLL otherwise the system can become unstable.

The digital trimming rate is:

Step size x Update rate.

Enhancements and variations

Starting the calibration from a centre digital code halve the maximum automatic calibration or start-up time.

After calibration, the counters can be locked to allow restart.

will fast

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Claims

1. A control circuit comprising:

a comparator circuit having an output and a plurality of inputs; and a digital control circuit having an output couplable to a VCO and an input coupled to the output of the comparator circuit, said digital control circuit operable to provide a digital control word to the VCO on the basis of a signal received from the output of the comparator circuit;

the comparator circuit having a first input for receiving a voltage control signal from a loop filter circuit for regulating the frequency of the VCO, a second input for receiving a first reference voltage, and a third input for receiving a second reference voltage, and wherein the comparator circuit is adapted to compare the voltage control signal with the first and second reference voltages, and to generate:

a down signal if the voltage control signal is greater than the first reference voltage,

an up signal if the voltage control signal is less than the second reference voltage,

both an up signal and a down signal if the voltage control signal lies between the first reference voltage and the second reference voltage.

2. A control circuit according to claim 1, wherein the digital control word generated by the digital control circuit is a 10 bit word.

3. A control circuit according to claim 1 or 2, further comprising a potential divider circuit for generating the first and second reference voltages provided to the second and third inputs, respectively, of the comparator circuit.

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4. A control circuit according to any one of claim 1 to 3, wherein the first reference voltage is about 0.6 volts and the second reference voltage is about 0.4 volts

5. An improved phase locked loop PLL circuit comprising:

a primary feedback loop comprising a feedback divider circuit for enabling multiplication of a reference frequency to the output frequency;

a secondary control loop for monitoring a voltage control signal and generating a digital control word for regulating the frequency of a voltage controlled oscillator, said secondary control loop comprising a digital control circuit according to claim 1 or 2.

6. Subject matter of the foregoing description in any novel or inventive combination thereof.

7 The subject matter of the statements of invention characterized by the features recited therein.