GB2498940A - Optimising parameters in a data receiver using data waveform eye height measurements - Google Patents

Abstract

A data receiver comprises a plurality of controllable circuit blocks, each circuit block responsive to a control parameter, and an optimiser 100 to optimise in turn each parameter of the circuit blocks for a period during which the other parameters are held constant. The parameters may include an amount of equalisation applied to an analogue data waveform, a data sampling phase, a sampling reference level and an amount of gain applied to an analogue waveform by an amplifier. The parameter optimisation may be based on measures of an eye height of a data waveform in the receiver. The optimisation process may comprise establishing a plurality of parameter test points having different values, measuring the responses of the receiver (the eye height) in response to the values, comparing the responses and then updating the test points. The process is repeated using the updated test points (see figures 7 and 8).

Description

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EYE HEIGHT BASED AND/OR TWO PARAMETER RECEIVER ADAPTATION

The present invention relates to receiving high speed data signals.

Background

The reception of data at high data rates, for example,

10 Gbs-1 and above, provides, as is known in the art, various challenges. One of these is that the signal level received for a particular bit of the incoming bitstream is dependent on the history of the preceding bits. For example a 1 preceded by a 0 will have a lower level (assuming 1 is represented by a high level) than a 1 preceded by another 1. (This is known as "inter-symbol interference".) Earlier bits than the previous bit also have an influence on the level of the present bit but this influence, while usually smaller than that of the previous bit, is often significant. A future bit (i.e. the next bit to be received after the present one) can also affect the level of the present bit. If the traces of an incoming bitstream data waveform are divided into segments one UI long (UI="unit interval" - the duration of an undistorted one bit pulse), and those segments are overlaid, the well-known "eye diagram" results. Typical examples of such an eye diagram are shown in Figures 1A and IB; the space in the centre free from traces is called the "eye". Figure 1A shows the eye diagram where the previous bit is a 1, in this case the influence of the previous bit is quite strong. The eye of interest 45 is the middle and left one of the three large spaces, The corresponding full eye diagram is Figure IB and includes both the traces of Figure 1A and those for the case where the previous bit is 0, which are those of Figure 1A reflected through the horizontal axis. Thus there are two eyes 45, 46 of interest. () Note that this diagram shows traces extending over a longer period than an interval of 1 UI; in the diagram

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1 UI is 48 of the units marked on the horizontal time axis. (The other markings on the diagram are explained below.)

A typical data receiver known in the art is shown in Figure 2. The incoming signal 10 is received at input terminal 11. For simplicity of illustration this is shown single ended but usually the signal will be a differential one. The signal 10 is first amplified to a level suitable (signal 14) for processing by the rest of the circuit by a variable gain amplifier 12.

The next stage is for the amplified data waveform 17 to be sampled by sampling block 18, a partial equalisation having been applied by an analogue equaliser 15 (described below). The sampling block comprises several samplers 19 in parallel. Each sampler 19 (See Figure 3) comprises a comparator 20 connected to compare the level of the data waveform 17 to a respective reference level 21. The output of each comparator 20 is latched by a latch 22 at a time determined by a local clock signal 23 generated by a common local oscillator 24. The latch has an output making the 1 or 0 valued sample taken available to the rest of the receiver circuit.

In this example, two of the samplers 19 are used to take the data. Sampler 19di is used to take the data when the previous bit is a 1. Its reference level 21di is set to be a level midway up the upper eye 45 (the one shown in Figure 1A and identified above in relation thereto). Sampler 19do is used to take the data when the previous bit is a 0. Its reference level 21do is set to be a level midway up the lower eye 46. In fact both samplers are used to take a sample in each UI interval but a multiplexer 26 is used to select between them on the basis of the value of the preceding bit. The preceding bit is stored in the first bit 21i of shift register 28. The

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output of the multiplexer is the input to the first bit of the shift register and the shift register 28 is shifted one bit each UI, again under the control of the local clock signal 23.

The gain of amplifier 12 is controlled by a gain control signal 13. A gain controller 50 calculates this by inspecting the output of an additional sampler 19gain , which samples the amplified and partially equalised data waveform 17 comparing the level of that waveform to a predefined target reference level Vtarget • If the waveform 17 is above the reference level Vtarget, the test sample will be a 1 and a 0 if the waveform 17 is below Vtarget.These test samples are held in a shift register 29. A particular one of the test samples along the shift register (it does not matter which) is output to the gain controller along with the corresponding data sample that was taken at the same time as the test sample (so in this example the two bits are at the same position along their respective shift registers). That data sample and the furureand previous data samples are also compared to the code 111 by code matcher 51 and whether or not they form the code is indicated to the gain controller. The gain controller only acts in cases where the code 111 is matched. When this occurs the test samples are used to adapt the variable gain amplifier. If the test sample is 1, then the waveform 17 is below the reference level Vtarget so the gain needs to be increased and vice versa. This keeps the 111 trace at the level of the target reference level; the 111 trace is the one that has the highest level and so is a useful measure of the amplitude of the data waveform. The gain is not adjusted at each bit but only from time to time, for example every few thousand samples.

The amplified output signal 14 of the variable gain amplifier 12 is equalised (before sampling) by an analogue equaliser 15.

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In this example the equaliser has a high-pass characteristic with the cut-off frequency being around the highest frequency in the incoming data signal (which is equal to half the data rate) with the gain in the stop band being set by an equalisation control signal 16. While "stop band" is the usual terminology it could be misleading in this case as the objective is not to eliminate those frequencies from the signal but to boost the higher frequencies relative to them, since the higher frequencies will have been attenuated in the transmission line over which the data signal was transmitted. As is known in the art, the analogue equaliser is controlled by a feedback loop based on samples 47 older than those used by the DFE 30 (described below) as is known in the art. Decisions (taken by block 48) based on those samples are used to adjust the equalisation control signal. Again the gain is only adjusted from time to time.

Figure 4 is a circuit diagram of an equivalent circuit for the analogue equaliser 15. This is a simple RC filter that has a capacitor connected between its input 60 and its output 61 and a resistor 65 is connected between the output and ground 64. A variable resistor 63 connected in parallel with the capacitor has its resistance controlled by the equalisation control signal 16 so when its resistance is high the gain in the stop band is low and when its resistance is low the gain in the stop band is higher. This equaliser only partially reverses the effects of the channel along which the data waveform was transmitted (a DFE described below also provides some equalisation).

The local oscillator 24 is a variable oscillator and is controlled by a clock recovery circuit 25, which adjusts the frequency and phase of the local clock signal 23. Many techniques are known in the art for keeping the local clock

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signal synchronised with the data waveform. Some of these techniques work off the analogue data waveform 17 such as in a phase locked loop, while others utilise digital samples 52 of the waveform taken by the data samplers (and/or by additional samplers) .

This clock recovery circuit 25 operates to provide a timing point for the sampling of the data that is near the centre of the eye since at that point the traces for which the current bit is a 1 or 0 pass respectively above and below the eye.

In this example the content of the shift register 28 is also used by a decision feedback equaliser DFE 30. This uses the recently taken bits to set the reference levels 21diand 21do of the data samplers 19di and 19do. In a sense the multiplexer 26, being responsive to the most recent bit 27i, is part of this equalisation process because it provides a gross adjustment of the data sampling reference level by choosing between the two samplers 19do and 19di. The DFE inspects the value of each of the recent most n samples (in this example n=3 so the DFE inspects 27i, 212 and 213 in the shift register) . In response to that it adds together respective n reference level contributions hi, h2 and h3 that are values of the contributions of those previous bits to the level in the current bit and removes the effect of their interference on the current bit as is known in the art. The contribution levels may for example be predetermined by design or by experimental measurements. Again the DFE only adjusts the reference levels 21di, 21d0 from time to time.

In the above the data and test samples taken are shown as being paralleled up by a shift register. At the highest data rates other methods known in the art may be more appropriate. It remains however that the samples taken are stored and can

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be used for calculations, which even if lengthy to perform on a UI timescale, can be used to make adjustments which are fed back many UI later.

The present invention relates to optimisation in data receivers of the parameters used to adapt blocks having parameters that can be optimised during operation either in an initial phase or continually during subsequent periods. Examples of those blocks controlled in examples of the invention below are: the gain applied to the incoming data signal with an amplifier, the relative gain between pass and stop bands in an analogue equaliser and the timing of the sampling. (In the description above of a typical receiver circuit these items have been selected for detailed discussion for the reason of convenience of illustrating the invention.) The approach to optimising these different parts of the receiver circuit has been in the prior art to give the feedback controlling the loop for each block a significantly different time constant. That is to keep those loops fairly independent in that the fastest loop will adjust first and then if changes are made by a slower loop the fastest loop can then re-optimise quickly to the new state of the circuit.

However the inventors have noticed that undesirable interaction between the loops occur nonetheless, in particular between the gain applied to the incoming data signal with an amplifier, the relative gain between pass and stop bands in an analogue equaliser and the timing of the sampling.

Summary of the Invention

The invention provides an alternative approach to optimising two or more circuit blocks in a data receiver to recover the loop interaction effect and to provide a more stable system. In a second aspect of the invention a new particular

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measurement is proposed as being a figure of merit that is to be used to optimise one or more parameters of one or more circuit blocks in a receiver.

According to the present invention there are provided methods of optimisation and receiver circuits as claimed in the appended claims.

Brief description of the drawings

Examples of the invention will now be described, with reference to the accompanying drawings, of which:

FIGURES 1A and IB are graphs each showing superposed traces of segments of a data waveform,

FIGURE 2 is a block diagram of a typical data waveform receiver circuit known in the art,

FIGURE 3 is a block diagram of a data sampler used in the circuit of Figure 2,

FIGURE 4 is an equivalent circuit of an analogue equaliser used in the circuit of Figure 2,

FIGURE 5 is a block diagram of a data waveform receiver circuit in accordance with the invention,

FIGURE 6 is an example of an optimisation method for two parameters in accordance with the invention,

FIGURE 7 is an example of an optimisation method in accordance with the invention for a single parameter,

FIGURE 8 illustrates the parameter test points, and FIGURE 9 is an example of a method measuring eye height.

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Examples

Figure 5 is a block diagram of an example of a circuit according to the invention. Generally this example is similar to the receiver circuit described above with reference to Figures 2 to 4, with similar reference numerals being used for similar parts. However in this example the feedback loops for the timing of the sampling and the analogue equaliser are not arranged to operate separately at the same time (although with different time constants) as in the circuit of Figures 2 to 4 but the feedback adjustment of the parameters of those two is controlled by a common optimisation control block 100 according to the method of the present invention.

Before this operation is explained in detail, a preferred form of the feedback for setting the phase of the oscillator 23 relative to the incoming data waveform used in this example is described. A similar method is described in our copending application 1106360, which is incorporated herein by reference. For this further samplers 19ti and 19to are provided, clocked to sample the data waveform at the same time as data samplers 19di and 19do (described below), however their reference levels 21ti and 21to are set to be respectively the level of the trace for the previous, current and future bits being 100 at the point where that trace is near the centre of the eye (see Figure IB) and minus that level to the other side of 0V (which level is that of the 011 near the centre of the eye). The values taken by these timing samplers are collected in respective shift registers 34 and 35. Code matchers 36 and 37 respectively test three consecutive bits in data shift register 28 (which three is not important) for the occurrence of codes 100 and 011. Responsive to one of those being found, clock recovery circuit 25' checks the collected test bit from the appropriate shift register 34 or 35 respectively that was sampled at the same time as the middle bit of those codes .

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For the 100 code: if the sample from 19t± is a 1 then it adjusts the phase of the local clock signal 23 to be later in subsequent unit intervals, and if is a 0 then it adjusts the phase of the local clock signal 23 to be earlier in subsequent unit intervals by a small fraction say 1/8 of a phase step (there being 48 phase steps in 1 UI in this example). A similar kind of adjustment is made for the Oil case using 19t0 . This timing loop follows jitter in the incoming data waveform so that the data is sampled in generally the same position across the eye each time. The reference level 21ti is variable (21to equally) and the optimiser 100 makes use of this, as is explained further below, using the effect that since the 100 trace has a downward gradient near the centre of the eye raising its level moves the sampling point earlier in the eye and lowering its level moves the sampling point later in the eye.

Returning to the operation of the optimisation block 100, in this example a different (compare the circuit of Figure 2) figure of merit is employed to determine whether and how adjustment is made. In this example, measurements of eye height, to be described further below, are used as the basis of adjustment of each of the timing of the sampling within the eye and the amount of equalisation provided by the analogue equaliser. It is to be noted however that the optimisation method of the invention could in general work off measurements different from eye height, and it is not essential for the same figure of merit to be used for optimisation of the two blocks. Further, the invention extends to optimising three or more blocks.

Figure 6 is a block diagram of the method performed by the optimiser block 100 in the example of Figure 5. In an outer loop of the method the optimiser 100 alternates between

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optimising the timing of the sampling 101 and optimising the analogue equaliser 103When a parameter has been optimised for a period its optimised value (in particular the "centre point" around around which it has been adapting in the single parameter optimisation in the method described below) iis output (steps 102 and 104) to the circuit and remains constant while the other parameter is optimised. Although changing one parameter may change the optimal value of the other, the alternating optimisations of the two parameters should move both to a place where both are optimised and stable (unless of course some other factor changes in which case the parameters will move again to a new optimal position).

During each period the optimiser follows the same method, although, of course, the parameter adjusted and output by the method is different, namely for the sampling timing adjustment the parameter is the reference level of the timing sampler and for the analogue equaliser it is the resistance of its variable resistor.

The method used for adjusting a parameter is shown in Figure 7 and is as follows. First 61 two test points (illustrated in Figure 8) for the parameter are established; these are the current value ("centre point value") of the parameter, plus and minus a constant delta value A. This delta is configurable and needs to be large enough to be able to detect a gradient in the adaptation curve for that parameter (i.e. the curve of eye height against the parameter) but also small enough so as not to cause large oscillations about the centre point.

In the next step 62 the value of the parameter output by the optimiser 100 to the receiver circuit is changed (step 62) to one of the test points and the eye height is measured (step 63). If the parameter being optimised is equalisation then the

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optimiser outputs it to register 70, which supplies in response its value as the equalisation control signal 16'. If the parameter being optimised is the sample timing within the eye then the optimiser outputs it to register 71, which supplies in response its value as the timing sampling reference levels 21tl and 21to, which as noted above control the point in time within the eye at which the samples are taken.

The method for determining the eye height is shown in Figure 9 and is as follows. First (step 91) two eye height test points are established; these are 74 and 75 in Figure 1A. These have the same timing as the data sampling point (for simplicity only one the two eyes mentioned above has its height measured) but have reference levels plus or minus a delta 5 above and below the data sampling point. (Note while it is preferred that the eye height test points have the same timing as the data samplers they could be offset in phase therefrom.) Figure 1(a) shows the position of the test points 74 and 75 well before they have reached the traces at the edge of the eye, which is only during an initial phase. 76 is the data sampling point (for where the previous bit was a 1). This delta 5 starts from a predetermined value, which may be zero, and is increased (step 92) until the test point reaches the edge of the eye (step 93). That is determined by the value provided by a data sampler for the test point. If that value is the same as the value sampled at the data sampling point the test point is inside the eye, whereas if it is different then the test point is now outside the eye. The circuit of Figure 5 is provided with samplers 19eht and 19ehb to sample the test points, which are provided with the reference levels 21eht and 21 ehb by the optimiser which calculates those from the current delta value 5 (and outputs them with a DAC - not shown).

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In detail, in fact, the eye height measurement is run as a continuous process with the step 63 (and similarly step 65, described below) simply reading the current value of the delta as the eye height (the eye height equals 25 so any multiple will do as a proportional measure). The traces are both noisy and their average position can drift over time. The method allows for that by increasing the delta 5 in relatively small steps while the test point is judged to be within the eye but decreasing it in a relatively large step when the test point is judged to be outside the eye. The smaller the size of the increasing step size relative to the decreasing step size the more accurately the size of the eye will be measured but the longer before it can be certain the edge of the eye has been reached. While that is generally true in the preferred example the size of the large decreasing step is kept constant and the size of the small increasing step is variable. The ratio of the two step sizes determines how far into the noisy edge of the eye the test point penetrates on average. A typical value for the size of the small step is 6 units of a 14 bit register, and a typical frequency of adjustment of delta 5 is once every 32UI (but only when the previous data bit is a 1).

The process of stepping the test point out in small steps and back in a large step does cause the test point to follow a saw tooth pattern. This is not a difficulty for the optimisation method because the delta value is truncated before use, by an amount eliminating that variation. The eye height measurement is continued for a predetermined period of time after which it is fairly certain that the edge of the eye has been found. (Apart from the initial period, this is when the parameter value is changed or when there is a change in the parameter being optimised - setting the predetermined eye height settling period to how long it would take the truncated value for delta to change by a few units is usually suitable. The

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eye-height is not, in this example, reset when the parameter value is changed or when there is a change in the parameter being optimised.)

As noted above, delta 5 is reduced if either of the test points is outside the eye. However, the data sampling point may not be symmetrically between the traces of the eye passing above and below it. More accuracy of eye height measurement can be obtained if the position of the data sampling method is kept symmetrically between the traces of the eye passing above and below it - a method for doing that is also described in our copending application 1106360 . Alternatively the test points can be moved independently towards the edge of the eye, the eye height then being the difference in their positions or the respective deltas being added together. A very simple, but not preferred measurement would have just one eye height test point being moved towards the eye on one side, with the difference in position between that point and the data sampling point 7 6 being taken as a measure of the eye height.

Now, returning to the method of optimisation of one particular parameter, i.e. Figure 7, once the eye height is measured for the first test point the next step 64 is that the parameter output by the optimiser 100 to the receiver circuit is changed to the other of the parameter test points and the eye height is measured again (step 65) .

The eye heights for the two test points are compared and if they are different to each other the centre point for the parameter is incremented 67 in the direction of that which has the larger eye height. (The dotted points in Figure 8 symbolise that step.) The loop then repeats 68 with two new test points offset by the same delta A from the new centre point. In order to guard against possible undesirable large

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oscillation about the optimum point and against responding to noise, the centre point is preferably only incremented a part of the way toward the test point having the larger eye height. A preferred value is 1/16 of the parameter test point delta (A). The fraction is programmable from 1 to 1/128. The smaller this value, the less movement the centre point makes from its optimal point. A typical frequency with which the centre point is updated is once every 224 UI for the parameters discussed.

Note that the value of the centre point can be stored to greater accuracy than is output to the receiver circuit with the size of the centre point increment being smaller than the significance of the least significant bit of the truncated output that goes back to the receiver circuit. This simply filters variations in the parameter value fed back to the receiver circuit.

The above method of optimising one parameter has two test points. The set could include more with the test to decide whether to move them taking them all into account.

This testing loop for one parameter proceeds for a predetermined period of time. Once that is elapsed the parameter value fed back to the receiver circuit is changed from being one of the test points to that of the centre point. The parameter value is held at that centre point value while the other parameter value is optimised.

The testing loop for one parameter may be useful in circuits other than receivers and can measure and be responsive to other measures of circuit performance.

A further block that can be optimised using the invention is the gain control. Further that can be done on the basis of eye

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height also. While one might expect that increasing the gain will lead to increasing the eye height until the gain has reached its maximum what happens in fact is that as the gain nears its maximum the gain of the amplifier 12 becomes less linear and the result of that is in fact reduced eye-height. So optimising the amplifier gain on the basis of eye height leads to a optimal gain value being selected and avoiding any non linear region of the amplifier.

In the above example there are numerous test samplers. In many examples the test samples are not needed every UI, indeed they may be tested much less frequently. Their use can be time divided by changing the reference level supplied to them to one for a different test sampling point. The storage for the samples produced (e.g. 28, 34, 45 can also be time divided, although the circuits using the test sample values will naturally have to keep track of which data is stored where at different times.

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Claims (1)

1. CLAIMS:

   1. A method performed in a data receiver for a data waveform of optimising a plurality of controllable parameters of the circuitry of the receiver, the method comprising:

   optimising in turn each parameter for a period during which each other parameter of the plurality is held constant.

   2. A method as claimed in claim 1 wherein a parameter of the plurality is an amount of equalisation applied to an analogue form of the data waveform in the data receiver.

   3. A method as claimed in claim 1 or claim 2 wherein a parameter of the plurality is the phase of a data sampling relative to the data waveform, or a parameter controlling that.

   4. A method as claimed in claim 3 wherein the parameter is a reference level used to sample the waveform to extract timing information.

   5. A method as claimed in claim 4 wherein the step of extracting the timing information is done in response to a certain series of data bits being received.

   6. A method as claimed in any preceding claim wherein a parameter of the plurality is the amount of gain applied to an analogue form of the data waveform by an amplifier.

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   7. A method as claimed in any preceding claim wherein the step of optimising a parameter of the plurality comprises:

   establishing a plurality of parameter test points having different values for the parameter,

   outputting each parameter test value of the plurality to the receiver circuit and measuring a particular response in the receiver circuit to that parameter test value,

   comparing the particular responses of the receiver circuit to each test parameter value of the plurality, and in response thereto updating the parameter test points by, at least in some cases of the comparison, moving them an amount, and repeating the parameter outputting, measuring and parameter updating steps using the updated test point parameter values.

   8. A method as claimed in claim 7 wherein the plurality of parameter test points is exactly two.

   9. A method as claimed in claim 7 or claim 8 wherein the amount by which the test parameter points of the plurality are moved is less than the difference between the highest and lowest parameter values of the parameter test points.

   10. A method as claimed in any preceding wherein the optimising of at least one parameter is in response to a measure of an eye height of a data waveform in the receiver circuit.

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   11. A method as claimed in claim 10 wherein the eye height is measured by:

   sampling the data waveform at an eye height test point,

   and moving the eye height test point towards the edge of the eye if the eye height test point sample is the same as a data sample from the eye and moving it away if not.

   12. A data receiver for a data waveform comprising:

   a plurality of controllable circuit blocks each responsive to a control parameter,

   and an optimiser operative to optimise in turn each parameter of the plurality of controllable circuit blocks for a period during which each other parameter of the plurality is held constant.

   13. A data receiver as claimed in claim 12 wherein a circuit block of the plurality is an equaliser connected to apply equalisation to the data waveform.

   14. A data receiver as claimed in claim 12 or claim 13 wherein a circuit block of the plurality is a clock recovery circuit operative to adjust the phase of a data sampler connected to sample the data waveform.

   15. A data receiver as claimed in claim 14 wherein the clock recovery circuit comprises a timing sampler connected to provide samples for the clock recovery circuit that has a controllable reference level connected to be controlled by the optimiser.

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   16. A data receiver as claimed in claim 15 wherein the clock recovery circuit comprises a code matcher connected to receive data samples of the data waveform and that is responsive thereto to indicate to the clock recovery circuit that a sample taken by the timing sampler is of a part of the data waveform having that code.

   17. A data receiver as claimed in one of claims 12 to 16 wherein a circuit block of the plurality is an amplifier connected to apply a controllable gain to the data waveform.

   18. A data receiver as claimed in any one of claims 12 to 17 wherein the optimiser is arranged to perform the following steps:

   establishing a plurality of parameter test points having different values for the parameter,

   outputting each parameter test value of the plurality to its controllable circuit block and measuring a particular response in the receiver circuit to that parameter test value,

   comparing the particular responses of the receiver circuit to each test parameter value of the plurality, and in response thereto updating the parameter test points by, at least in some cases of the comparison, moving them an amount, and repeating the parameter outputting, measuring and parameter updating steps using the updated test point parameter values.

   19. A data receiver as claimed in any one of claims 12 to 18 comprising at least one eye height test point sampler connected to sample the data waveform and having a reference input connected to receive an eye height test point reference level from the optimiser.

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   20. A method performed in a data receiver for a data waveform of optimising a controllable parameter of the circuitry of the receiver, the method comprising:

   optimising the parameter in response to a measure of an eye height of a data waveform in the receiver circuit.

   21. A method as claimed in claim 20 wherein the parameter optimised is an amount of equalisation applied to an analogue form of the data waveform in the data receiver.

   22. A method as claimed in claim 20 wherein the parameter optimised is the phase of a data sampling relative to the data waveform, or a parameter controlling that.

   23. A method as claimed in claim 22 wherein the parameter optimised is a reference level used to sample the waveform to extract timing information.

   24. A method as claimed in claim 23 wherein the step of extracting the timing information is done in response to a certain series of data bits being received.

   25. A method as claimed in claim 20 wherein the parameter optimised is the amount of gain applied to an analogue form of the data waveform by an amplifier.

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   26. A method as claimed in any one of claims 20 to 25 wherein the step of optimising the parameter comprises:

   establishing a plurality of parameter test points having different values for the parameter,

   outputting each parameter test value of the plurality to the receiver circuit and measuring a particular response in the receiver circuit to that parameter test value,

   comparing the particular responses of the receiver circuit to each test parameter value of the plurality, and in response thereto updating the parameter test points by, at least in some cases of the comparison, moving them an amount, and repeating the parameter outputting, measuring and parameter updating steps using the updated test point parameter values.

   27. A method as claimed in claim 26 wherein the plurality of parameter test points is exactly two.

   28. A method as claimed in claim 26 or claim 27 wherein the amount by which the test parameter points of the plurality are moved is less than the difference between the highest and lowest parameter values of the parameter test points.

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   29. A data receiver for a data waveform comprising:

   a controllable circuit block responsive to a control parameter,

   at least one eye height test point sampler connected to sample the data waveform and having a reference input connected to receive an eye height test point reference level, and an optimiser connected to supply the eye height test point reference level thereto and to receive eye height test point samples therefrom, and being operative to optimise the control parameter of the controllable circuit block in response to the eye height test points samples.

   30. A data receiver as claimed in claim 29 wherein the controllable circuit block is an equaliser connected to apply equalisation to the data waveform.

   31. A data receiver circuit block is a c the phase of a data waveform.

   as claimed in 29 whe lock recovery circui sampler connected to rein the controllable t operative to adjust sample the data

   32. A data receiver as claimed in claim 31 wherein the clock recovery circuit comprises a timing sampler connected to provide samples for the clock recovery circuit that has a controllable a reference level connected to be controlled by the optimiser.

   33. A data receiver as claimed in claim 32 wherein the clock recovery circuit comprises a code matcher connected to receive data samples of the data waveform and that is responsive thereto to indicate to the clock recovery circuit that a sample taken by the timing sampler is of a part of the data waveform having that code.

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   34. A data receiver as claimed in claim 29 wherein the controllable circuit block is an amplifier connected to apply a controllable gain to the data waveform.

   35. A data receiver as claimed in any one of claims 29 to 34 wherein the optimiser is arranged to perform the followings steps:

   establishing a plurality of parameter test points having different values for the parameter,

   outputting each parameter test value of the plurality to its controllable circuit block and measuring a particular response in the receiver circuit to that parameter test value, comparing the particular response of the receiver circuit to each test parameter value of the plurality, and in response thereto updating the parameter test points by, at least in some cases of the comparison, moving them an amount, and repeating the parameter outputting, measuring and parameter updating steps using the updated test point parameter values.

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   36. A method performed in a circuit of optimising a controllable parameter of the circuit, the method comprising:

   establishing a plurality of parameter test points having different values for the parameter,

   outputting each parameter test value of the plurality to the circuit and measuring a particular response in the circuit to that parameter test value,

   comparing the particular responses of the circuit to each test parameter value of the plurality, and in response thereto updating the parameter test points by, at least in some cases of the comparison, moving them an amount, and repeating the parameter outputting, measuring and parameter updating steps using the updated test point parameter values.

   37. A method as claimed in claim 36 wherein the plurality of parameter test points is exactly two.

   38. A method as claimed in claim 36 or claim 37 wherein the amount by which the test parameter points of the plurality are moved is less than the difference between the highest and lowest parameter values of the parameter test points.

   39. A method as claimed in any one of claims 36 to 38 wherein the method is performed in a data receiver for a data waveform.

   40. A method as claimed in claim 39 wherein the parameter is an amount of equalisation applied to an analogue form of the data waveform in the data receiver.

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   41. A method as claimed in claim 40 wherein the parameter is the phase of a data sampling relative to the data waveform, or a parameter controlling that.

   43. A method as claimed in claim 42 wherein the parameter is a reference level used to sample the waveform to extract timing information.

   44. A method as claimed in claim 40 wherein the step of extracting the timing information is done in response to a certain series of data bits being received.

   47. A method as claimed in claim 42 wherein the parameter is the amount of gain applied to an analogue form of the data waveform by an amplifier.