GB2497606A

GB2497606A - Transmission of multiple audio data streams using pulse length modulation

Info

Publication number: GB2497606A
Application number: GB201207387A
Authority: GB
Inventors: Peter John Frith; John Laurence Pennock; John Paul Lesso
Original assignee: Wolfson Microelectronics PLC
Current assignee: Cirrus Logic International UK Ltd
Priority date: 2011-12-14
Filing date: 2012-04-27
Publication date: 2013-06-19
Anticipated expiration: 2032-04-27
Also published as: GB2561478B; GB201808769D0; WO2013088174A1; GB201207379D0; GB2561477A; GB201121524D0; GB2497566A; GB2561477B; GB2497606B; GB2497605A; GB2561478A; GB201808768D0; GB201207387D0

Abstract

Transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. Audio interface circuitry comprises a pulse length modulator, PLM 103. The PLM 103 is responsive to a plurality of data streams (PDM-R, PDM-L) of audio data samples at a sample rate, to generate a stream of data pulses (MPDM) at the sample rate. The length of each said data pulse is dependent upon on a combination of the then current audio data samples from the plurality of data streams, such as a logical combination. The audio data streams may comprise 1-bit digital data streams corresponding to left and right audio data channels. Preferably, the PLM is responsive to a clock signal having a frequency equal to the sample rate and to a second clock signal having a frequency which is a multiple of the first clock signal. Circuitry for receiving and extracting the data is also disclosed. An interface 104 receives the stream of data pulses (MPDM) and data extraction circuitry 105, 106 determines the pulse length of said data pulse and determines a data value for each of the plurality of audio data streams.

Description

Data Transfer This application relates to methods and apparatus for data transfer, especially to transfer of multiple channels of digital audio data, and in particular to audio data transfer that can use a single communications channel.

In many electronic devices there is a need to transmit audio data signals, or other data signals, within the electronic devices, or to some peripheral or accessory device(s) that may be attached to the electronic devices, for instance a set of headphones. In many modern electronic devices, especially devices with RF transmission capability such as a mobile telephone or computing device, analogue audio signals are liable to be corrupted by electromagnetic interference (EMI) and coupling from other nearby circuitry. It is therefore desirable to transmit signals from an audio processing device, e.g. an integrated circuit audio hub/codec, to the driver of a transducer e.g. speaker, in a digital format so as to preserve the integrity and quality of the audio signal. For audio data there is also typically a requirement to send data for multiple channels, for instance left (L) and right (R) data channels for stereo audio.

Modern electronic devices such as smartphones, tablets and the like typically transmit digital audio data using three data wires plus a ground wire. The signal data for both L/R audio channels is typically sent on one wire in serial format, for example in words of 24 bits, with separate words being sent for the left (L) data channel and the right (R) data channel. The bit clock signal (BCLK) is sent on another wire and a further clock at the left/right words rate (LRCLK) sent on a further wire as illustrated in figure 1.

Alternatively, the audio data may be transmitted as a high-rate 1-bit stream, sometimes referred to as Pulse Density Modulation (PDM). Word-length reduction, noise shaping and/or delta-sigma techniques may be applied to reduce quantisation noise in the audio band at the expense of noise higher frequencies to reduce the required bit rate.

However, this still requires two wires, one for the data and one for the clock. Moreover, the digital data spectrum will include components corresponding to the base band audio signals, which may couple onto other analogue lines. Stereo data may be transmitted along one wire, typically alternating between sending left channel data and right channel data, but the separate clock line is still needed and the spectrum may still present similar problems.

It is therefore an object of the present invention to provide methods and apparatus for data transfer of multiple data channels that at least mitigate some of the aforementioned disadvantages.

Thus according to the present invention there is provided audio interface circuitry comprising: a pulse-length-modulator, responsive to a plurality of data streams of audio data samples at a sample rate, to generate a stream of data pulses at said sample rate; wherein the length of each said data pulse is dependent upon on a combination of the then current audio data samples from said plurality of data streams.

The audio data streams may comprise 1-bit digital audio data streams and may correspond to audio data channels which may be separate channels, such as left and right stereo data channels.

The pulse-length-modulator (PLM) may be responsive to a first clock signal having a frequency equal to said sample rate. The PLM may further be responsive to a second clock signal, the second clock signal having a frequency which is a multiple of the frequency of the first clock signal, which may be at least five times and may be at least eight times the frequency of the first clock signal. The length of each data pulse may be based on a selected number of cycles of the second clock signal.

The minimum data pulse length may be a plurality of cycles of the second clock signal and the maximum data pulse length may be shorter than the period of the first clock signal by a plurality of cycles of the second clock signal.

The PLM may be configured so that at least one combination of input audio data can be encoded as at least two different altemative data pulse lengths. The PLM may vary between said at least two different alternative data pulse lengths, for instance by alternating between said at least two different alternative data pulse lengths or by randomly selecting one of the alternative data pulse lengths. The variation may be arranged to control the average data pulse length for all instances of a given combination of input audio data and this may apply to a plurality of possible combinations of input data.

A plurality of combinations of input data may each be encoded as two different lengths of data pulse, the two lengths being symmetric about a predetermined length. One combination of input data may be encoded as a data pulse having a length substantially equal to said predetermined length.

The PLM may also receive at least one additional data channel and the length of at least some individual data pulses may encode the then current audio data samples from said plurality of data streams and also the then current data sample for said additional data channel. The additional data channel may be a control data channel.

When no data is received on the additional data channel the PLM may vary between pulse lengths that encode the same audio data combination. A series of data pulses with a first reserved sequence may be used prior to encoding any additional data, where the first reserved sequence corresponds to the encoding that would be used for a particular data sequence on the additional data channel and it is not used when no data is available on the additional data channel. When data on the additional channel stops the PLM may encode a second reserved sequence of additional data.

The FLM may comprise a combiner for producing a combined data value from each of said audio data streams and may comprise a counter arranged to count at a frequency of the second clock signal and a comparator for comparing the count value to the combined data value.

The PLM may produce an output which varies between a first non zero voltage and a second non zero voltage.

The rising edges of the data pulses may be separated by a regular time interval equal to the sample period or it may be the falling edges of the data pulses.

The output from the pulse-length-modulator may be connected to an audio signal path on a printed circuit board of a host device or to a connector of a host device, such a socket, and may comprises connections for some or all of audio data-out, audio data-in, power and ground. The power connection may also serve as the audio data-out connection and/or the audio data-in connection may also serve as the audio data-out connection. The connector may be a connector for a headset. In use the PLM may provide audio data and power to a peripheral connected to said connector. The connector could be an optical connector or an RF transmitter.

The audio interface circuitry may comprise bi-directional interface circuitry configured to transmit said data pulses generated by the PLM over a first communications link and receive pulse-length-modulated data pulses via said first communications link. The PLM may be configured to transmit data pulses during a first portion of the sample period and the bi-directional interface circuitry is configured to receive data pulse during a second, different portion of the sample period. The bi-directional interface circuitry may comprise a drive circuit for voltage modulating the communications link based on the data pulses and a read circuit responsive to the resultant voltage on the first communications link, wherein the read circuit is configured to subtract the drive voltage modulation from the resultant voltage signal.

In another aspect of the invention there is provided audio circuitry comprising: an interface configured to receive a serial pulse-length modulated audio data input comprising a series of data pulses at a sample rate; and data extraction circuitry configured to determine the pulse length of said data pulse and to determine a data value for each of a plurality of audio data streams from said pulse length.

Clock recovery circuitry may be configured to recover a first clock signal based on said sample rate. The data extraction circuitry may sample the data pulse at a predetermined number of intervals within the period of the first clock signal to determine the pulse length of the data pulse and may comprise a delay line having a plurality of tap points.

There may be at least a first data extraction module and a second data extraction module, the data extraction modules determining data values for different audio data streams to one another. The first data extraction module may receive the input serial pulse-length modulated audio data from the interface and pass it to the second data extraction module. The first and second data extraction modules may be associated with respective first and second audio transducers.

There may also be power circuitry to derive a power supply from the input serial pulse-length modulated audio data signal. The data extraction circuitry may be powered by such power supply.

Audio transceiver circuitry may comprise audio interface circuitry for sending audio data-out and audio circuitry to receive audio data-in.

Embodiments of the invention may be implemented as an audio system having circuitry configured to transmit audio data for a plurality of audio channels to audio circuitry for receiving the data.

The audio circuitry may be implemented as an integrated circuit and/or in an electronic device. The device may be at least one of: a portable device; a battery powered device; a communication device; a computing device; a personal media player; a music player; a mobile telephone; a docking station for a portable device; a headset; and a hearing aid.

The invention also relates to a method of transmitting audio data comprising, generating a pulse length modulated signal comprising a series of data pulses at a sample rate; wherein the length of each data pulse is dependent upon on a combination of then current audio data samples from said plurality of data streams.

The method may be implemented in any of the embodiments as described above.

In another aspect of the invention there is provided an audio system for transferring audio data for a plurality of audio channels over a single wire connection comprising a pulse-length-modulator configured to produce a series of data pulses at regular intervals wherein the length of each data pulse encodes audio data for each of said plurality of audio channels.

The invention also provides a data transfer system for transferring data for a plurality of separate data channels over a single wire connection comprising a pulse-length-modulator configured to produce a series of data pulses at regular intervals wherein the length of each data pulse encodes data from each of said plurality of audio channels.

In a further aspect of the invention there is provided audio interface circuitry comprising: a pulse-length-modulator responsive to audio data for a plurality of audio channels to generate data pulses at a regular time interval; wherein the length of the data pulses encode said audio data; and wherein the length of an individual data pulse encodes audio data for said plurality of audio channels.

The invention also provides an audio interface for receiving and encoding a plurality of streams of 1-bit audio data samples and for transmitting a stream of encoded data pulses via a single communication link." In a further aspect there is provided an audio interface for receiving and encoding a plurality of streams of 1-bit audio data samples and simultaneously transmitting on a clock edge of a stream of encoded data pulses a plurality of sampled 1-bit audio data samples via a single communication link.

The invention will now be described by way of example only with reference to the following drawings, of which: Figure 1 illustrates a prior art three-wire data transfer protocol for stereo audio data; Figure 2 illustrates a data transfer system according to an embodiment of the present invention; Figure 3 illustrates example data waveforms on the various signal lines of the embodiment illustrated in Figure 2; Figure 4 illustrates one embodiment of a suitable audio transmitter; Figure 5 illustrates example waveforms on the various signal lines of the transmitter embodiment illustrated in Figure 4; Figure 6 illustrates one embodiment of a suitable audio data receiver; Figure 7 illustrates example waveforms on the various signal lines of the receiver embodiment illustrated in Figure 6; Figure 8 illustrates one example of an encoding scheme which allows data input combinations to have alternative possible encodings; Figure 9 illustrates a data transfer system according to another embodiment of the present invention; Figure 10 illustrates another example of an encoding scheme; Figure 11 illustrates an embodiment of interface circuitry for sending pulse-length-modulated data over a single data link; Figure 12 illustrates the waveforms on the various signal lines illustrated in Figure 11; Figure 13 illustrates another embodiment of interface circuitry for sending pulse-length-modulated data over a single data link; Figure 14 illustrates an application of an embodiment of the invention; Figure 15 illustrates an application of another embodiment of the invention; Figure 16 illustrates an application of a further embodiment of the invention; Figure 17 illustrates an application of another embodiment of the invention; Figure 18 illustrates an application of a yet further embodiment of the invention; Figure 19 illustrates an application of a further embodiment of the invention; Figure 21 illustrates an application of another embodiment of the invention; Figure 22 illustrates various consumers and generators of data in a device and a connected accessory apparatus; Figure 23 illustrates a first embodiment of the invention for transferring data in the arrangement shown in Figure 22; Figure 24 illustrates a second embodiment of the invention for transferring data in the arrangement shown in Figure 22; Figure 25 illustrates an electronic device with various connections for accessory apparatuses; and Figure 26 illustrates various connections between internal and external systems of an electronic device.

Figure 2 illustrates an embodiment of a data transfer system for transferring multiple simultaneous channels of data over a single link. In this example stereo audio data is transferred over a single wire, i.e. conductive path 111, between a first component 101 and a second component 102. The first component 101 may be audio interface circuitry that is incorporated as part of an audio codec or a digital signal processor of a host device for example. The second component 102 may be audio interface circuitry, for example as part of transducer driving circuitry. The second component 102 may be part of the same host device as the first component 101 and thus the link 111 may comprise a trace on a PCB of the host device or other permanent wired connection.

Alternatively the second component 102 could be part of a separate device to the first component 101. Forexample the first component 101 could be located in a media player or mobile telephone or the like and the second component 102 could be part of a second device, for example a peripheral or accessory device, that is coupled in use such as a headset or docking station or the like. In this case the link 111 may comprise a conductive path involving a suitable connection (not shown) such as a plug and socket. In further embodiments the first and second components may both be implemented on the same integrated circuit, and the link is an on-chip connection, to reduce the width of interconnect bussing between blocks. Various applications of the embodiments of the present invention will be described in more detail later.

The audio interface circuitry of the first component 101 has a pulse-length-modulator (PLM) 103 which receives audio data input data, PDM-R and FDM-L, for the left and right audio channels. In this example the L/R input data are separate 1-bit (i.e. PDM) digital input data streams for each channel, i.e. left channel and right channel. At regular intervals, for instance in each period of a first clock signal CK (which preferably matches the sample rate of the LIR 1-bit audio data input) the FLM generates a data pulse with a length that depends on the logical combination of [JR input audio data.

For left and right 1-bit audio data inputs there are four possible combinations of input data and the PLM 103 generates a data pulse having a length (i.e. duration) which varies according to the output of the particular L/R input data combination, as illustrated

in table 1 below.

PDM-L Value PDR-R Value PDM Combined Pulse length (TFCK) value 0 0 00 1 0 1 01 2 1 0 10 3 1 1 11 4

Table 1

The pulse length is preferably determined as a multiple of a clock period of a second clock signal, FCK, which has a frequency which is a multiple of the first clock signal CK. It will be clear that the frequency of the second clock signal FCK should be at least four times the frequency of the first clock signal CK and is preferably at least five times the frequency of the first clock signal to allow for a pulse length of 4TFCK within each period of the first clock signal and also allow a gap between pulses to ease downstream clock recovery.

Figure 3 illustrates the first clock signal CK and second clock signal FCK, which in this example has a frequency five times that of the first clock signal CK. Figure 3 also illustrates that in each period of the first clock signal CK the right and left input data streams FDM-L and PDM-R will each have a data value of 1 or 0 depending on their respective current data i.e. logic levels. The resulting PLM data signal (MPDM), generated to represent a logical combination of [JR input audio data as per table 1, is also illustrated. This comprises a series of data pulses, at the frequency of the first clock signal OK, where the length of each individual data pulse encodes a data value for the left audio channel and also a data value for the right audio channel.

It will be noted that there is always one data pulse per period of the first clock signal CK and that the data pulses are arranged so that there is always a gap between data pulses. This means that the PLM data signal (MPDM) can itself be used to recover the first clock signal CK by the receiving interface circuitry. In the example shown, the rising edges of the clock signal are separated by the clock period but the skilled person will appreciate that the falling edges could instead be synchronised to the first clock signal CK.

Referring back to Figure 2 the output from the P[M 103 is transmitted as data signal MPDM to the second component 102. The audio interface circuitry of the second component 102 has an interface 104 for receiving the data signal. In this example the interface 104 comprises a two way divider that allows copies of the data signal MPDM to reach a first data extraction module 105 and a second data extraction module 106.

The first data extraction module 105 extracts the first clock signal from the data signal.

As mentioned above the period between the rising (or alternatively the falling) edge of each data pulse indicates the first clock period. The first data extraction module 105 then determines the length of each data pulse and uses this to determine the audio data for the left audio channel. From table 1 above it can be seen that pulse lengths of 1 012 times the second clock signal FCK indicate a data value of 0 for the left channel and pulse lengths of 3 or 4 times the second clock signal FCK indicate data 1 for the left audio channel. Given that the second clock signal is a known multiple of the first clock signal frequency the relevant length of the data pulse can therefore be determined. Likewise the second data extraction module 106 determines the first clock signal and also determines the length of the data pulse to determine the data value for the right audio data channel. In this instance a pulse length of 1 or 3 times the second clock signal indicates a data value of zero for the right channel and a pulse length of 2 or4 indicates a data value of 1.

Each of the first and second data extraction modules therefore outputs a version of the first clock signal CK and a digital data signal for the relevant audio channel. The digital data signals may, for instance by a 1-bit PDM signal nut it will be appreciated that other formats are possible. These signals can be passed to respective DAC-amplifiers 107, 108 to drive respective loudspeakers 109 and 110.

The PLM 103 is therefore a PLM encoder for receiving data and producing a PLM data signal encoding such data. The data extraction modules 105 and 106 are PLM decoders which receive the PLM data signal and decode the signal.

Figure 2 shows separate data extraction modules 105, 106 for each channel, associated with the relevant DAC-amplifier 107, 108 and speaker 109, 110 for each channel. In a device having internal stereo speakers the speakers may typically be separated and arranged to receive signals from an audio source such as codec and thus the arrangement shown in Figure 2 may be preferred. In this case the data extraction module for each channel 105, 106 may be integrated with the respective DAC-amplifler 107, 108 for that channel. In other arrangements however, instead of separate data extraction modules for each channel a single data extraction module could be used to extract the data for more than one channel.

Figure 3 illustrates that the data signals PDM-RX and PDM-LX, respectively extracted by the first and second data extraction modules 105, 106, are the same as the respective input data PDM-R and PDM-L.

This embodiment of the present invention therefore supplies simultaneous audio data for multiple audio channels using only a single communication link, i.e. a single data wire, without requiring any clock signals to be sent.

Figure 4 illustrates one example of a suitable pulse-length-modulator (PLM) 103, i.e. a PLM encoder, that may be used as part of an audio interface. As illustrated the PLM has a combiner 401 that receives the two input 1-bit data streams, PDM-L and FDM-R.

The combiner 401 converts the input data to a 2-bit combined data stream PDM-C (as described above in relation to table 1). A counter 402 is also arranged to receive the first and second clock signals CK and FCK respectively. The second clock signal FCK is arranged to clock the counter to increment and the first clock signal is provided at the reset input. Thus each period of the first clock signal the counter will increment at the rate of the second clock signal. The output is thus is a sawtooth ramp waveform that is reset to zero at the start of each period of the first clock signal (or alternatively the counter could be arranged to count down from a certain starting level each period).

The output of the combiner 401 and counter 402 is compared by comparator 403 which is clocked at the second clock frequency FCK, and is configured to give a high output if RAMP is greater than the combined signal PDM-C. At the first relevant (e.g. rising) clock edge of FCK after the counter has reset, the RAMP signal will be zero, and the combined signal will be zero or greater, so the output of the comparator goes high at the beginning of the first relevant edge of ECK in each period of the first clock signal. At successive FCK edges, the RAMP signal will have increased: the comparator output goes low when the ramp signal has exceeded the combined data value. This results in a data pulse where the rising edge is synchronised to the first clock signal (i.e. the rising edge of each data pulse occurs at the first relevant FCK edge after the rising edge of the CK clock signal) and the pulse length depends on the combined data value. It will of course be appreciated that the comparator could be arranged so that the output goes low at the start of the clock period and goes high only as a result of the comparison to synchronise the falling edges of the data pulses.

Figure 5 illustrates the various data waveforms and shows how the comparison of the combined data value PDM-C with the ramp signal can generate the pulse-length modulated data signal (MPDM).

It should be noted that the PLM described with reference to Figure 4 acts on 1-bit PDM input data streams. In some embodiments there may be a need to convert an audio data stream for an audio channel into a 1-bit PDM data stream before it is input to the PLM. For example if input analogue audio data from a microphone or other analogue source is received there may be a need to convert it to a 1-bit PDM digital data stream.

Alternatively if audio data is received or stored in multi-bit PCM format there may be need to convert the audio data words into a 1-bit PDM stream using known conversion techniques. Thus referring to figure 2 first component 101 may comprise conversion circuitry (not shown) for converting an input audio stream into a 1-bit PDM stream which is then provided to the PLM 103.

However in some embodiments the PLM may be arranged to receive multi-bit input data for one or more audio data channels. For example consider left and right stereo data where each channel comprises two-bit digital audio data. This means that each clock period there may sixteen possible combinations of audio data. If the second clock signal is arranged to have a frequency which is at least seventeen times that of the first clock signal the sixteen possible combinations may therefore be encoded by sixteen different pulse lengths. The principle of operation is the same, for example a four-bit combined data signal representing the state of both input channels may be produced and compared to a counter ramp that increments at the rate of the second clock signal. Clearly this could be extended to digital signals of higher numbers of bits but with a consequent increase in the number of different pulse lengths required and a corresponding increase in the speed of the second clock signal compared to the first clock signal, which may require very fast components and accurate resolution between relatively small differences in pulse length. Another example is 3-level data as used for control of Class-D H-bridge output stages, requiring nine possible pulse lengths for a stereo pair.

Other techniques for pulse length modulation in general, for example using delay-locked loops (DLL) are known and could be adapted for use in embodiments. Also it should also be noted that the first and second clock signals could be received by the PLM 103 or one or both of these signals may be generated by the PLM. For instance the PLM may receive the first clock signal, for example as a clock accompanying and synchronous to the PDM data and generate the second clock signal or the PLM may receive no clock signals and may recover the first clock signal from the input data using known clock recovery techniques.

Figure 6 illustrates one embodiment of suitable data extraction module 105 or 106, i.e. a PLM decoder. In this embodiment, the clock signal is recovered using a Delay-Locked-Loop (DLL) comprising a voltage-controlled delay line 601, itself comprising a chain of voltage-controlled delay elements 602, together with a phase-frequency detector (PFD) 603, charge pump 604 and loop filter 605 as known. The DLL receives the MPDM signal and the PFD 603 is designed suitably so that each rising edge of delay line output SYNC is locked to a rising edge of the incoming MPDM stream. Thus the delay along the delay line becomes equal to a period of the original CK clock.

The duty cycle of SYNC will vary with the data carried on MPDM. To establish a clock with 50% duty cycle, SYNC is applied to the set input S of an edge-triggered RS flip-flop 606, while a signal y5 from half way along the delay line is applied to the reset input.

To extract a measure, PL, of the length of each transmitted PLM data pulse (i.e. each pulse of data signal MPDM), the data at a number of equally spaced taps of the delay line 601 is summed in a summer 607. The delay taps are arranged to sample the signal at intervals equal to the second clock frequency FCK and in sufficient number to be able to discriminate between the number of different possible pulse lengths. In this embodiment, where the second clock frequency is known to be five times the frequency of the first clock signal and there are four possible different pulse lengths, there are five delay taps at equal spacings along the delay line.

The determined data pulse length value FL is then applied to a look-up table 608 or equivalent logic to decode the MPDM signal in the relevant PDM audio data channel or channels. In the embodiment illustrated in Figure 2, where there is a different data extraction module for each data channel, respective logic inputs LR are tied to ground or VDD to signify left or right channel. This signal LR representing whether PDM-L or PDM-R is to be extracted may also be applied to the look-up table to determine the appropriate data value. Alternatively a multiplexer between the MSB and LSB of the two bit PL data value, driven by LR, may be used to select the appropriate data output.

In other embodiments, especially with more than two receiving channels, alternative methods of identifying each receiver may be implemented and used to extract appropriate data using suitably adapted truth tables.

The look-up table contains a truth table such as shown in table 2 below.

PL LR PDM-L PDM-R

00 0 -0 01 0 -1 0 -0 11 0 -1 00 1 0 - 01 1 0 - 1 1 - 11 1 1 -

Table 2

It will be appreciated however that in other embodiments a single data extraction module may be used to extract both the PDM-R and PDM-L together.

It will be noted that this detection method does not require explicit recovery of the second clock signal FCK (or any clock signal faster than the fist clock signal). However if this is required, for instance for other circuitry, such a clock may be generated by logical combination of the tapped outputs yl toy9 as known. The recovered first or second clocks may be used for other functions in the device. Indeed the rising (or even both) edges of the unprocessed MPDM signal may be used as a clock edge.

Figure 7 illustrates the MPDM input signal that would be received for the various possible data combinations, how the first clock signal CKX can be recovered and how the output of the delay tap y5 can set a 50:50 duty cycle for the clock signal. These waveforms also shows how the outputs of the delay taps yl to y9, when summed, provide an indication of the length of the data pulse which can then be used to extract the PDM-R and PDM-L audio data streams.

In correct operation, the sampled output of the first delay tap yl is always 0 and the sampled output of the last delay tap y9 is always 1. This can be used to generate a flag indicating correct operation i.e. lock of the DLL loop and correctly formatted input data.

In this case it can then be noted that the value of PL only varies due to the contribution of delay taps (y3, y5 and y7}. If the value PL were produced by summing just the output of these three delay taps then the values of PDM-L and/or PDM-R can then be selected merely as the MSB and LSB bits of PL, as illustrated in Table 2.

The embodiments described above relate to two channels of audio data, e.g. left and right stereo data. However it will be appreciated that the principle can be extended to more channels of audio data, for example for surround sound. For example if there were four channels of audio data, left-front, left-rear, right-front, right-rear and each data channel was a 1-bit PDM data stream then the combined data would comprise a 4-bit data signal which could be encoded by 16 different pulse lengths.

In the embodiments described above the number of possible pulse lengths that can be produced by the pulse-length-modulator has been set to simply provide unique encoding for each possible input data combination, i.e. the period of the first clock signal has been divided into an equal number of time slots sufficient to allow unique encoding. However in some embodiments of the invention the number of possible time slots may be greater than is required just for unique coding of the audio data channels.

These extra slots can be used to provide a number of additional features and advantages.

In one embodiment the PLM may be arranged so that at least one combination of input audio data for the left and right audio channels can be encoded as at least two different alternative data pulse lengths. In other words a particular combined data value, say 10, may be encoded as a first pulse length or alternatively as a second, different, pulse length.

Varying the pulse lengths can help reduce problems with EMI by effectively whitening the data signal spectrum. Thus the PLM may be arranged to use the first pulse length to encode one instance of the combined data value and the second pulse length to encode a later instance of the same combined data value. In other words the PLM may vary between the two different alternative data pulse lengths when encoding a given combination of input audio data. In one embodiment the PLM may simply alternate between the possible different encodings but in other embodiment the PLM may be arranged to select between the alternative encodings at random.

In one embodiment the PLM is arranged to vary between the possible encoding pulse lengths so as to control the average pulse length of all instances of a particular combination of input data.

Advantageously for any possible combined data values that have alternative possible encodings the possible encodings may be symmetric about a given pulse length.

Figure 8 illustrates a period of the first clock signal which is divided into eight separate time slots, i.e. the frequency of the second clock signal is set to be eight times that of the first clock signal so that there are seven possible pulse lengths (it will be recalled that a pulse length using all eight time slots is not used to ensure a gap between data pulses, to allow simple clock recovery using the rising edge thus available at each first clock period). The input data combination 11 (i.e. data 1 on the left channel and data 1 on the right channel) may be encoded as a pulse length of four time slots (illustrated as position 3). This encoding may be the only option for an input data combination 11. All the other possible input data combination values, 10,01 and 00 however may each be encoded as two possible pulse lengths. In each instance, as illustrated, the pulse lengths may be symmetric about a given pulse length. Thus input combination 00 may be encoded as a pulse of one time slot in length (position 0) or 7 times slots in length (position 6).

In this example the various alternative pulse lengths are symmetric about a pulse length that is half the interval between pulses (which may give advantages for DC balance in some implementations). However this does not need to be the case and where there more time slots available any desired pulse length may be chosen that has sufficient time slots on either side.

The truth table that the PLM uses to encode the input data to pulse length may therefore be based on that set out in table 3 below.

Left data Right Data R value position o 0 0 0 o 1 0 1 1 0 0 2 1 1 0 3 o o 1 6 o 1 1 5 1 0 1 4 1 1 1 3

Table 3

The R value is used to control which alternative encoding is used for those input data combinations which have alternative encodings. If a respective R value is simply alternated between successive occurrences of each input code pair, the average pulse length will be constant, irrespective of the input data.

It may be good enough merely to alternate a common R in alternate clock cycles, assuming random input codes. However in some embodiments the R value for each input code pair or a common R value is generated as a random (or pseudo random) sequence. This ensures that the output signal spectrum is whitened.

The receiver would need to be able to distinguish between seven different pulse lengths and thus could be implemented with a delay line having 16 elements and 8 taps. A different look-up table would also clearly be required.

In another embodiment redundant time slots may be used to encode at least one additional data channel or side data channel. In other words the PLM may be arranged so that at least some data pulses encode not only multiple audio channels but also at least one additional data channel. The additional data channel may, for instance comprise control data for controlling aspects of the audio apparatus. For instance audio control data for enabling or disabling mute or one of several standby or low-EMI modes, or controlling volume may be transmitted.

The additional data may be encoded as a separate data channel as described above.

Thus with two 1-bit PDM audio data channels, e.g. left and right audio data, and a 1-bit control data channel, the eight possible unique data combinations of audio and control data could be encoded as eight different pulse widths, requiring the clock period to be divided into nine separate time slots. Thus the frequency of the second clock signal could be set to be at least nine times that of the first clock signal.

However whilst it is certainly possible to derive a second clock signal to provide any desired number of time slots in the period of the first time clock signal it is noted that it most convenient to generate 2N time slots, i.e. to derive a second clock frequency which is 2' times the first clock frequency. This would provide 2N1 possible pulse lengths. Thus providing sufficient time slots to encode both the two audio data channels and the control data channel in each data pulse, with convenient generation of the second clock signal, would involve generating 16 (i.e. 2) time slots -with the associated requirements for fast circuitry.

It has been realised however that the data rate required for additional data such as control data may be lower than that required for the audio data channels. Thus in one embodiment some, but not all, data pulses may also be encoded with additional data.

Provided that the number of possible pulse lengths is at least one greater than the minimum needed to uniquely encode the audio data channels then at least one particular input combination of audio data can be encoded in two alternative ways and any instances of such audio data combination can thus be used to transfer the additional data.

Thus consider two 1-bit PDM audio data channels, for instance left and right stereo audio data. As described previously a combined signal representing both audio channels will thus be a two bit signal and will require four possible pulse lengths for unique encoding of the audio data. This would require at least five time slots in each period of the first clock signal. As also mentioned it may be more convenient to generate eight time slots (i.e. 2 time slots) rather than five, thus providing seven possible pulse lengths. As only four pulse lengths are needed to encode the audio data this leave three possible pulse lengths that can be used as alternatives encodings for the audio data. This means that three out of the four possible audio data combinations can be used to transmit additional data.

For example encoding could be performed according to the following table: Left audio data Right audio Data Control / side Pulse length (TreK) channel data o 0 0 1 0 1 0 2 1 0 0 3 1 1 N/A 4 0 0 1 7 0 1 1 6 1 0 1 5 1 1 N/A 4

Table 4

Thus a pulse length of 1TFOK indicates an input audio data combination 0100 and a control data value of 0 whereas a pulse length of 7TFCK indicates an input audio data combination of 00 but a control data value of 1. However the audio input data combination 11 is only be encoded as one possible pulse length, equal to 4TFCK.

Therefore any instances of the input audio data combination 11 means that the particular data pulse can not also be used to encode the control data.

Assuming the input audio data combinations provide effectively random sequences this still allows an average of 0.75 control bits per symbol of the MPDM data which is sufficiently high for most control data, although clearly there is a code dependent latency. This code dependence may be mitigated by re-coding the audio input data stream to reduce the density of 11 states by known methods, for example bit flipping techniques.

Figure 9 illustrates an embodiment including control data transfer. In this embodiment pulse-length-modulator (PLM) 901 receives left and right audio data as 1-bit PDM signals as described previously but also receives control data CDATA. The PLM 901 is responsive to first clock signal CK and second clock signal FCK which is eight times the frequency of the first clock signal. The PLM may implement the encoding shown in

table 4 above.

In one embodiment the audio data may be combined together with the control data value to provide a pulse length data value in accordance with the table 4 above. The pulse length data value may be compared with a sawtooth ramp signal that increase each time slot as described previously.

The data extraction modules 902 and 903 operate as described previously to extract the clock and relevant audio data signals except that the truth tables include indications of the value of control data for all pulse lengths other than 4TFGK. The extracted control data can then be used to control DAC-amplifiers 904, 905 respectively.

In some embodiments control data may only need to be transmitted infrequently.

When no control data needs to be transmitted the control data signal could be effectively be set to be a constant string of zeros (or ones). However in one embodiment when there is no control data to be transferred the PLM 901 may be arranged to vary between the alternative encodings for the audio data input combinations as described previously with respect to figure 8 in order to whiten the signal data spectrum and provide the EMI benefits mentioned above.

The FLM may therefore be arranged such that, when no control data is present, those audio data combinations that can be encoded by alternative pulse lengths are varied between the alternative encodings -either alternated or selected randomly as noted previously. Advantageously, as previously noted the two possible encodings for a given audio combination have pulse lengths which are symmetrical about a given pulse length. When subsequently control data is available the PLM may then encode the control data as described.

In this arrangement the receiver will need to be aware whether the variation between two alternative possible pulse lengths for a given audio combination is simply random variation for the purposes of reducing EMI issues or whether the encoding represents control data which has been encoded into the data pulse.

Therefore in this embodiment there is at least a first reserved sequence of control data modulation which the PLM is arranged not to use when not transmitting control data.

The receiver may decode each data pulse as if it were encoding control data and look to see whether the reserved control data pattern occurs. If not the receiver will ignore the control data encoding as being random variation implemented by the PLM.

However if the reserved data sequence is received in the control data encoding the receiver will then treat subsequent control data encoding as genuine control data.

When the PLM then reaches the end of the control data to be transmitted it may send a second reserved sequence of control data (which may be the same or different to the first reserved sequence) to indicate that the control data has ended. After the second reserved sequence has been encoded the PLM may then return to varying between the possible alternative pulse lengths for EMI management reasons. The receiver, after detecting the second reserved sequence will stop treating the encoded control data as genuine control data and disregard the control data encoding unless and until another instance of the first reserved sequence is detected.

In some embodiments, especially for higher-speed links, where rise/fall times may be significant and may be further degraded in transmission along the wires, it may be advantageous to ensure that the shortest pulse length that can be used has a certain minimum width. For instance rather than allow the shortest possible pulse length to be equal to 1TFCK it may be beneficial to ensure that the shortest pulse width is, for example 2TFCK As shown in Figure 10 if the frequency of the second clock signal is eight times that of the first clock signal then there are eight time slots and, as shown in plot (a), there may be seven possible positions at which a pulse may end, leading to seven possible pulse widths. However to ensure satisfactory detection of the pulse the minimum pulse width may be set to be equal to two time slots and hence there may be only six possible pulse widths -positions 0 to 5 shown in plot (b). There may also be advantages in ensuring a minimum gap between the end of a pulse and the start of the next pulse, e.g. there may be a minimum gap equal to two time slots -either in combination with an extended minimum pulse duration leading to five possible pulse widths as shown in plot (c) or instead of an extended minimum pulse duration, plot (d).

It should also be noted that the minimum pulse length and/or minimum gap between pulses could be some other value, such as 1.5 times the second clock period as shown in plot e.

The PLM could be arranged to produce such minimum periods by adjusting the values and delay of the ramp signal for instance and the receiver would simply arrange the delay taps at appropriate points and with an appropriate look-up table or equivalent.

Embodiments of the present invention therefore allow multiple data channels to be transmitted over a single link with the possibility of alternative encodings being available for at least some combinations of input data, which can be used to reduce the EMI effects by whitening the data signal spectrum and/or allowing transfer of additional data, such a control data, possibly at a reduced data rate. The embodiments described have discussed transfer of data in one direction only, from component 101 to component 102. In many applications howeverthere may be a need to transfer data in both directions. There may therefore be a first link for data to be transferred in a first direction, say from a first device to a second device, and a second link for data to be transferred in the other direction, from the second device to the first device. If the data to be transferred in both directions comprises multiple channels then each of the first and second devices may comprise audio interface circuitry for transmitting data such as PLM 103 and audio interface circuitry for receiving data such as data extraction module 105 and/or data extraction module 106.

In some embodiments however the same link may be used for data transfer in both directions. Figure 11 shows one embodiment of bi-directional interface circuitry that allows multi-channel PDM data to be transferred in both directions over the same link 1101 by means of a PLM Codec, i.e. a FLM encoder/decoder. First bi-directional interface circuitry 1102 is arranged to receive a first pulse-length-modulated signal MFDM-1 for transmission over the link 1101 and to extract a second pulse-length-modulated signal MPDM-2 that has been received over the link 1101 for onward transmission. Bi-directional interface circuitry 1103 does the same but in reverse.

In each of the first and second bi-directional interfaces circuitry drives switched currents dependent on MPDM-1 or MPDM-2 onto that end of the link 1 101.This link has a fixed impedance (at one or both ends) to a reference voltage VR which may, for instance by VDD/2. Both signals MPDM-1 and MPPDM-2 therefore provide a resultant voltage on the link 1101 as illustrated in Figure 12. The bi-directional interface circuitry is then arranged to subtract the signal transmitted from that end from the resultant voltage, thus ensuring that the inbound signal derived from each bi-directional interface circuit is just that which was transmitted at the far end.

In another embodiment, as illustrated in Figure 13, a single link 1301 could be used as a time-multiplexed bus. Thus with a period of a first clock signal there may be a first period of N clock cycles of a second, higher rate clock signal ECK for data transmission in one directions and a period of M clock cycles of the second clock signal FCK for transmission of data in the other direction. Thus the transmitter at one side of the link, say the PLM 1302, may transmit a pulse-length-modulated data signal based on the input data channels PDM-1 A and PDM-1 B where the pulse length is varied between 1 and N of the second clock cycles. At the end of the N cycles the output from the PLM 1302 is made high impedance and the PLM 1303 at the other end of the link starts transmitting its pulse-length-modulated signal for a selected number of the M remaining cycles. The ratio of N to M may be 50:50 or may depend on the number of channels of data being transferred in each direction. The right hand side receiver passes data to the data extraction circuitry 1304 only when its transmifter is disabled (set to high impedance). The data extraction circuitry 1304 recovers the clock signal OK and may also determine the second clock signal FCK, as described earlier, both of which are supplied to the PLM 1303. The pulse length of the received data can then be used to determine the output audio data PDM-1A and PDM-1 B. The left hand data extraction circuitry 1305 operates in the same way except that clock recovery is not needed as the relevant clock signals are available. The bus keeper or bus holderl3O6 operates to keep the link line 1301 stable (i.e. low) in underlap when both drivers are high impedance.

It should be noted that the embodiments described above have described the data link as a conductive path. This conductive path could comprise one or more of a conductive path on an integrated circuit, a contact between an integrated circuit and a printed circuit board (PCB), a conductive path on a PCB, a contact for an external device such as a contact on a plug or socket for example and/or a conductive wire.

For example an audio processing integrated circuit (IC) of a host device, such as an audio codec, may have a PLM encoder as part of the IC for producing a PLM data stream from data received from the codec, for instance retrieved from memory or from a communications processor or the like. This may be communicated, for instance via a PCB, to output transducers within the host device. Each output transducer may have an associated transducer driver which includes a PLM decoder which decodes the data stream for that transducer or one transducer driver may include a PLM decoder for decoding the data streams for multiple transducers. In some embodiments have the PLM encoder and/or PLM decoder may be separate lOs. There may be a DAC associated with an output transducer to receive, from the PLM decoder, the decoded digital data stream for an output transducer and provide analogue driving signals. The DAC5 could form part of the same IC and the PLM decoder and/or transducer driver or again be a separate IC. The PLM data stream may also be transmitted to a connection interface for conversion to an analogue signal for transmission to an accessory apparatus.

The PLM data stream may also be transmitted to an external device, i.e. an accessory device such as a headset, via any suitable connection -for instance a plug and socket.

The FLM data stream may therefore be sent, via suitable contacts on the relevant connectors, to an external peripheral device. Again there may be a transducer driver having an associated PLM decoder and possibly a DAC, as part of the same IC or separate, for each output transducer or one transducer driver may produce data streams for multiple transducers.

Likewise input transducers may be coupled via ADCs to a PLM encoder for generating a FLM data signal to be sent to a FLM decoder associated with the audio circuitry, which may or may not may part of the same IC.

However the link could be provided by any suitable means of data exchange. For instance an optical (for example infra-red) data link could be provided via a suitable waveguide, such as an optical fibre or the like, or may simply be transmitted into free space, e.g. for a wireless headphone. In such an embodiment the FLM may comprise an optical source for producing a length modulated optical pulse and the receiver may comprise an optical detector. The optical link may comprise a suitable optical detector and as mentioned the link may comprise optical waveguides or be at least partly achieved through free space. Fart of the optical link may be implemented in an optical circuit board. The optical transmitter may itself be a FLM encoder and thus may receive individual data streams directly and produce an appropriate PLM data stream.

Alternatively the optical transmitter may receive a PLM data stream over a conductive wire from a FLM encoder in a host device and simply convert it to an optical signal. On a receiver side an optical receiver may be an optical PLM decoder for decoding the optical FLM data received and providing individual digital data streams for each transducer. Alternatively there may be an optical transducer which converts an optical PLM data signal into a corresponding electrical PLM data stream which can then be decoded as described above.

Alternatively or additionally the link could be provided by RE transmission and thus PLM may comprise a suitable transmitting antenna for generating length modulated RF transmissions and the receiver may comprise a receiving antenna. Again the RE transmission apparatus may include a PLM encoder for receive individual data streams directly and produce an appropriate RF PLM data stream or it may receive a PLM data stream over a conductive wire from a PLM encoder in a host device and simply produce a corresponding RF PLM signal. On a receiver side the RF receiver may be an RF PLM decoder for decoding the RF PLM data received and providing individual digital data streams for each transducer. Alternatively there may be an RF transducer which converts an RF FLM data signal into a corresponding electrical PLM data stream which can then be decoded as described above.

The link may comprise various different types of transmission medium and may comprise components for converting one type of FLM data signal, say a voltage pulse-length modulated signal on a conductive path into another type of PLM data signal say an optical pulse-length-modulated signal in an optical waveguide for example.

In some applications, where a destination device for the transmitted audio signals does not have its own power source it will be necessary to transfer power as well as the data. Thus, although the data for multiple audio channels may be transmitted via single data link it may be necessary to also have at least a power supply link and a ground link. Where there is two way data exchange there may also be separate data links for outbound and inbound data. However in some embodiments, especially when the MPDM signal comprises voltage pulse-length-modulated signals, the data signal may also be used to transfer power. Various techniques are known for deriving a power supply voltage from a data supply, for example using a simple diode or synchronous switching circuitry. When the data link is also used to transfer power the voltage on the data line may be arranged to vary from a first non-zero voltage to a second non-zero voltage to indicate the data pulses. In this way the signal line is never at zero voltage. However given that with embodiments of the present invention there is always at least one data pulse per cycle and there may be a minimum pulse period or controlled average pulse period (which may be equal to half the clock cycle) it would be possible to derive a suitable supply voltage even if the data pulses vary between a first non-zero voltage and ground.

Figures 14 to 18 illustrate some example applications of the embodiments of the present invention as applied to headsets, i.e. headphones or earbuds or the like which may or may not include microphones for voice data transfer or active noise cancellation (ANC). The same principles would also apply to connections of other accessory devices.

Figure 14 illustrates a two way data exchange between a DSP or codec 1401 of a first device 1402, such as a personal media player, gaming device or mobile telephone, to a headset 1403 via interface circuitry 1404. In this embodiment there is two way data exchange using FLM data signals (MPDM_UP and MFDM_DOWN). The headset may have interface module 1405 which receives the MPDM_UP data signal, as well as separate power and ground links, and which transmits the MPDM_DOWN signal. The device 1402 may therefore connect to the headset 1403 via a 4-connector plug 1406.

The interface module 1405 of the headset may receive the MPDM_UP signal and transfer the signal to data extraction circuitry associated with each loudspeaker 1408, 1409 in a similar fashion as described previously (or alternatively could extract the two PDM data channels and send each data PDM channel to the appropriate loudspeaker).

The interface module 1405 may also receive audio data, via individual single channel PLM or PDM data links (which may use a clock or clocks recovered from the MPDM data received by the adjacent speaker circuitry), from noise cancellation microphones 1409, 1410 associated with each loudspeaker and may produce a multi-channel audio signal MPDM down to be transmitted back to the DsPtcodec 1401.

Figure 19 shows a similar arrangement to Figure 14 but illustrates that the earphones may also comprise error microphones 1901 and 1902 which monitor the sound emitted into the ear. The error microphones 1901, 1902 may be used instead of outward facing, i.e. ambient noise facing, active noise cancellation microphones 1409 and 1410 to implement a feedback noise cancellation system. In some embodiments however the forward facing, i.e. speaker facing, microphones are provided in addition to the outward facing microphones 1409, 1410 in a combined feedback/feedforward system or to continually tune the signal processing of a feedforward ANC system. Where both inward and outward facing microphones are present then there may be two channels of audio microphone data to be transmitted from the earphone. The error microphone may be a digital microphone package or chip converting a signal from the analogue microphone transducer element into a digital format, for example a single-bit delta-sigma audio data stream.

Each earphone may therefore be provided with a FLM module 1903, 1904 comprising data extraction circuitry, i.e. a PLM decoder, for extracting the appropriate audio signals for the speakers and also PLM encoding circuitry for encoding the audio data from the microphones into an MPDM_DOWN signal for transmission to the interface module 1405.

In some embodiments the loudspeaker in the earphone may generate a signal indicative of the instantaneous current flow passing through the speaker coil. This flow data regarding the speaker current may be useful for speaker protection functions where the current flow data is fed back to an upstream DSP circuitry to appropriately limit the current fed to the speaker so as to avoid thermal or mechanical overload of the speaker. This current flow data may be generated by any suitable current sensing element, such as a MOS current mirror or resistor, within driver amplifier circuitry inside the headphone. The flow data may be in a digital format, for instance a 1-bit delta-sigma data stream. Thus there may be a desire to transmit speaker current flow data in addition to one or more audio data channels from one or more microphones. Again therefore PLM circuitry in the earphone may combine the microphone data and current flow data into a PLM signal as described previously for transmission to the interface module.

Figure 20 shows an embodiment similar to that shown in Figure 19 but with addition of a voice microphone 2001 to pick up a user's voice, possibly together with a related outward facing microphone 2002 that picks up ambient noise to enable transmission side noise cancelling. Again these microphones 2001 and 2002 may be digital microphones, for example with single-bit delta-sigma output formats. The microphones may or not be co-packaged with interface module 1405. The microphone data could be transmitted to the interface module 1405 as, for example, separate PDM data streams for the interface module to merge this data into a PLM signal (MPDM-DOWN) to be transmitted to the device. However in some embodiments these output audio streams may be merged together by PLM 2003 which is local to the microphones to produce a PLM data stream for transmission to interface module 1405. The interface module may then merge the data from the voice microphone(s) with any data from the earphone noise cancellation microphone(s) and any other data such as speaker current flow data.

Figure 15 illustrates an embodiment with the same four links as shown in Figure 14.

However in this embodiment the interface module is effectively located with one loudspeaker. Thus the right loudspeaker data extraction module (i.e. on the right hand of the page -as shown this would be the left channel for the user) receives the MPDM_UP signal, extracts the data for the right audio channel and forwards the MPDM_UP data onto the left loudspeaker circuitry. The active noise cancellation audio data from the microphone associated with the left loudspeaker is sent, as single channel PDM, possibly using a clock or clocks recovered from MPDM UP, to interface circuitry associated with the right loudspeaker where the multi-channel MPDM_DOWN signal is formed.

Figure 21 shows another embodiment similar to Figure 15 but again illustrates that there may be inward facing and/or outward facing microphones and thus there may be data from more than one microphone from each earphone. Additionally or alternatively there may be speaker current flow data to be transmitted as described above.

In this embodiment the earphone shown on the left thus has a PLM module for transmitting a PLM signal based on the combined microphone/current data. The interface in the earphone shown on the right combines this data with the data from the right earphone for transmission to the devicel4O2. The MPDM_DOWN signal from the interface in the right shown earphone may therefore be the combined data from four or more data streams, e.g. two microphone channels for each earphone.

Figure 16 shows another embodiment similar to that shown in Figure 14 but wherein a single link (MPDM) is used for bi-directional data transfer. Thus only a three connector plug and socket are required. Figure 17 is a similar embodiment to that shown in Figure 15 but using a bi-directional data link. In this embodiment the data link between the right and left hand speakers may be used to send the multichannel MPDM signal up to the left speaker with only one channel of PDM data from the microphone associated with the left speaker being sent back on the same link. Again there could be more than one microphone for noise cancellation and/or speaker current flow data could be sensed and transmitted along the bi-directional link. Also there may be voice microphone data from a voice microphone, possibly with a transmission noise cancellation microphone.

Figure 18 shows an embodiment similar to that shown in Figure 17 but wherein the data signal link is also used to provide power supply. Thus only a two connector plug/socket is required to provide the link for power/data signal PMDM and ground. An interface module in the headset derives power for the loudspeakers and data extraction circuitry.

As mentioned some embodiments may include transmission of detected current and/or voltage waveforms from the speakers to the host device or codec, for speaker protection features, instead of or in addition to signals from the adjacent microphones.

Also similar configurations of the speakers and microphones may be part of the host device, wired via a PCB or other internal wiring, rather than separately wired headphones.

A device may therefore have several different audio transducers such as speakers and/or microphones within a device and/or connections for various external audio peripherals such as headsets etc. Figure 22 illustrates how a device 2201,which could for example be a portable computing device, mobile telephone handset or the like, may have an audio codec 2202 that may or may not include Digital Signal Processing (DSP) circuitry for processing audio signals for the device. The device itself may comprise various audio transducers, i.e. components such as loudspeakers 2203 and 2204 and microphones 2205 and 2206. In addition there may be a connection interface 2207, such as a suitable jack, for connecting a headset 2208 which may comprise loudspeakers 2209 and 2210 for audio play back and one or more microphones 2211 for voice communication or noise cancellation. It will of course be appreciated that the headset could take the form of any of the embodiments described above.

In operation the DSP/Codec 2202 may transmit data to the loudspeakers 2203 and 2204 of the device or the loudspeakers 2209 and 2210 depending on whether a headset is connected and/or the operating mode of the device. The DSP/Codec may also receive data from the microphones 2205 and 2206 on the device and/or microphone 2211 on the headset. There may also be data regarding operation of the transducers such as loudspeaker current data as described previously.

It can be therefore be seen that, in the audio domain, there device has a number of possible generators and consumers (or sources and sinks) of data that need to communicate with the DSP/Codec. For instance! microphones 2205 and 2206 on the device may be generators of audio data streams, labelled as B and C respectively.

Loudspeakers 2203 and 2204 on the device may be consumers for audio data streams (labelled as streams a and d respectively) transmitted from the DSP/Codec 2202. In addition in some embodiments the loudspeakers may also be generators of current data, data streams A and D respectively.

The loudspeakers 2209, 2210 of the headset may also be consumers of audio data streams (streams e and f respectively) and headset microphone 2211 may be a generator of data stream 0.

All of the signals generated and/or consumed by the audio transducers may be digital signals, for instance 1 bit data streams, with any necessary digital-to-analogue or analogue-to-digital conversion being embedded within the respective transducer circuitry.

All of the transducers within the device 2201 and interface 2207 therefore need to be connected to the DSP/Codec 2202, and, as mentioned above, digital data connections are typically preferred. Each transducer within the device could be separately connected to the DSF/Codec 2202 via a separate connection but this would involve multiple connection paths on the FCB and multiple pins on the DSPfCodec.

As mentioned previously the use of PLM encoding can allow multiple audio data streams to be encoded and transited over a single wire link. Thus as discussed above in relation to Figure 2 the data streams a and d for loudspeakers 2203 and 2204 could be combined into a PLM signal and transmitted over a common signal path, i.e. a single signal path on the PCB say, for at least part of the signal path before being separated into separate paths to each loudspeaker.

In another embodiment however the signal paths may be arranged so that there is a link, i.e. signal path, between first and second components such that data to be transmitted to or received from the second component is transmitted via the first component.

In other words for data to be transmitted to the second component, a pulse length modulated signal with combined data for both the first and second components may be received by the first component. The data extraction circuitry for the first component can extract the relevant data for the first component and then forward the signal to the second component. The forwarded signal may be an unchanged version of the received PLM signal and the second component may therefore extract the relevant data. Alternatively the first component could extract the data for both of the first and second components and transmit a PDM signal with just the relevant data for the second component to the second component. In some embodiments, as will be described below, the second component may itself have a link for forwarding a signal to a third component and the data transmitted to the first component may be a combined data stream for all of the first, second and third components, in which case the data forwarded from the first component to the second component may be the original PLM signal (MPDM) or a re-encoded PLM signal (MPDM') with just the data for the second and third components.

Likewise for data being received the second component may transfer data to a first component over a link -which could be a single data stream representing data from just the second component or may be a PLM signal encoding data from at least a third component. The first component will receive the data and merge it into a PLM signal for onward transmission.

Figure 23 shows an embodiment of a suitable connection between the transducers of the device arrangement illustrated in Figure 22. Figure 23 shows a FLM module 2301, e.g. a PLM codec, for communications to/from the DSP/Codec 2202.

For data to be transferred from the DSP/Codec 2201 to the loudspeakers there is a first signal path to the loudspeaker 2203 for transmitting a signal mU. There is also a signal path from loudspeaker 2203 to loudspeaker 2204 for transmitting a signal ml and a further signal path from loudspeaker 2204 to interface 2207 for transmitting a signal m4. In use, with a headset connected by plugging a suitable connector into the jack of interface 2207 there will also be a signal path from interface 2207 to the loudspeakers of the headset 2208 for transmitting a signal m4'.

The signal mU transmitted by the DSP/codec 2202 to loudspeaker 2203 must therefore contain all necessary audio streams for loudspeakers 2203, 2204 and the loudspeakers of the headset 2208, i.e. signal mU must comprise audio streams a and d and/ore and f.

In some devices and applications the device may be arranged such that the internal loudspeakers 2203 and 2204 do not operate if audio is being played via the headset loudspeakers and vice versa. In such a situation there may only ever be a need to transmit two audio data streams, perhaps along with control data for activating/deactivating the relevant loudspeakers. In some applications however it may be necessary to transfer separate data streams a, d, e and f simultaneously.

Signal mU may therefore be a FLM signal which encodes the required data streams.

Data extraction circuitry associated with loudspeaker 2203 extracts the data stream a for loudspeaker 2203 (if present) and forwards the signal to loudspeaker 2204. The signal ml which is forwarded may be a re-encoded PLM signal with just data streams d, e and f but it may be simpler in some embodiments to simply forward the signal received, i.e. ml is equivalent to mO.

Data extraction circuitry associated with loudspeaker 2204 receives the signal ml an extracts any data for audio stream d. A signal m4 is then forwarded to the interface 2207. Again the signal that is forwarded may the same as the signal received, i.e. m4=ml or the signal may be re-encoded.

The interface 2207 receives signal m4 and forwards data to the headset (when connected). The interface jack may also transmit power and provide a ground connection as described above in relation to the headset embodiments. The interface may simply provide an appropriate connection for the incoming signal m4 to the jack.

However in some embodiments it may be preferred to receive the signal at the interface and re-transmit a signal via the connection. Again the transmitted signal m4' may be the same as the signal m4 received at the interface. However in some embodiments the interface does extract data streams e and f and generates a new PLM signal containing only data streams e and f. As will be appreciated the headset connection may be relatively long and of a more variable quality than is the case for the relatively predictable connections within the device itself Re-encoding the signal to be transmitted by the interface to contain just the audio data streams e and I for the headset means that fewer distinct pulse lengths are required in the signal and thus a larger time resolution (i.e. slower second clock) can be used as compared to the signals transmitted within the device. This can ease the signal integrity requirements and ensure good transmission The discussion above of course assumes that the headset is suitable for receiving FLM signals. In some embodiments the headset may instead use conventional digital audio signals or instead require analogue driving signals. In which case the interface 2207 receives the PLM signal m4 and extracts the relevant audio data streams e and f and generates appropriate driving signals for the headset.

Figure 23 also shows a separate series of signal paths between components for transmitting data to the DSPtCodec 2202. Data from the microphone(s) of the headset 2208 may be communicated to the interface 2207 as a data signal M4. Where there is a single microphone with digital output this output could be transmitted as a single-bit digital data stream. Where there are two or more microphones and/or other data to be transmitted a suitable PLM signal may be transmitted.

The interface 2207 receives this signal and forwards a signal M4 to next component in the series, in this example loudspeaker 2204. Data extraction circuitry in the interface 2207 could determine the received audio signal data G in the received signal M4' and re-encode it in the signal M4 transmitted to the next component or the received signal may be transmitted directly in some embodiments.

In this example the loudspeaker 2204 is also a generator of data, for example current data used for speaker protection. Thus the signal M4 from the interface is received and combined with the speaker data for onward transmission as a PLM signal M3 to the next component, microphone 2205. Here the data from microphone 2205 is combined with the existing audio data and a new signal M2 transmitted onward.

Data stream C from microphone 2206 is also combined into the signal to form a new signal Ml which is then combined with data A from loudspeaker 2203 to form a signal MO which is then passed to the PLM module 2301 associated with the DSP/Codec 2202. Signal MO is therefore a PLM signal which includes data streams A, B, C, D and G. The data extraction circuitry in PLM module 2301 can extract the individual data streams and transmit the retrieved data streams to the DSP/codec in any suitable way.

It should be noted that each of signals MO, Ml, M2 and M3 are PLM signals. As mentioned signal M4 comprise a single audio data stream only and thus could be a PDM signal for instance but in some embodiments may be a PLM signal.

In each link between components the PLM signal produced may be provided with just sufficient time slots to encode the audio data streams present. For example if there is only a single data stream of audio data from the headset 2208 and a single data stream of current data from loudspeaker 2204 then signal M3 may be an PLM signal with five time slots (to provide four different pulse lengths with a gap between pulses).

In other words the second clock for the relevant link may have a frequency five times that of the first clock signal. For signal M2 however there is a need to encode another data stream (data stream B) and thus eight pulse lengths and nine time slots may be required. Thus the relevant link may run with a different second clock frequency which is nine times the first clock frequency. Typically the same first clock frequency will be used on all links as this will be set by the required bit rate.

In some embodiments however it may be desirable to use the same general circuitry for each link, thus the first and second clock frequencies may be set to be the same for each of the PLM signals in the chain. Thus signal MO may have a second clock frequency running at at least 33 times the first clock frequency to provide 32 different pulse lengths to encode the five data streams A, B, C, D and G. Each of the signals Ml, M2 arid M3 (and possibly M4) may therefore also run with a second clock frequency which is at the same frequency thus potentially allowing the same number of pulse lengths. For the earlier signals in the chain the various alternatives for encoding the signals present could be alternated as described previously or only a subset of possible pulse widths could be used.

Each of the components receiving a PLM signal and adding new data to the signal sent onwards could be provided with data extraction circuitry for extracting the existing data and a PLM modulator for producing a new PLM signal based on an appropriate truth

table.

In some instance however each component may be arranged to modify the pulse length of the pulse without determining what the existing data is. For example assume that each of signals M4, M3, M2, Ml and MO is a PLM data signal with 32 available pulse lengths, i.e. there are 33 time slots in each period of the first clock signal. The interface 2207 may produce a signal that encodes the single data stream G only. The PLM associated with the interface could be arranged to produce a pulse of 1 time slot in length for data 0 and a pulse of 17 time slots in length for data 1. The loudspeaker may then may arranged to leave the pulse length unmodulated if data stream D is data 0 but to extend the pulse length by 8 time slots if data stream D is data 1. Likewise microphone 2205, microphone 2206 and loudspeaker 2203 could each be arranged to leave the pulse length unmodulated if the relevant data stream is data 0 and to extend the pulse length by 4,2 and 1 time slots respectively if the relevant data stream is data 1.

The result will be a pulse length in signal MO which uniquely encodes all of the data streams A, B, C, D and G. However each component in the chain simply modifies the pulse length by a predetermined amount based on its own data stream and doesn't need to determine what the upstream data is.

This arrangement means that a single PLM signal can be sent upstream from the DSP/Codec to provide data for all consumers of audio data with each consumer component simply tapping data from the signal at an appropriate point in a chain.

Likewise a chain for downstream data to be transmitted to the DSP/Codec is provided with data being merged into the signal at appropriate points. This avoids the need for distinct connections to/from each component.

In such an arrangement the upstream and downstream links may be arranged relatively close together as shown and thus two signal paths, e.g. traces on a PCB, may pass near to some of the transducers. In the example shown in Figure 23 the signal paths are close to the transducers consuming signals a and d and generating signals A, B, C and D. However some transducers may be separated relatively far apart from one another on the device. In the example shown in Figure 23 microphone 2206 is located on the opposite side of the device. Thus means that a separate, relatively long, connection must be used to connect the microphone to a suitable tap point on the PLM link. Otherwise a separate connection between microphone 2206 and DSP/Codec 2202 may be provided.

In another embodiment however the links between at least some components may be arranged in a complete chain. Thus data transmitted by the DSP/codec 2202 for an upstream consumer component may be transmitted in the same direction as data generated by a component for transmission to the DSP/Codec 2202. This allows for two signal paths to be spaced apart in a configuration that reduces the amount of signal track required but still provides communication between the DSPfCodec 2202 and each consumer and still allows each generator to transmit to the DSP/Codec.

Figure 24 illustrates one example of a suitable arrangement. In this arrangement the PLM module 2301 of DSP/Codec 2202 has a first link to loudspeaker 2203 as described previous and transmits a signal mU which is a PLM signal which encodes data for all of the generators as described previously. In this embodiment however the data stream a for loudspeaker 2203 is extracted and the measured current flow data is also encoded into the signal transmitted ml onward from the loudspeaker. This signal is transmitted to the microphone 2205 where the signal is re-coded to include data stream B. Signal m2, which thus contains at least audio data streams d, e and f and data streams A and B, is then passed to loudspeaker 2204 where audio data d is extracted for the loudspeaker and current flow data 0 is encoded. The signal comprising data streams e and f and also A, B and 0 is then passed to the interface where audio data streams e and f can be extracted for sending to the headset as described above. Any microphone data from the headset can encoded into the signal m4 which is then sent, via a different return path, to microphone 2206. Microphone data stream C is encoded to produce signal m5 which is then returned to the DSP/Codec which can the extract data streams A, B, C, D, and C. The PLM signal transmitted between any components may therefore be suitable to encode each of the data streams a, d, e and f and A, B, C, D and G. It will be appreciated however that no signal comprises audio streams a and A. In other words as loudspeaker 2203 consumes audio stream a but generates data stream A the PLM signal ml may be adjusted so that the encoding for outgoing audio stream a is replaced by the encoding for measured data stream A. Likewise no signal contains both audio stream d and data stream D or audio streams e and f and microphone data stream 0. The most number of individual data streams is thus those contained in signals m2, m3 and m5 which need each need to encode five different data streams (m2 encodes consumer audio streams e and f and generated data streams A, B and D; m3 encodes data streams e, f and A, B and D; and m5 encodes generated data streams A, B, C, D and G).

Thus each link may use a PLM signal capable of encoding five different data streams.

Signal mU originally transmitted will encode the consumer data streams a, d, e and f and may use the other available pulse lengths as alternatives to whiten the data spectrum as discussed previously. Signal ml re-encodes the signal to remove the data encoding for stream a but to include data from stream A. Again the PLM module associated with each component may extract the data for each data stream and remodulate taking any new data into account or may simply extract any data for the relevant component and apply a unique length modulation based on any current data. In this instance the modulations applied by those components that replace data will need to take the value of the extracted data into account and the initial signal encoding by the DSP/Codec should use the same length modulation for the relevant data channel.

Obviously the data extraction/modulation circuitry for each component will need to know which data stream to extract. This can be predetermined and fixed so that each transducer always extracts a given data stream, in which case the relevant details can be stored in a suitable non-volatile memory and/or the data extraction circuitry may be hardwired so as to generate data 1 for predetermined pulse lengths and data 0 for other pulse lengths. In other embodiments however there may be some configurability in which component extract data at which point in the chain. This could be established however by any suitable configuration, such as token passing such as is known in the art.

A PLM encoder/decoder such as described above may be implemented as part of a host device which is configured for communication with various other components of the host device and external devices that may be connected in various ways. For instance Figure 25 shows a device 2501, in this example a mobile telephone handset which may have various internal audio transducers and connections for external accessory apparatus. The handset 2501 may have at least one internal loudspeaker 2502 and at least one microphone 2503. There may also be various microphones 2504 arranged for noise cancellation. There may also be a user interface, such as control buttons 2505, a keyboard and/or touch screen 2506 for activating various control functions such as volume control.

As shown in figure 26 a device 2501 may therefore comprise audio processing circuitry such as a digital audio hub 2601 for control over audio for the device. The audio control circuitry 2601 may therefore provide audio data to output transducers of the host device 2501, such as speaker 2502, and receive data from input transducers of the host device, such as microphone 2503 (and/or microphones 2504 shown in Figure 25).

In use the audio circuitry 2601 may receive and transmit audio data from/to various other device systems. For instance the audio circuitry 2601 may receive audio data from a baseband (communications) processor 2602 via a first interface 2603. The baseband processor 2603 may provide communications to a telephone network 2604 via a suitable antenna. Thus audio circuitry 2601 may receive audio data from the baseband processor for processing and transmission to loudspeaker 2502 and data from microphone 2503 may be sent for communication via the telephone network 2604.

The audio circuitry may also communicate with an applications processor 2605 via a second interface 2606. The applications processor may retrieve audio data from memory 2607, for instance for playback of stored music. Commands from a device user interface may be communicated to the audio hub 2601 via the applications processor 2605.

There may also be additional systems such as a wireless transceiver 2608 which communicates via interface 2609 for wireless communications.

In some instances the various device systems may communicate audio data with each other via the audio processing circuitry 2601. The audio processing circuitry 2601 may therefore comprise at least two interfaces for device systems with a digital only path between interfaces.

The audio circuitry 2601 may also transmit data to external devices, such as accessory or peripheral apparatuses. For instance the audio circuitry 2601 may communicate via suitable connections with output transducers 2610 and/or receive data trom external input transducers 2611.

Referring back to Figure 25 such external apparatuses may be connected in various ways. For instance a headset comprising earphones 2507 for receiving stereo data and a voice microphone 2509 for receiving voice audio may be connected via a suitable jack plug to a headphone socket of the device. The same socket could also be used for driving line-out signals to an external audio device, or such an external audio device 2509 comprising speakers 2510 and an amplifier unit 2511 could be connected via a different connector, possibly via a docking station. Wireless communication may also be used to communicate audio data wirelessly to a suitable device, such as wireless headset 2512 having speakers 2513 and microphone 2514. As shown in Figure 26 wireless communication may occur via wireless transceiver 2608.

Embodiments described above have assumed that all incoming PDM data streams have the same sample rate. If say one data stream has say half the sample rate, then each sample may obviously be sampled twice in successive clock intervals to provide an equivalent system. Similarly each sample of a PDM output stream may be sampled more than once to provide a higher effective sample rate.

Embodiments described above receive one-bit, i.e. two-level, streams of input data.

The invention may be adapted to process multi-level inputs, e.g. 3-level inputs (-1, 0, +1) as used to directly drive Class D H-bridges for example, by suitable adaptation of the truth tables, and similarly to output multi-level output pulse streams.

It can therefore be seen that embodiments of the present invention can be used to provide efficient data transfer using only a limited number of connections and which offers the ability to send additional data when required and/or reduce any EMI effects by making use of alternative data encodings for combinations of input data.

The embodiments herein have been described in relation to audio data. However, although reference is made herein to "audio data", the electrical signals that are handled by the circuitry can represent any physical phenomenon. For example, the term "audio data" can mean not just signals that represent sounds that are audible by the human ear (for example in the frequency range of 20Hz -20kHz), but can also mean input and/or output signals to and/or from haptic transducers (typically at frequencies below 20Hz, or at least below 300Hz) and/or input and/or output signals to and/or from ultrasonic transducers (for example in the frequency range of 20kHz - 300kHz) and/or to infrasonic transducers (typically at frequencies below 20Hz).

Therefore, it will be appreciated that the principles disclosed herein may be applied to other types of data for driving transducers such as haptic transducers, ultrasonic transducers, hearing aid coils and the like or for receiving data from transducers. In general for a given functional unit of a device there may be various consumers of data transmitted from that unit and various generators of data to be received by that functional unit, as described above in the context of an audio DSP/codec. The embodiments of the present invention are equally applicable to other types of data that may be sent from a functional unit to consumers and/or sent to the functional unit from generators.

It will be appreciated that the interface circuitry may conveniently be implemented, at least partly, as an integrated circuit and may form part of a host electronic device, especially a portable device and/or a battery powered device. The interface circuitry may be used in an audio device such as a personal music or video player. The amplifier may be implemented in a mobile communications device such as mobile telephone or a computing device, such as a laptop or tablet computer or PDA. The interface circuitry may be used in a gaming device.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single feature or other unit may fulfil the functions of several units recited in the claims. The word "amplify" can also mean "attenuate", i.e. decrease, as well as increase and vice versa and the word "add" can also mean "subtract", i.e. decrease, as well as increase and vice versa. Any reference numerals or labels in the claims shall not be construed so as to limit their scope.

Claims

<claim-text>CLAIMS1. Audio interface circuitry comprising: a pulse-length-modulator, responsive to a plurality of data streams of audio data samples at a sample rate, to generate a stream of data pulses at said sample rate; wherein the length of each said data pulse is dependent upon on a combination of the then current audio data samples from said plurality of data streams.</claim-text> <claim-text>2. Audio interface circuitry as claimed in claim 1 wherein said audio data streams comprise 1-bit digital audio data streams.</claim-text> <claim-text>3. Audio interface circuitry as claimed in claim 1 or claim 2 wherein said audio data streams correspond to audio data channels.</claim-text> <claim-text>4. Audio interface circuitry as claimed in any preceding claim wherein the pulse-length-modulator is responsive to a first clock signal having a frequency equal to said sample rate.</claim-text> <claim-text>5. Audio interface circuitry as claimed in claim 4 wherein said pulse-length-modulator is further responsive to a second clock signal, wherein the second clock signal has a frequency which is a multiple of the frequency of the first clock signal and wherein the length of each data pulse is based on a selected number of cycles of the second clock signal.</claim-text> <claim-text>6. Audio interface circuitry as claimed in claim 5 wherein the minimum data pulse length is a plurality of cycles of the second clock signal.</claim-text> <claim-text>7. Audio interface circuitry as claimed in claim 5 or claim 6 wherein the maximum data pulse length is shorter than the period of the first clock signal by a plurality of cycles of the second clock signal.</claim-text> <claim-text>8. Audio interface circuitry as claimed in any preceding claim wherein the pulse-length-modulator is configured so that at least one combination of input audio data for said plurality of audio data streams can be encoded as at least two different alternative data pulse lengths.</claim-text> <claim-text>9. Audio interface circuitry as claimed in claim 8 wherein the pulse-length-modulator is configured so as to vary between said at least two different alternative data pulse lengths when encoding said at least one combination of input audio data.</claim-text> <claim-text>10. Audio interface circuitry as claimed in claim 8 or claim 9 wherein the pulse-length-modulator is configured so as to alternate between said at least two different alternative data pulse lengths when encoding said at least one combination of input audio data.</claim-text> <claim-text>11. Audio interface circuitry as claimed in claim 8 or claim 9 wherein the pulse-length-modulator is configured so as to randomly select one of said at least two different alternative data pulse lengths when encoding said at least one combination of input audio data.</claim-text> <claim-text>12. Audio interface circuitry as claimed in claim 8 or claim 9 wherein the pulse-length-modulator is configured so as, when encoding said at least one combination of input audio data, to vary between said at least two different alternative data pulse length so as to control the average data pulse length for all instances of a given combination of input audio data.</claim-text> <claim-text>13. Audio interface circuitry as claimed in claim 12 wherein a plurality of combinations of input audio data can each be encoded as a plurality of alternative data pulse lengths and the pulse-length-modulator is configured to vary between the respective alternative data pulse length so that the average data pulse length for each combination of input audio data is substantially the same.</claim-text> <claim-text>14. Audio interface circuitry as claimed in any of claims 8 to 13 wherein a plurality of combinations of input data can each be encoded as two different lengths of data pulse, the two lengths being symmetric about a predetermined length.</claim-text> <claim-text>15. Audio interface circuitry as claimed in claim 14 wherein one combination of input data can be encoded as a data pulse having a length substantially equal to said predetermined length.</claim-text> <claim-text>16. Audio interface circuitry as claimed in any preceding claim wherein the pulse-length-modulator is also configured to receive at least one additional data channel and wherein the length of at least some individual data pulses encodes the then current audio data samples from said plurality of data streams and also the then current data sample for said additional data channel.</claim-text> <claim-text>17. Audio interface circuitry as claimed in claim 16 wherein said additional data channel is a control data channel.</claim-text> <claim-text>18. Audio interface circuitry as claimed in claim 16 or claim 17 wherein! when no data is received on said additional data channel the pulse length modulator may vary between pulse lengths that encode the same audio data combination.</claim-text> <claim-text>19. Audio interface circuitry as claimed in claim 18 wherein the pulse-length-modulator is configured such that, when data is received on an additional data channel to modulate a series of data pulses with a first reserved sequence prior to encoding said data of the additional data channel, where the first reserved sequence corresponds to the encoding that would be used for a particular data sequence on the additional data channel and wherein the pulse-length-modulator is configured so as not to use the first reserved sequence when no data is available on the additional data channel.</claim-text> <claim-text>20. Audio interface circuitry as claimed in claim 18 or claim 19 wherein the pulse-length-modulator is configured such that when data on the additional channel stops it encodes a second reserved sequence of additional data.</claim-text> <claim-text>21. Audio interface circuitry as claimed in any preceding claim, when dependent directly or indirectly on claim 5, wherein the frequency of the second clock signal is at least five times the frequency of the first clock signal.</claim-text> <claim-text>22. Audio interface circuitry as claimed in claim 21 wherein the frequency of the second clock signal is at least eight times the frequency of the first clock signal.</claim-text> <claim-text>23. Audio interface circuitry as claimed in any preceding claim wherein said plurality of audio data streams comprise left and right stereo data channels.</claim-text> <claim-text>24. Audio interface circuitry as claimed in any preceding claim wherein said pulse-length-modulator is configured to receive a separate audio data stream for each of said audio channels.</claim-text> <claim-text>25. Audio interface circuitry as claimed in claim 23 or 24 wherein the pulse-length-modulator comprises a combiner for producing a combined data value from each of said audio data streams.</claim-text> <claim-text>26. Audio interface circuitry as claimed in claim 25, when dependent on claim 5, further comprising a counter arranged to count at a frequency of the second clock signal and a comparator for comparing the count value to the combined data value.</claim-text> <claim-text>27. Audio interface circuitry as claimed in any preceding claim wherein the pulse-length-modulator is configured to produce an output which varies between a first non zero voltage and a second non zero voltage.</claim-text> <claim-text>28. Audio interface circuitry as claimed in any preceding claim wherein the rising edges of the data pulses are separated by a regular time interval equal to the sample period.</claim-text> <claim-text>29. Audio interface circuitry as claimed in any of claims ito 27 wherein the falling edges of the data pulses are separated by a regular time interval equal to the sample period..</claim-text> <claim-text>30. Audio interface circuitry as claimed in any preceding claim wherein the output from the pulse-length-modulator is connected to an audio signal path on a printed circuit board of a host device.</claim-text> <claim-text>31. Audio interface circuitry as claimed in any preceding claim wherein the output from the pulse-length-modulator is connected to a connector of a host device.</claim-text> <claim-text>32. Audio interface circuitry as claimed in 31 wherein said connector comprises a socket.</claim-text> <claim-text>33. Audio interface circuitry as claimed in claim 31 where said connector comprises a connection for a headset.</claim-text> <claim-text>34. Audio interface circuitry as claimed in claim 31 or claim 32 wherein said pulse-length-modulator is configured, in use, to provide audio data and power to a peripheral connected to said connector.</claim-text> <claim-text>35. Audio interface circuitry as claimed in any of claims 31 to 33 wherein said connector comprises connections for audio data-out, power and ground.</claim-text> <claim-text>36. Audio interface circuitry as claimed in claim 35 wherein said power connection also serves as said audio data-out connection.</claim-text> <claim-text>37. Audio interface circuitry as claimed in claim 35 or claim 36 further comprising an audio data-in connection.</claim-text> <claim-text>38. Audio interface circuitry as claimed in claim 37 wherein said audio data-in connections also serves as said audio data-out connection.</claim-text> <claim-text>39. Audio interface circuitry as claimed in claim 31 wherein the connector is an optical connector.</claim-text> <claim-text>40. Audio interface circuitry as claimed in claim 31 wherein the connector is an rf transmitter.</claim-text> <claim-text>41. Audio interface circuitry as claimed in any preceding claim further comprising bi-directional interface circuitry configured to transmit said data pulses generated by the pulse-length-modulator over a first communications link and receive pulse-length-modulated data pulses via said first communications link.</claim-text> <claim-text>42. Audio interface circuitry as claimed in claim 41 wherein the pulse-length-modulator is configured to transmit data pulses during a first portion the sample period and the bi-directional interface circuitry is configured to receive data pulse during a second, different portion of the sample period.</claim-text> <claim-text>43. Audio interface circuitry as claimed in claim 41 wherein the bi-directional interface circuitry comprises a drive circuit for voltage modulating the first communications link based on the data pulses and a read circuit responsive to the resultant voltage on the first communications link, wherein the read circuit is configured to subtract the drive voltage modulation from the resultant voltage signal.</claim-text> <claim-text>44. Audio circuitry comprising: an interface configured to receive a serial pulse-length modulated audio data input comprising a series of data pulses at a sample rate; data extraction circuitry configured to determine the pulse length of said data pulse and to determine a data value for each of a plurality of audio data streams from said pulse length.</claim-text> <claim-text>45. Audio circuitry as claimed in claim 44 comprising clock recovery circuitry configured to recover a first clock signal based on said sample rate.</claim-text> <claim-text>46. Audio circuitry as claimed in claim 45 wherein the data extraction circuitry is configured to sample the data pulse at a predetermined number of intervals within the period of the first clock signal to determine the pulse length of the data pulse.</claim-text> <claim-text>47. Audio circuitry as claimed in claim 46 wherein the data extraction circuitry comprises a delay line having a plurality of tap points.</claim-text> <claim-text>48. Audio circuitry as claimed in any preceding claim wherein the data extraction circuitry comprises at least a first data extraction module and a second data extraction module wherein the first data extraction module and the second data extractions module are configured to determine data values for different audio data streams to one another.</claim-text> <claim-text>49. Audio circuitry as claimed in claim 48 wherein said first data extraction module is configured to receive the input serial pulse-length modulated audio data from the interface and to pass said input serial pulse-length modulated audio data to the second data extraction module.</claim-text> <claim-text>50. Audio circuitry as claimed in claim 48 or 49 wherein each of the at least first and second data extraction modules are associated with respective first and second audio transducers.</claim-text> <claim-text>51. Audio circuitry as claimed in any of claims 44 -50 further comprising power circuitry configured to derive a power supply from said input serial pulse-length modulated audio data signal.</claim-text> <claim-text>52. Audio circuitry as claimed in claim 51 wherein the data extraction circuitry is powered by said power supply.</claim-text> <claim-text>53. A headset comprising audio circuitry as claimed in any of claims 44-52.</claim-text> <claim-text>54. Audio transceiver circuitry comprising audio interface circuitry as claimed in any of claims 1 -43 to send audio data-out and audio circuitry as claimed in any of claims 44 -53 to receive audio data-in.</claim-text> <claim-text>55. An audio system comprising audio circuitry as claimed in any of claims 1 -43 configured to transmit audio data for a plurality of audio channels to audio circuitry as claimed in any of claims 44-53.</claim-text> <claim-text>56. An integrated circuit comprising audio interface circuitry as claimed in any of claims 1 -43 and/or audio circuitry as claimed in any of claims 44-53.</claim-text> <claim-text>57. An electronic device comprising audio interface circuitry as claimed in any of claims 1 -43 and/or audio circuitry as claimed in any of claims 44-53.</claim-text> <claim-text>58. An electronic device as claimed in claim 57 wherein said device is at least one of: a portable device; a battery powered device; a communication device; a computing device; a personal media player; a music player; a mobile telephone; a docking station for a portable device; a headset; and a hearing aid.</claim-text> <claim-text>59. A method of transmitting audio data comprising, generating a pulse length modulated signal comprising a series of data pulses at a sample rate; wherein the length of each data pulse is dependent upon on a combination of then current audio data samples from said plurality of data streams.</claim-text> <claim-text>60. A method as claimed in claimed in claim 59 wherein said data streams comprise two or more 1-bit digital audio data channels.</claim-text> <claim-text>61. A method as claimed in claim 59 or claim 60 comprising generating said data pulses based on a first clock signal having a frequency equal to said sample rate.</claim-text> <claim-text>62. A method as claimed in claim 61 wherein generating the data pulses comprises generating a pulse having a length equal to a selected number of cycles of a second clock signal which has a frequency which is a multiple of the frequency of the first clock signal.</claim-text> <claim-text>63. A method as claimed in any of claims 59-62 wherein generating said data pulses comprises, for at least some combinations of input audio data, varying between at least two different alternative data pulse lengths.</claim-text> <claim-text>64. A method as claimed in claim 63 comprising alternating between said at least two different alternative data pulse lengths.</claim-text> <claim-text>65. A method as claimed in claim 63 comprising randomly selecting between said at least two different alternative data pulse lengths.</claim-text> <claim-text>66. A method as claimed in any of claims 63 to 65 wherein a plurality of combinations of input data can each be encoded as two different lengths of data pulse, the two lengths being symmetric about a predetermined length.</claim-text> <claim-text>67. A method as claimed in any of claims 59 to 66 further comprising receiving at least one additional data channel and generating the data pulses such that the length of at least some individual data pulses encodes audio data for said plurality of audio streams and also said additional data channel.</claim-text> <claim-text>68. A method as claimed in claim 67 wherein said additional data channel is a control data channel.</claim-text> <claim-text>69. A method as claimed in claim 67 or claim 68 comprising, in the absence of data on said additional data channel, varying between possible alternative pulse lengths that encode the same audio data combination.</claim-text> <claim-text>70. A method as claimed in claim 69 comprising generating the data pulses so as to encode a first reserved additional data sequence prior to transmitting any data of the additional data channel, wherein the first reserved additional data sequence is not used when no data is available on the additional data channel.</claim-text> <claim-text>71. A method as claimed in claim 69 or claim 70 comprising, at the end of transmission of any data on the additional data channel, transmitting a second reserved sequence of additional data.</claim-text> <claim-text>72. A method as claimed in any of claims 59 to 71 comprising transmitting said data pulses over a first communications link and receiving pulse-length-modulated data pulses via said first communications link.</claim-text> <claim-text>73. A method as claimed in claim 72 comprising transmitting data pulses during a first portion of said regular time interval and receiving data pulses during a second, different portion of said regular time interval.</claim-text> <claim-text>74. A method as claimed in claim 72 comprising transmitting data pulses and receiving data pulses simultaneously.</claim-text> <claim-text>75. An audio system for transferring audio data for a plurality of audio channels over a single wire connection comprising a pulse-length-modulator configured to produce a series of data pulses at regular intervals wherein the length of each data pulse encodes audio data for each of said plurality of audio channels.</claim-text> <claim-text>76. A data transfer system for transferring data for a plurality of separate data channels over a single wire connection comprising a pulse-length-modulator configured to produce a series of data pulses at regular intervals wherein the length of each data pulse encodes data from each of said plurality of audio channels.</claim-text> <claim-text>77. Audio interface circuitry comprising: a pulse-length-modulator responsive to audio data for a plurality of audio channels to generate data pulses at a regular time interval; wherein the length of the data pulses encode said audio data; and wherein the length of an individual data pulse encodes audio data for said plurality of audio channels.</claim-text> <claim-text>78. An audio interface for receiving and encoding a plurality of streams of 1-bit audio data samples and for transmitting a stream of encoded data pulses via a single communication link." 79. An audio interface for receiving and encoding a plurality of streams of 1-bit audio data samples and simultaneously transmitting on a clock edge of a stream of encoded data pulses a plurality of sampled 1-bit audio data samples via a single communication link.80. Audio interface circuitry as hereinbefore described with reference to Figures 2 - 18 of the accompanying drawings.81 An audio system comprising at least first and second audio components having a signal path between them such that data to be transmitted to or received from the second audio component is transmitted via the first audio component, wherein the first audio component comprises at least one of audio interface circuitry as claimed in any of claims 1 -43 to send audio data-out and audio circuitry as claimed in any of claims 44-53 to receive audio data-in.82 An audio system as claimed in claim 81 wherein said first audio component is configured to receive a serial pulse-length modulated audio data input comprising data for at least one audio component and to forward a signal to said second component.83. An audio system as claimed in claim 82 wherein said input signal comprises data for said first audio components and wherein the first audio component is configured to extract said data for said first component.84. An audio system as claimed in claim 82 or claim 83 wherein said first audio component forwards the serial pulse-length modulated audio data input signal received to the second audio component.85. An audio system as claimed in claim 82 or 83 wherein said first audio component forwards a modified serial pulse-length modulated audio data input signal received to the second audio component.86. An audio system as claimed in claim 85 wherein said first audio component modifies said forwarded serial pulse-length modulated audio data signal to encode data generated by said first audio component.87. An audio system as claimed in any of claims 81 -86 comprising a plurality of audio components with each audio component being connected to the next audio component in a chain.</claim-text>