GB2497566A - Simultaneous transmission of a plurality of audio data streams via a single communication link - Google Patents

Abstract

Audio interface circuitry comprises a pulse length modulator, PLM 103, for transfer of multiple digital audio data streams over a single communications link, such as a single wire. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L) of 1-bit audio data samples at a sample rate, to generate a stream of data pulses (MPDM) at the sample rate. The length of each said data pulse is dependent upon on a logical combination of the current audio data samples. The PLM may also be responsive to a first clock signal having a frequency equal to the sample rate, and a second clock signal having a frequency which is a multiple of the sample rate. The length of data pulses is preferably based on a selected number of cycles of the second clock signal. Circuitry for receiving and extracting the data is also disclosed. An interface 104 receives the stream of data pulses (MPDM) and data extraction circuitry 105, 106 determines the pulse length of said data pulse and determines a data value for each of the plurality of audio data streams.

Description

Data Transfer This application relates to methods and apparatus for data transfer, especially to transfer of multiple channels of digital audio data, and in particular to audio data transfer that can use a single communications channel.

In many electronic devices there is a need to transmit audio data signals, or other data signals, within the electronic devices, or to some peripheral device(s) that may be attached to the electronic devices, for instance a set of headphones. In many modern electronic devices, especially devices with SF transmission capability such as a mobile telephone or computing device, analogue audio signals are liable to be corrupted by electromagnetic interference (EMI) and coupling from other nearby circuitry. It is therefore desirable to transmit signals from an audio processing device! e.g. an integrated circuit audio hub/codec, to the driver of a transducer e.g. speaker, in a digital format so as to preserve the integrity and quality of the audio signal. For audio data there is also typically a requirement to send data for multiple channels, for instance left (L) and right (5) data channels for stereo audio.

Modern electronic devices such as smartphones, tablets and the like typically transmit digital audio data using three data wires plus a ground wire. The signal data for both L/R audio channels is typically sent on one wire in serial format, for example in words of 24 bits, with separate words being sent for the left (L) data channel and the right (5) data channel. The bit clock signal (BCLK) is sent on another wire and a further clock at the left/right words rate (LRCLK) sent on a further wire as illustrated in figure 1.

Alternatively, the audio data may be transmitted as a high-rate 1-bit stream, sometimes referred to as Pulse Density Modulation (PDM). Word-length reduction, noise shaping and/or delta-sigma techniques may be applied to reduce quantisation noise in the audio band at the expense of noise higher frequencies to reduce the required bit rate.

However, this still requires two wires, one for the data and one for the clock. Moreover, the digital data spectrum will include components corresponding to the base band audio signals, which may couple onto other analogue lines. Stereo data may be transmitted along one wire, typically alternating between sending left channel data and right channel data, but the separate clock line is still needed and the spectrum may still present similar problems.

It is therefore an object of the present invention to provide methods and apparatus for data transfer of multiple data channels that at least mitigate some of the aforementioned disadvantages.

Thus according to the present invention there is provided audio interface circuitry comprising: a pulse-length-modulator, responsive to a plurality of data streams of audio data samples at a sample rate, to generate a stream of data pulses at said sample rate; wherein the length of each said data pulse is dependent upon on a combination of the then current audio data samples from said plurality of data streams.

The audio data streams may comprise 1-bit digital audio data streams and may correspond to audio data channels which may be separate channels, such as left and right stereo data channels.

The pulse-length-modulator (PLM) may be responsive to a first clock signal having a frequency equal to said sample rate. The PLM may further be responsive to a second clock signal, the second clock signal having a frequency which is a multiple of the frequency of the first clock signal, which may be at least five times and may be at least eight times the frequency of the first clock signal. The length of each data pulse may be based on a selected number of cycles of the second clock signal.

The minimum data pulse length may be a plurality of cycles of the second clock signal and the maximum data pulse length may be shorter than the period of the first clock signal by a plurality of cycles of the second clock signal The PLM may be configured so that at least one combination of input audio data can be encoded as at least two different alternative data pulse lengths. The PLM may vary between said at least two different alternative data pulse lengths, for instance by alternating between said at least two different alternative data pulse lengths or by randomly selecting one of the alternative data pulse lengths. The variation may be arranged to control the average data pulse length for all instances of a given combination of input audio data and this may apply to a plurality of possible combinations of input data.

A plurality of combinations of input data may each be encoded as two different lengths of data pulse, the two lengths being symmetric about a predetermined length. One combination of input data may be encoded as a data pulse having a length substantially equal to said predetermined length.

The PLM may also receive at least one additional data channel and the length of at least some individual data pulses may encode the then current audio data samples from said plurality of data streams and also the then current data sample for said additional data channel. The additional data channel may be a control data channel.

When no data is received on the additional data channel the PLM may vary between pulse lengths that encode the same audio data combination. A series of data pulses with a first reserved sequence may be used prior to encoding any additional data, where the first reserved sequence corresponds to the encoding that would be used for a particular data sequence on the additional data channel and it is not used when no data is available on the additional data channel. When data on the additional channel stops the PLM may encode a second reserved sequence of additional data.

The FLM may comprise a combiner for producing a combined data value from each of said audio data streams and may comprise a counter arranged to count at a frequency of the second clock signal and a comparator for comparing the count value to the combined data value.

The PLM may produce an output which varies between a first non zero voltage and a second non zero voltage.

The rising edges of the data pulses may be separated by a regular time interval equal to the sample period or it may be the falling edges of the data pulses.

The output from the pulse-length-modulator may be connected to an audio signal path on a printed circuit board of a host device or to a connector of a host device, such a socket, and may comprises connections for some or all of audio data-out, audio data-in, power and ground. The power connection may also serves as the audio data-out connection and/or the audio data-in connection may also serve as the audio data-out connection. The connector may be a connector fora headset. In use the PLM may provide audio data and power to a peripheral connected to said connector. The connector could be an optical connector or an rf transmitter.

The audio interface circuitry may comprise bi-directional interface circuitry configured to transmit said data pulses generated by the PLM over a first communications link and receive pulse-length-modulated data pulses via said first communications link. The PLM may be configured to transmit data pulses during a first portion of the sample period and the bi-directional interface circuitry is configured to receive data pulse during a second, different portion of the sample period. The bi-directional interface circuitry may comprise a drive circuit for voltage modulating the communications link based on the data pulses and a read circuit responsive to the resultant voltage on the first communications link, wherein the read circuit is configured to subtract the drive voltage modulation from the resultant voltage signal.

In another aspect of the invention there is provided audio circuitry comprising: an interface configured to receive a serial pulse-length modulated audio data input comprising a series of data pulses at a sample rate; and data extraction circuitry configured to determine the pulse length of said data pulse and to determine a data value for each of a plurality of audio data streams from said pulse length.

Clock recovery circuitry may be configured to recover a first clock signal based on said sample rate. The data extraction circuitry may sample the data pulse at a predetermined number of intervals within the period of the first clock signal to determine the pulse length of the data pulse and may comprise a delay line having a plurality of tap points.

There may be at least a first data extraction module and a second data extraction module, the data extraction modules determining data values for different audio data streams to one another. The first data extraction module may receive the input serial pulse-length modulated audio data from the interface and pass it to the second data extraction module. The first and second data extraction modules may be associated with respective first and second audio transducers.

There may also be power circuitry to derive a power supply from the input serial pulse-length modulated audio data signal. The data extraction circuitry may be powered by such power supply.

Audio transceiver circuitry may audio interface circuitry for sending audio data-out and audio circuitry to receive audio data-in.

Embodiments of the invention may be implemented as an audio system having circuitry configured to transmit audio data for a plurality of audio channels to audio circuitry for receiving the data.

The audio circuitry may be implemented as an integrated circuit and/or in an electronic device. The device may be at least one of: a portable device; a battery powered device; a communication device; a computing device; a personal media player; a music player; a mobile telephone; a docking station for a portable device; a headset; and a hearing aid.

The invention also relates to a method of transmitting audio data comprising, generating a pulse length modulated signal comprising a series of data pulses at a sample rate; wherein the length of each data pulse is dependent upon on a combination of then current audio data samples from said plurality of data streams.

The method may be implemented in any of the embodiments as described above.

In another aspect of the invention there is provided an audio system for transferring audio data for a plurality of audio channels over a single wire connection comprising a pulse-length-modulator configured to produce a series of data pulses at regular intervals wherein the length of each data pulse encodes audio data for each of said plurality of audio channels.

The invention also provides a data transfer system for transferring data for a plurality of separate data channels over a single wire connection comprising a pulse-length-modulator configured to produce a series of data pulses at regular intervals wherein the length of each data pulse encodes data from each of said plurality of audio channels.

In a further aspect of the invention there is provided audio interface circuitry comprising: a pulse-length-modulator responsive to audio data for a plurality of audio channels to generate data pulses at a regular time interval; wherein the length of the data pulses encode said audio data; and wherein the length of an individual data pulse encodes audio data for said plurality of audio channels.

The invention also provides an audio interface for receiving and encoding a plurality of streams of 1-bit audio data samples and for transmitting a stream of encoded data pulses via a single communication link." In a further aspect there is provided an audio interface for receiving and encoding a plurality of streams of 1-bit audio data samples and simultaneously transmitting on a clock edge of a stream of encoded data pulses a plurality of sampled 1-bit audio data samples via a single communication link.

The invention will now be described by way of example only with reference to the following drawings, of which: Figure 1 illustrates a prior art three-wire data transfer protocol for stereo audio data; Figure 2 illustrates a data transfer system according to an embodiment of the present invention; Figure 3 illustrates example data waveforms on the various signal lines of the embodiment illustrated in Figure 2; Figure 4 illustrates one embodiment of a suitable audio transmitter; Figure 5 illustrates example waveforms on the various signal lines of the transmitter embodiment illustrated in Figure 4; Figure 6 illustrates one embodiment of a suitable audio data receiver; Figure 7 illustrates example waveforms on the various signal lines of the receiver embodiment illustrated in Figure 6; Figure 8 illustrates one example of an encoding scheme which allows data input combinations to have alternative possible encodings; Figure 9 illustrates a data transfer system according to another embodiment of the present invention; Figure 10 illustrates another example of an encoding scheme; Figure 11 illustrates an embodiment of interface circuitry for sending pulse-length-modulated data over a single data link; Figure 12 illustrates the waveforms on the various signal lines illustrated in Figure 11; Figure 13 illustrates another embodiment of interface circuitry for sending pulse-length-modulated data over a single data link; Figure 14 illustrates an application of an embodiment of the invention; Figure 15 illustrates an application of another embodiment of the invention; Figure 16 illustrates an application of a further embodiment of the invention; Figure 17 illustrates an application of another embodiment of the invention; and Figure 18 illustrates an application of a yet further embodiment of the invention; Figure 2 illustrates an embodiment of a data transfer system for transferring multiple simultaneous channels of data over a single link. In this example stereo audio data is transferred over a single wire, i.e. conductive path 111, between a first component 101 and a second component 102. The first component 101 may be audio interface circuitry that is incorporated as part of an audio codec or a digital signal processor of a host device for example. The second component 102 may be audio interface circuitry, for example as part of transducer driving circuitry. The second component 102 may be part of the same host device as the first component 101 and thus the link 111 may comprise a trace on a PCB of the host device or other permanent wired connection.

Alternatively the second component 102 could be part of a separate device to the first component 101. For example the first component 101 could be located in a media player or mobile telephone or the like and the second component 102 could be pad of a second device, for example a peripheral device, that is coupled in use such as a headset or docking station or the like. In this case the link 111 may comprise a conductive path involving a suitable connection (not shown) such as a plug and socket.

In further embodiments the first and second components may both be implemented on the same integrated circuit, and the link is an on-chip connection, to reduce the width of interconnect bussing between blocks. Various applications of the embodiments of the present invention will be described in more detail later.

The audio interface circuitry of the first component 101 has a pulse-length-modulator (PLM) 103 which receives audio data input data, PDM-R and PDM-L, for the left and right audio channels. In this example the L/R input data are separate 1-bit (i.e. PDM) digital input data streams for each channel, i.e. left channel and right channel. At regular intervals, for instance in each period of a first clock signal CK (which preferably matches the sample late of the L/R 1-bit audio data input) the PLM generates a data pulse with a length that depends on the logical combination of LIR input audio data.

For left and right 1-bit audio data inputs there are four possible combinations of input data and the PLM 103 generates a data pulse having a length (i.e. duration) which varies according to the output of the particular LIR input data combination, as illustrated

in table 1 below.

PDM-L Value PDR-R Value PDM Combined Pulse length (TFCK) value 0 0 00 1 0 1 01 2 1 0 10 3 1 1 11 4

Table 1

The pulse length is preferably determined as a multiple of a clock period of a second clock signal, FCK, which has a frequency which is a multiple of the first clock signal CK. It will be clear that the frequency of the second clock signal FCK should be at least four times the frequency of the first clock signal CK and is preferably at least five times the frequency of the first clock signal to allow for a pulse length of 4TFCK within each period of the first clock signal and also allow a gap between pulses to ease downstream clock recovery.

Figure 3 illustrates the first clock signal CK and second clock signal FCK, which in this example has a frequency five times that of the first clock signal CK. Figure 3 also illustrates that in each period of the first clock signal CK the right and left input data streams PDM-L and PDM-R will each have a data value of 1 or 0 depending on their respective current data i.e. logic levels. The resulting MPDM data signal, generated to represent a logical combination of LIR input audio data as per table 1, is also illustrated. This comprises a series of data pulses, at the frequency of the first clock signal CK, where the length of each individual data pulse encodes a data value for the left audio channel and also a data value for the right audio channel.

It will be noted that there is always one data pulse per period of the first clock signal CK and that the data pulses are arranged so that there is always a gap between data pulses. This means that the data signal MPDM can itself be used to recover the first clock signal CK by the receiving interface circuitry. In the example shown, the rising edges of the clock signal are separated by the clock period but the skilled person will appreciate that the falling edges could instead be synchronised to the first clock signal CK.

Referring back to Figure 2 the output from the PLM 103 is transmitted as data signal MPDM to the second component 102. The audio interface circuitry of the second component 102 has an interface 104 for receiving the data signal. In this example the interface 104 comprises a two way divider that allows copies of the data signal MPDM to reach a first data extraction module 105 and a second data extraction module 106.

The first data extraction module 105 extracts the first clock signal from the data signal.

As mentioned above the period between the rising (or alternatively the falling) edge of each data pulse indicates the first clock period. The first data extraction module 105 then determines the length of each data pulse and uses this to determine the audio data for the left audio channel. From table 1 above it can be seen that pulse lengths of 1 or 2 times the second clock signal FCK indicate a data value of 0 for the left channel and pulse lengths of 3 or 4 times the second clock signal ECK indicate data 1 for the left audio channel. Given that the second clock signal is a known multiple of the first clock signal frequency the relevant length of the data pulse can therefore be determined. Likewise the second data extraction module 106 determines the first clock signal and also determines the length of the data pulse to determine the data value for the right audio data channel. In this instance a pulse length of 1 or 3 times the second clock signal indicates a data value of zero for the right channel and a pulse length of 2 or4 indicates a data value of 1.

Each of the first and second data extraction modules therefore outputs a version of the first clock signal CK and a 1-bit data (PDM) signal for the relevant audio channel.

These signals can be passed to respective DAC-amplifiers 107, 108 to drive respective loudspeakers 109 and 110.

Figure 2 shows separate data extraction modules 105, 106 for each channel, associated with the relevant DAC-amplifier 107, 108 and speaker 109, 110 for each channel. In a device having internal stereo speakers the speakers may typically be separated and arranged to receive signals from an audio source such as codec and thus the arrangement shown in Figure 2 may be preferred. In this case the data extraction module for each channel 105, 106 may be integrated with the respective DAC-amplifler 107, 108 for that channel. In other arrangements however, instead of separate data extraction modules for each channel a single data extraction module could be used to extract the data for more than one channel.

Figure 3 illustrates that the data signals PDM-RX and PDM-LX, respectively extracted by the first and second data extraction modules 105, 106, are the same as the respective input data PDM-R and PDM-L.

This embodiment of the present invention therefore supplies simultaneous audio data for multiple audio channels using only a single communication link, i.e. a single data wire, without requiring any clock signals to be sent.

Figure 4 illustrates one example of a suitable pulse-length-modulator (PLM) 103 that may be used as part of an audio interface. As illustrated the PLM has a combiner 401 that receives the two input 1-bit data streams, PDM-L and PDM-R. The combiner 401 converts the input data to a 2-bit combined data stream PDM-C (as described above in relation to table 1). A counter 402 is also arranged to receive the first and second clock signals OK and ECK respectively. The second clock signal FCK is arranged to clock the counter to increment and the first clock signal is provided at the reset input. Thus each period of the first clock signal the counter will increment at the rate of the second clock signal. The output is thus is a sawtooth ramp waveform that is reset to zero at the start of each period of the first clock signal (or alternatively the counter could be arranged to count down from a certain starting level each period).

The output of the combiner 401 and counter 402 is compared by comparator 403 which is clocked at the second clock frequency FCK, and is configured to give a high output if RAMP is greater than the combined signal PDM-C. At the first relevant (e.g. rising) clock edge of FCK after the counter has reset, the RAMP signal will be zero, and the combined signal will be zero or greater, so the output of the comparator goes high at the beginning of the first relevant edge of FOK in each period of the first clock signal. At successive FCK edges, the RAMP signal will have increased: the comparator output goes low when the ramp signal has exceeded the combined data value. This results in a data pulse where the rising edge is synchronised to the first clock signal (i.e. the rising edge of each data pulse occurs at the first relevant FCK edge after the rising edge of the CK clock signal) and the pulse length depends on the combined data value. It will of course be appreciated that the comparator could be arranged so that the output goes low at the start of the clock period and goes high only as a result of the comparison to synchronise the falling edges of the data pulses.

Figure 5 illustrates the various data waveforms and shows how the comparison of the combined data value PDM-C with the ramp signal can generate the MPDM data signal.

It should be noted that the PLM described with reference to Figure 4 acts on 1-bit PDM input data streams. In some embodiments there may be a need to convert an audio data stream for an audio channel into a 1-bit PDM data stream before it is input to the PLM. For example if input analogue audio data from a microphone or other analogue source is received there may be a need to convert it to a 1-bit PDM digital data stream.

Alternatively if audio data is received or stored in multi-bit PCM format there may be need to convert the audio data words into a 1-bit PDM stream using known conversion techniques. Thus referring to figure 2 first component 101 may comprise conversion circuitry (not shown) for converting an input audio stream into a 1-bit PDM stream which is then provided to the PLM 103.

However in some embodiments the PLM may be arranged to receive multi-bit input data for one or more audio data channels. For example consider left and right stereo data where each channel comprises two-bit digital audio data. This means that each clock period there may sixteen possible combinations of audio data. If the second clock signal is arranged to have a frequency which is at least seventeen times that of the first clock signal the sixteen possible combinations may therefore be encoded by sixteen different pulse lengths. The principle of operation is the same, for example a four-bit combined data signal representing the state of both input channels may be produced and compared to a counter ramp that increments at the rate of the second clock signal. Clearly this could be extended to digital signals of higher numbers of bits but with a consequent increase in the number of different pulse lengths required and a corresponding increase in the speed of the second clock signal compared to the first clock signal, which may require very fast components and accurate resolution between relatively small differences in pulse length. Another example is 3-level data as used for control of Class-D H-bridge output stages! requiring nine possible pulse lengths for a stereo pair.

Other techniques for pulse length modulation in general, for example using delay-locked loops (DLL) are known and could be adapted for use in embodiments. Also it should also be noted that the first and second clock signals could be received by the PLM 103 or one or both of these signals may be generated by the PLM. For instance the FLM may receive the first clock signal, for example as a clock accompanying and synchronous to the FDM data and generate the second clock signal or the PLM may receive no clock signals and may recover the first clock signal from the input data using known clock recovery techniques.

Figure 6 illustrates one embodiment of suitable data extraction module 105 or 106. In this embodiment, the clock signal is recovered using a Delay-Locked-Loop (DLL) comprising a voltage-controlled delay line 601, itself comprising a chain of voltage-controlled delay elements 602, together with a phase-frequency detector (PFD) 603, charge pump 604 and loop filter 605 as known. The DLL receives the MPDM signal and the PFD 603 is designed suitably so that each rising edge of delay line output SYNC is locked to a rising edge of the incoming MPDM stream. Thus the delay along the delay line becomes equal to a period of the original OK clock.

The duty cycle of SYNC will vary with the data carried on MPDM. To establish a clock with 50% duty cycle, SYNC is applied to the set input S of an edge-triggered RS flip-flop 606, while a signal y5 from half way along the delay line is applied to the reset input.

To extract a measure, PL, of the length of each transmitted MPDM data pulse, the data at a number of equally spaced taps of the delay line 601 is summed in a summer 607.

The delay taps are arranged to sample the signal at intervals equal to the second clock frequency ECK and in sufficient number to be able to discriminate between the number of different possible pulse lengths. In this embodiment, where the second clock frequency is known to be five times the frequency of the first clock signal and there are four possible different pulse lengths, there are five delay taps at equal spacings along the delay line.

The determined data pulse length value PL is then applied to a look-up table 608 or equivalent logic to decode the MPDM signal in the relevant PDM audio data channel or channels. In the embodiment illustrated in Figure 2, where there is a different data extraction module for each data channel, respective logic inputs LR are tied to ground or VDD to signify left or right channel. This signal LR representing whether PDM-L or PDM-R is to be extracted may also be applied to the look-up table to determine the appropriate data value. Alternatively a multiplexer between the MSB and LSB of the two bit PL data value, driven by LR, may be used to select the appropriate data output.

In other embodiments, especially with more than two receiving channels, alternative methods of identifying each receiver may be implemented and used to extract appropriate data using suitably adapted truth tables.

The look-up table contains a truth table such as shown in table 2 below.

PL LR PDM-L PDM-R

00 0 -0 01 0 -1 0 -0 11 0 -1 00 1 0 - 01 1 0 - 1 1 - 11 1 1 -

Table 2

It will be appreciated however that in other embodiments a single data extraction module may be used to extract both the PDM-R and PDM-L together.

It will be noted that this detection method does not require explicit recovery of the second clock signal FCK (or any clock signal faster than the fist clock signal). However if this is required, for instance for other circuitry, such a clock may be generated by logical combination of the tapped outputs yl to y9 as known. The recovered first or second clocks may be used for other functions in the device. Indeed the rising (or even both) edges of the unprocessed MPDM signal may be used as a clock edge.

Figure 7 illustrates the MFDM input signal that would be received for the various possible data combinations, how the first clock signal CKX can be recovered and how the output of the delay tap y5 can set a 50:50 duty cycle for the clock signal. These waveforms also shows how the outputs of the delay taps yl to y9, when summed, provide an indication of the length of the data pulse which can then be used to extract the PDM-R and PDM-L audio data streams.

In correct operation, the sampled output of the first delay tap yl is always 0 and the sampled output of the last delay tap y9 is always 1. This can be used to generate a flag indicating collect operation i.e. lock of the DLL loop and correctly formatted input data.

In this case it can then be noted that the value of FL only varies due to the contribution of delay taps {y3. y5 and yl}. If the value FL were produced by summing just the output of these three delay taps then the values of PDM-L and/or PDM-R can then be selected merely as the MSB and LSB bits of PL, as illustrated in Table 2.

The embodiments described above relate to two channels of audio data, e.g. left and right stereo data. However it will be appreciated that the principle can be extended to more channels of audio data, for example for surround sound. For example if there were four channels of audio data, left-front, left-rear, right-front, right-rear and each data channel was a 1-bit PDM data stream then the combined data would comprise a 4-bit data signal which could be encoded by 16 different pulse lengths.

In the embodiments described above the number of possible pulse lengths that can be produced by the pulse-length-modulator has been set to simply provide unique encoding for each possible input data combination, i.e. the period of the first clock signal has been divided into an equal number of time slots sufficient to allow unique encoding. However in some embodiments of the invention the number of possible time slots may be greater than is required just for unique coding of the audio data channels.

These extra slots can be used to provide a number of additional features and advantages.

In one embodiment the PLM may be arranged so that at least one combination of input audio data for the left and right audio channels can be encoded as at least two different alternative data pulse lengths. In other words a particular combined data value, say 10, may be encoded as a first pulse length or alternatively as a second, different, pulse length.

Varying the pulse lengths can help reduce problems with EMI by effectively whitening the data signal spectrum. Thus the PLM may be arranged to use the first pulse length to encode one instance of the combined data value and the second pulse length to encode a later instance of the same combined data value. In other words the PLM may vary between the two different alternative data pulse lengths when encoding a given combination of input audio data. In one embodiment the FLM may simply alternate between the possible different encodings but in other embodiment the PLM may be arranged to select between the alternative encodings at random.

In one embodiment the PLM is arranged to vary between the possible encoding pulse lengths so as to control the average pulse length of all instances of a particular combination of input data.

Advantageously for any possible combined data values that have alternative possible encodings the possible encodings may be symmetric about a given pulse length.

Figure 8 illustrates a period of the first clock signal which is divided into eight separate time slots, i.e. the frequency of the second clock signal is set to be eight times that of the first clock signal so that there are seven possible pulse lengths (it will be recalled that a pulse length using all eight time slots is not used to ensure a gap between data pulses, to allow simple clock recovery using the rising edge thus available at each first clock period). The input data combination 11 (i.e. data 1 on the left channel and data 1 on the right channel) may be encoded as a pulse length of four time slots (illustrated as position 3). This encoding may be the only option for an input data combination 11. All the other possible input data combination values, 10,01 and 00 however may each be encoded as two possible pulse lengths. In each instance, as illustrated, the pulse lengths may be symmetric about a given pulse length. Thus input combination 00 may be encoded as a pulse of one time slot in length (position 0) or 7 times slots in length (position 6).

In this example the various alternative pulse lengths are symmetric about a pulse length that is half the interval between pulses (which may give advantages for DC balance in some implementations). However this does not need to be the case and where there more time slots available any desired pulse length may be chosen that has sufficient time slots on either side.

The truth table that the PLM uses to encode the input data to pulse length may therefore be based on that set out in table 3 below.

Left data Right Data R value position o 0 0 0 o 1 0 1 1 0 0 2 1 1 0 3 o 0 1 6 o 1 1 5 1 0 1 4 1 1 1 3

Table 3

The R value is used to control which alternative encoding is used for those input data combinations which have alternative encodings. If a respective R value is simply alternated between successive occurrences of each input code pair, the average pulse length will be constant, irrespective of the input data.

It may be good enough merely to alternate a common R in alternate clock cycles, assuming random input codes. However in some embodiments the R value for each input code pair or a common R value is generated as a random (or pseudo random) sequence. This ensures that the output signal spectrum is whitened.

The receiver would need to be able to distinguish between seven different pulse lengths and thus could be implemented with a delay line having 16 elements and 8 taps. A different look-up table would also clearly be required.

In another embodiment redundant time slots may be used to encode at least one additional data channel or side data channel. In other words the PLM may be arranged so that at least some data pulses encode not only multiple audio channels but also at least one additional data channel. The additional data channel may, for instance comprise control data for controlling aspects of the audio apparatus. For instance audio control data for enabling or disabling mute or one of several standby or low-EMI modes, or controlling volume may be transmitted.

The additional data may be encoded as a separate data channel as described above.

Thus with two 1-bit PDM audio data channels, e.g. left and right audio data, and a 1-bit control data channel, the eight possible unique data combinations of audio and control data could be encoded as eight different pulse widths, requiring the clock period to be divided into nine separate time slots. Thus the frequency of the second clock signal could be set to be at least nine times that of the first clock signal.

However whilst it is certainly possible to derive a second clock signal to provide any desired number of time slots in the period of the first time clock signal it is noted that it most convenient to generate 2N time slots, i.e. to derive a second clock frequency which is 2' times the first clock frequency. This would provide 2N1 possible pulse lengths. Thus providing sufficient time slots to encode both the two audio data channels and the control data channel in each data pulse, with convenient generation of the second clock signal, would involve generating 16 (i.e. 2) time slots -with the associated requirements for fast circuitry.

It has been realised however that the data rate required for additional data such as control data may be lower than that required for the audio data channels. Thus in one embodiment some, but not all, data pulses may also be encoded with additional data.

Provided that the number of possible pulse lengths is at least one greater than the minimum needed to uniquely encode the audio data channels then at least one particular input combination of audio data can be encoded in two alternative ways and any instances of such audio data combination can thus be used to transfer the additional data.

Thus consider two 1-bit PDM audio data channels, for instance left and right stereo audio data. As described previously a combined signal representing both audio channels will thus be a two bit signal and will require four possible pulse lengths for unique encoding of the audio data. This would require at least five time slots in each period of the first clock signal. As also mentioned it may be more convenient to generate eight time slots (i.e. 2 time slots) rather than five, thus providing seven possible pulse lengths. As only four pulse lengths are needed to encode the audio data this leave three possible pulse lengths that can be used as alternatives encodings for the audio data. This means that three out of the four possible audio data combinations can be used to transmit additional data.

For example encoding could be performed according to the following table: Left audio data Right audio Data Control / side Pulse length (TreK) channel data o 0 0 1 o 1 0 2 1 0 0 3 1 1 N/A 4 O 0 1 7 0 1 1 6 1 0 1 5 1 1 N/A 4

Table 4

Thus a pulse length of 1TFOK indicates an input audio data combination 0100 and a control data value of 0 whereas a pulse length of 7TFCK indicates an input audio data combination of 00 but a control data value of 1. However the audio input data combination 11 is only be encoded as one possible pulse length, equal to 4TFCK.

Therefore any instances of the input audio data combination 11 means that the particular data pulse can not also be used to encode the control data.

Assuming the input audio data combinations provide effectively random sequences this still allows an average of 0.75 control bits per symbol of the MPDM data which is sufficiently high for most control data, although clearly there is a code dependent latency. This code dependence may be mitigated by re-coding the audio input data stream to reduce the density of 11 states by known methods, for example bit flipping techniques.

Figure 9 illustrates an embodiment including control data transfer. In this embodiment pulse-length-modulator (PLM) 901 receives left and right audio data as 1-bit PDM signals as described previously but also receives control data CDATA. The PLM 901 is responsive to first clock signal CK and second clock signal FCK which is eight times the frequency of the first clock signal. The PLM may implement the encoding shown in

table 4 above.

In one embodiment the audio data may be combined together with the control data value to provide a pulse length data value in accordance with the table 4 above. The pulse length data value may be compared with a sawtooth ramp signal that increase each time slot as described previously.

The data extraction modules 902 and 903 operate as described previously to extract the clock and relevant audio data signals except that the truth tables include indications of the value of control data for all pulse lengths other than 4TFGK. The extracted control data can then be used to control DAC-amplifiers 904, 905 respectively.

In some embodiments control data may only need to be transmitted infrequently.

When no control data needs to be transmitted the control data signal could be effectively be set to be a constant string of zeros (or ones). However in one embodiment when there is no control data to be transferred the PLM 901 may be arranged to vary between the alternative encodings for the audio data input combinations as described previously with respect to figure 8 in order to whiten the signal data spectrum and provide the EMI benefits mentioned above.

The FLM may therefore be arranged such that, when no control data is present, those audio data combinations that can be encoded by alternative pulse lengths are varied between the alternative encodings -either alternated or selected randomly as noted previously. Advantageously, as previously noted the two possible encodings for a given audio combination have pulse lengths which are symmetrical about a given pulse length. When subsequently control data is available the PLM may then encode the control data as described.

In this arrangement the receiver will need to be aware whether the variation between two alternative possible pulse lengths for a given audio combination is simply random variation for the purposes of reducing EMI issues or whether the encoding represents control data which has been encoded into the data pulse.

Therefore in this embodiment there is at least a first reserved sequence of control data modulation which the PLM is arranged not to use when not transmitting control data.

The receiver may decode each data pulse as if it were encoding control data and look to see whether the reserved control data pattern occurs. If not the receiver will ignore the control data encoding as being random variation implemented by the PLM.

However if the reserved data sequence is received in the control data encoding the receiver will then treat subsequent control data encoding as genuine control data.

When the PLM then reaches the end of the control data to be transmifted it may send a second reserved sequence of control data (which may be the same or different to the first reserved sequence) to indicate that the control data has ended. After the second reserved sequence has been encoded the PLM may then return to varying between the possible alternative pulse lengths for EMI management reasons. The receiver, after detecting the second reserved sequence will stop treating the encoded control data as genuine control data and disregard the control data encoding unless and until another instance of the first reserved sequence is detected.

In some embodiments, especially for higher-speed links, where rise/fall times may be significant and may be further degraded in transmission along the wires, it may be advantageous to ensure that the shortest pulse length that can be used has a certain minimum width. For instance rather than allow the shortest possible pulse length to be equal to 1TFCK it may be beneficial to ensure that the shortest pulse width is, for example 2TFCK As shown in Figure 10 if the frequency of the second clock signal is eight times that of the first clock signal then there are eight time slots and, as shown in plot (a), there may be seven possible positions at which a pulse may end, leading to seven possible pulse widths. However to ensure satisfactory detection of the pulse the minimum pulse width may be set to be equal to two time slots and hence there may be only six possible pulse widths -positions 0 to 5 shown in plot (b). There may also be advantages in ensuring a minimum gap between the end of a pulse and the start of the next pulse, e.g. there may be a minimum gap equal to two time slots -either in combination with an extended minimum pulse duration leading to five possible pulse widths as shown in plot (c) or instead of an extended minimum pulse duration, plot (d).

It should also be noted that the minimum pulse length and/or minimum gap between pulses could be some other value, such as 1.5 times the second clock period as shown in plot e.

The PLM could be arranged to produce such minimum periods by adjusting the values and delay of the ramp signal for instance and the receiver would simply arrange the delay taps at appropriate points and with an appropriate look-up table or equivalent.

Embodiments of the present invention therefore allow multiple data channels to be transmitted over a single link with the possibility of alternative encodings being available for at least some combinations of input data, which can be used to reduce the EMI effects by whitening the data signal spectrum and/or allowing transfer of additional data, such a control data, possibly at a reduced data rate. The embodiments described have discussed transfer of data in one direction only, from component 101 to component 102. In many applications however there may be a need to transfer data in both directions. There may therefore be a first link for data to be transferred in a first direction, say from a first device to a second device, and a second link for data to be transferred in the other direction, from the second device to the first device. If the data to be transferred in both directions comprises multiple channels then each of the first and second devices may comprise audio interface circuitry for transmitting data such as PLM 103 and audio interface circuitry for receiving data such as data extraction module 105 and/or data extraction module 106.

In some embodiments however the same link may be used for data transfer in both directions. Figure 11 shows one embodiment of bi-directional interface circuitry that allows multi-channel PDM data to be transferred in both directions over the same link 1101. First bi-directional interface circuitry 1102 is arranged to receive a first pulse-length-modulated signal MPDM-1 for transmission over the link 1101 and to extract a second pulse-length-modulated signal MPDM-2 that has been received over the link 1101 for onward transmission. Bi-directional interface circuitry 1103 does the same but in reverse.

In each of the first and second bi-directional interfaces circuitry drives switched currents dependent on MPDM-1 or MPDM-2 onto that end of the link 1101.This link has a fixed impedance (at one or both ends) to a reference voltage VR which may, for instance by VDD/2. Both signals MPDM-1 and MPPDM-2 therefore provide a resultant voltage on the link 1101 as illustrated in Figure 12. The bi-directional interface circuitry is then arranged to subtract the signal transmitted from that end from the resultant voltage, thus ensuring that the inbound signal derived from each bi-directional interface circuit is just that which was transmitted at the far end.

In another embodiment, as illustrated in Figure 13, a single link 1301 could be used as a time-multiplexed bus. Thus with a period of a first clock signal there may be a first period of N clock cycles of a second, higher rate clock signal ECK for data transmission in one directions and a period of M clock cycles of the second clock signal FCK for transmission of data in the other direction. Thus the transmitter at one side of the link, say the PLM 1302, may transmit a pulse-length-modulated data signal based on the input data channels PDM-1 A and PDM-1 B where the pulse length is varied between 1 and N of the second clock cycles. At the end of the N cycles the output from the PLM 1302 is made high impedance and the PLM 1303 at the other end of the link starts transmitting its pulse-length-modulated signal for a selected number of the M remaining cycles. The ratio of N to M may be 50:50 or may depend on the number of channels of data being transferred in each direction. The right hand side receiver passes data to the data extraction circuitry 1304 only when its transmitter is disabled (set to high impedance). The data extraction circuitry 1304 recovers the clock signal OK and may also determine the second clock signal ECK, as described earlier, both of which are supplied to the PLM 1303. The pulse length of the received data can then be used to determine the output audio data PDM-1A and PDM-1 B. The left hand data extraction circuitry 1305 operates in the same way except that clock recovery is not needed as the relevant clock signals are available. The bus keeper or bus holderl3O6 operates to keep the link line 1301 stable (i.e. low) in underlap when both drivers are high impedance.

It should be noted that the embodiments described above have described the data link as a conductive path. However the link could be provided by any suitable means of data exchange. For instance an optical (for example infra-red) data link could be provided via a suitable waveguide, such as an optical fibre or the like, or may simply be transmitted into free space, e.g. for a wireless headphone. In such an embodiment the PLM may comprise an optical source for producing a length modulated optical pulse and the receiver may comprise an optical detector. The optical link may comprise a suitable optical detector and as mentioned the link may comprise optical waveguides or be at least partly achieved through free space. Part of the optical link may be implemented in an optical circuit board. Alternatively the link could be provided by RF transmission and thus PLM may comprise a suitable transmitting antenna for generating length modulated RF transmissions and the receiver may comprise a receiving antenna. The link may comprise various different types of transmission medium and may comprise components for converting one type of MPDM signal, say a voltage pulse-length modulated signal on a conductive path into another type of MPDM signal say an optical pulse-length-modulated signal in an optical waveguide for

example.

In some applications, where a destination device for the transmitted audio signals does not have its own power source it will be necessary to transfer power as well as the data. Thus, although the data for multiple audio channels may be transmitted via single data link it may be necessary to also have at least a power supply link and a ground link. Where there is two way data exchange there may also be separate data links for outbound and inbound data. However in some embodiments! especially when the MPDM signal comprises voltage pulse-length-modulated signals, the data signal may also be used to transfer power. Various techniques are known for deriving a power supply voltage from a data supply, for example using a simple diode or synchronous switching circuitry. When the data link is also used to transfer power the voltage on the data line may be arranged to vary from a first non-zero voltage to a second non-zero voltage to indicate the data pulses. In this way the signal line is never at zero voltage. However given that with embodiments of the present invention there is always at least one data pulse per cycle and there may be a minimum pulse period or controlled average pulse period (which may be equal to half the clock cycle) it would be possible to derive a suitable supply voltage even if the data pulses vary between a first non-zero voltage and ground.

Figures 14 to 18 illustrate some example applications of the embodiments of the present invention as applied to headsets, i.e. headphones or earbuds or the like which may or may not include microphones for voice data transfer or active noise cancellation.

Figure 14 illustrates a two way data exchange between a DSP or codec 1401 of a first device 1402, such as a personal media player, gaming device or mobile telephone, to a headset 1403 via interface circuitry 1404. In this embodiment there is two way data exchange (MPDM_UP and MPDM_DOWN). The headset may have interface module 1405 which receives the MPDM_UP data signal, as well as separate power and ground links, and which transmits the MPDM DOWN signal. The device 1402 may therefore connect to the headset 1403 via a 4-connector plug 1406. The interface module 1405 of the headset may receive the MPDM_UP signal and transfer the signal to data extraction circuitry associated with each loudspeaker 1408, 1409 in a similar fashion as described previously (or alternatively could extract the two PDM data channels and send each data PDM channel to the appiopriate loudspeaker). The interface module 1405 may also receive audio data, via individual single channel PLM or PDM data links(which may use a clock or clocks recovered from the MPDM data received by the adjacent speaker circuitry), from noise cancellation microphones 1409, 1410 associated with each loudspeaker and may produce a multi-channel audio signal MPDM down to be transmitted back to the DSP/codec 1401.

Figure 15 illustrates an embodiment with the same four links as shown in Figure 14.

However in this embodiment the interface module is effectively located with one loudspeaker. Thus the right loudspeaker data extraction module receives the MPDM_UP signal, extracts the data for the right audio channel and forwards the MPDM_UP data onto the left loudspeaker circuitry. The active noise cancellation audio data from the microphone associated with the left loudspeaker is sent, as single channel PDM, possibly using a clock or clocks recovered from MPDM UP, to interface circuitry associated with the right loudspeaker where the multi-channel MPDM_DOWN signal is formed.

Figure 16 shows another embodiment similar to that shown in Figure 14 but wherein a single MPDM link is used for bi-directional data transfer. Thus only a three connector plug and socket are required. Figure 17 is a similar embodiment to that shown in Figure 15 but using a bi-directional data link. In this embodiment the data link between the right and left hand speakers may be used to send the multichannel MPDM signal up to the left speaker with only one channel of PDM data from the microphone associated with the left speaker being sent back on the same link.

Figure 18 shows an embodiment similar to that shown in Figure 17 but wherein the data signal link is also used to provide power supply. Thus only a two connector plug/socket is required to provide the link for power/data signal PMDM and ground. An interface module in the headset derives power for the loudspeakers and data extraction circuitry.

Further embodiments may include transmission of detected current and voltage waveforms from the speakers to the host device or codec, for speaker protection features, instead of or in addition to signals from the adjacent microphones. Also similar configurations of the speakers and microphones may be part of the host device, wired via a POB or other internal wiring, rather than separately wired headphones.

Embodiments described above have assumed that all incoming PDM data streams have the same sample rate. If say one data stream has say half the sample rate, then each sample may obviously be sampled twice in successive clock intervals to provide an equivalent system. Similarly each sample of a PDM output stream may be sampled more than once to provide a higher effective sample rate.

Embodiments described above receive one-bit, i.e. two-level, streams of input data.

The invention may be adapted to process multi-level inputs, e.g. 3-level inputs (-1, 0, +1) as used to directly drive Class D H-bridges for example, by suitable adaptation of the truth tables, and similarly to output multi-level output pulse streams.

It can therefore be seen that embodiments of the present invention can be used to provide efficient data transfer using only a limited number of connections and which offers the ability to send additional data when required and/or reduce any EMI effects by making use of alternative data encodings for combinations of input data.

The embodiment have been described in relation to transfer of multiple channels of audio data but it will be appreciated that the principles may be applied to other types of data for driving transducers such as haptic transducers, ultrasonic transducers, hearing aid coils and the like.

It will be appreciated that the interface circuitry may conveniently be implemented, at least partly, as an integrated circuit and may form part of a host electronic device, especially a portable device and/or a battery powered device. The interface circuitry may be used in an audio device such as a personal music or video player. The amplifier may be implemented in a mobile communications device such as mobile telephone or a computing device, such as a laptop or tablet computer or PDA. The interface circuitry may be used in a gaming device.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single feature or other unit may fulfil the functions of several units recited in the claims. The word "amplify" can also mean "attenuate", i.e. decrease, as well as increase and vice versa and the word "add" can also mean "subtract", i.e. decrease, as well as increase and vice versa. Any reference numerals or labels in the claims shall not be construed so as to limit their scope.

Claims (1)

1. <claim-text>CLAIMS1. Audio interface circuitry comprising: a pulse-length-modulator, responsive to a plurality of data streams of audio data samples at a sample rate, to generate a stream of data pulses at said sample rate; wherein the length of each said data pulse is dependent upon on a combination of the then current audio data samples from said plurality of data streams.</claim-text> <claim-text>2. Audio interface circuitry as claimed in claim 1 wherein said audio data streams comprise 1-bit digital audio data streams.</claim-text> <claim-text>3. Audio interface circuitry as claimed in claim 1 or claim 2 wherein said audio data streams correspond to audio data channels.</claim-text> <claim-text>4. Audio interface circuitry as claimed in any preceding claim wherein the pulse-length-modulator is responsive to a first clock signal having a frequency equal to said sample rate.</claim-text> <claim-text>5. Audio interface circuitry as claimed in claim 4 wherein said pulse-length-modulator is further responsive to a second clock signal, wherein the second clock signal has a frequency which is a multiple of the frequency of the first clock signal and wherein the length of each data pulse is based on a selected number of cycles of the second clock signal.</claim-text> <claim-text>6. Audio interface circuitry as claimed in claim 5 wherein the minimum data pulse length is a plurality of cycles of the second clock signal.</claim-text> <claim-text>7. Audio interface circuitry as claimed in claim 5 or claim 6 wherein the maximum data pulse length is shorter than the period of the first clock signal by a plurality of cycles of the second clock signal.</claim-text> <claim-text>8. Audio interface circuitry as claimed in any preceding claim wherein the pulse-length-modulator is configured so that at least one combination of input audio data for said plurality of audio data streams can be encoded as at least two different alternative data pulse lengths.</claim-text> <claim-text>9. Audio interface circuitry as claimed in claim 8 wherein the pulse-length-modulator is configured so as to vary between said at least two different alternative data pulse lengths when encoding said at least one combination of input audio data.</claim-text> <claim-text>10. Audio interface circuitry as claimed in claim 8 or claim 9 wherein the pulse-length-modulator is configured so as to alternate between said at least two different alternative data pulse lengths when encoding said at least one combination of input audio data.</claim-text> <claim-text>11. Audio interface circuitry as claimed in claim 8 or claim 9 wherein the pulse-length-modulator is configured so as to randomly select one of said at least two different alternative data pulse lengths when encoding said at least one combination of input audio data.</claim-text> <claim-text>12. Audio interface circuitry as claimed in claim 8 or claim 9 wherein the pulse-length-modulator is configured so as, when encoding said at least one combination of input audio data, to vary between said at least two different alternative data pulse length so as to control the average data pulse length for all instances of a given combination of input audio data.</claim-text> <claim-text>13. Audio interface circuitry as claimed in claim 12 wherein a plurality of combinations of input audio data can each be encoded as a plurality of alternative data pulse lengths and the pulse-length-modulator is configured to vary between the respective alternative data pulse length so that the average data pulse length for each combination of input audio data is substantially the same.</claim-text> <claim-text>14. Audio interface circuitry as claimed in any of claims 8 to 13 wherein a plurality of combinations of input data can each be encoded as two different lengths of data pulse, the two lengths being symmetric about a predetermined length.</claim-text> <claim-text>15. Audio interface circuitry as claimed in claim 14 wherein one combination of input data can be encoded as a data pulse having a length substantially equal to said predetermined length.</claim-text> <claim-text>16. Audio interface circuitry as claimed in any preceding claim wherein the pulse-length-modulator is also configured to receive at least one additional data channel and wherein the length of at least some individual data pulses encodes the then current audio data samples from said plurality of data streams and also the then current data sample for said additional data channel.</claim-text> <claim-text>17. Audio interface circuitry as claimed in claim 16 wherein said additional data channel is a control data channel.</claim-text> <claim-text>18. Audio interface circuitry as claimed in claim 16 or claim 17 wherein! when no data is received on said additional data channel the pulse length modulator may vary between pulse lengths that encode the same audio data combination.</claim-text> <claim-text>19. Audio interface circuitry as claimed in claim 18 wherein the pulse-length-modulator is configured such that, when data is received on an additional data channel to modulate a series of data pulses with a first reserved sequence prior to encoding said data of the additional data channel, where the first reserved sequence corresponds to the encoding that would be used for a particular data sequence on the additional data channel and wherein the pulse-length-modulator is configured so as not to use the first reserved sequence when no data is available on the additional data channel.</claim-text> <claim-text>20. Audio interface circuitry as claimed in claim 18 or claim 19 wherein the pulse-length-modulator is configured such that when data on the additional channel stops it encodes a second reserved sequence of additional data.</claim-text> <claim-text>21. Audio interface circuitry as claimed in any preceding claim, when dependent directly or indirectly on claim 5, wherein the frequency of the second clock signal is at least five times the frequency of the first clock signal.</claim-text> <claim-text>22. Audio interface circuitry as claimed in claim 21 wherein the frequency of the second clock signal is at least eight times the frequency of the first clock signal.</claim-text> <claim-text>23. Audio interface circuitry as claimed in any preceding claim wherein said plurality of audio data streams comprise left and right stereo data channels.</claim-text> <claim-text>24. Audio interface circuitry as claimed in any preceding claim wherein said pulse-length-modulator is configured to receive a separate audio data stream for each of said audio channels.</claim-text> <claim-text>25. Audio interface circuitry as claimed in claim 23 or 24 wherein the pulse-length-modulator comprises a combinerfor producing a combined data value from each of said audio data streams.</claim-text> <claim-text>26. Audio interface circuitry as claimed in claim 25, when dependent on claim 5, further comprising a counter arranged to count at a frequency of the second clock signal and a comparator for comparing the count value to the combined data value.</claim-text> <claim-text>27. Audio interface circuitry as claimed in any preceding claim wherein the pulse-length-modulator is configured to produce an output which varies between a first non zero voltage and a second non zero voltage.</claim-text> <claim-text>28. Audio interface circuitry as claimed in any preceding claim wherein the rising edges of the data pulses are separated by a regular time interval equal to the sample period.</claim-text> <claim-text>29. Audio interface circuitry as claimed in any of claims 1 to 27 wherein the falling edges of the data pulses are separated by a regular time interval equal to the sample period..</claim-text> <claim-text>30. Audio interface circuitry as claimed in any preceding claim wherein the output from the pulse-length-modulator is connected to an audio signal path on a printed circuit board of a host device.</claim-text> <claim-text>31. Audio interface circuitry as claimed in any preceding claim wherein the output from the pulse-length-modulator is connected to a connector of a host device.</claim-text> <claim-text>32. Audio interface circuitry as claimed in 31 wherein said connector comprises a socket.</claim-text> <claim-text>33. Audio interface circuitry as claimed in claim 31 where said connector comprises a connection for a headset.</claim-text> <claim-text>34. Audio interface circuitry as claimed in claim 31 or claim 32 wherein said pulse-length-modulator is configured, in use, to provide audio data and power to a peripheral connected to said connector.</claim-text> <claim-text>35. Audio interface circuitry as claimed in any of claims 31 to 33 wherein said connector comprises connections for audio data-out, power and ground.</claim-text> <claim-text>36. Audio interface circuitry as claimed in claim 35 wherein said power connection also serves as said audio data-out connection.</claim-text> <claim-text>37. Audio interface circuitry as claimed in claim 35 or claim 36 further comprising an audio data-in connection.</claim-text> <claim-text>38. Audio interface circuitry as claimed in claim 37 wherein said audio data-in connections also serves as said audio data-out connection.</claim-text> <claim-text>39. Audio interface circuitry as claimed in claim 31 wherein the connector is an optical connector.</claim-text> <claim-text>40. Audio interface circuitry as claimed in claim 31 wherein the connector is an rf transmitter.</claim-text> <claim-text>41. Audio interface circuitry as claimed in any preceding claim further comprising bi-directional interface circuitry configured to transmit said data pulses generated by the pulse-length-modulator over a first communications link and receive pulse-length-modulated data pulses via said first communications link.</claim-text> <claim-text>42. Audio interface circuitry as claimed in claim 41 wherein the pulse-length-modulator is configured to transmit data pulses during a first portion the sample period and the bi-directional interface circuitry is configured to receive data pulse during a second, different portion of the sample period.</claim-text> <claim-text>43. Audio interface circuitry as claimed in claim 41 wherein the bi-directional interface circuitry comprises a drive circuit for voltage modulating the first communications link based on the data pulses and a read circuit responsive to the resultant voltage on the first communications link, wherein the read circuit is configured to subtract the drive voltage modulation from the resultant voltage signal.</claim-text> <claim-text>44. Audio circuitry comprising: an interface configured to receive a serial pulse-length modulated audio data input comprising a series of data pulses at a sample rate; data extraction circuitry configured to determine the pulse length of said data pulse and to determine a data value for each of a plurality of audio data streams from said pulse length.</claim-text> <claim-text>45. Audio circuitry as claimed in claim 44 comprising clock recovery circuitry configured to recover a first clock signal based on said sample rate.</claim-text> <claim-text>46. Audio circuitry as claimed in claim 45 wherein the data extraction circuitry is configured to sample the data pulse at a predetermined number of intervals within the period of the first clock signal to determine the pulse length of the data pulse.</claim-text> <claim-text>47. Audio circuitry as claimed in claim 46 wherein the data extraction circuitry comprises a delay line having a plurality of tap points.</claim-text> <claim-text>48. Audio circuitry as claimed in any preceding claim wherein the data extraction circuitry comprises at least a first data extraction module and a second data extraction module wherein the first data extraction module and the second data extractions module are configured to determine data values for different audio data streams to one another.</claim-text> <claim-text>49. Audio circuitry as claimed in claim 48 wherein said first data extraction module is configured to receive the input serial pulse-length modulated audio data from the interface and to pass said input serial pulse-length modulated audio data to the second data extraction module.</claim-text> <claim-text>50. Audio circuitry as claimed in claim 48 or 49 wherein each of the at least first and second data extraction modules are associated with respective first and second audio transducers.</claim-text> <claim-text>51. Audio circuitry as claimed in any of claims 44 -50 further comprising power circuitry configured to derive a power supply from said input serial pulse-length modulated audio data signal.</claim-text> <claim-text>52. Audio circuitry as claimed in claim 51 wherein the data extraction circuitry is powered by said power supply.</claim-text> <claim-text>53. A headset comprising audio circuitry as claimed in any of claims 44-52.</claim-text> <claim-text>54. Audio transceiver circuitry comprising audio interface circuitry as claimed in any of claims 1 -43 to send audio data-out and audio circuitry as claimed in any of claims 44-53 to receive audio data-in.</claim-text> <claim-text>55. An audio system comprising audio circuitry as claimed in any of claims 1 -43 configured to transmit audio data for a plurality of audio channels to audio circuitry as claimed in any of claims 44-53.</claim-text> <claim-text>56. An integrated circuit comprising audio interface circuitry as claimed in any of claims 1 -43 and/or audio circuitry as claimed in any of claims 44-53.</claim-text> <claim-text>57. An electronic device comprising audio interface circuitry as claimed in any of claims 1 -43 and/or audio circuitry as claimed in any of claims 44-53.</claim-text> <claim-text>58. An electronic device as claimed in claim 57 wherein said device is at least one of: a portable device; a battery powered device; a communication device; a computing device; a personal media player; a music player; a mobile telephone; a docking station for a portable device; a headset; and a hearing aid.</claim-text> <claim-text>59. A method of transmitting audio data comprising, generating a pulse length modulated signal comprising a series of data pulses at a sample rate; wherein the length of each data pulse is dependent upon on a combination of then current audio data samples from said plurality of data streams.</claim-text> <claim-text>60. A method as claimed in claimed in claim 59 wherein said data streams comprise two or more 1-bit digital audio data channels.</claim-text> <claim-text>61. A method as claimed in claim 59 or claim 60 comprising generating said data pulses based on a first clock signal having a frequency equal to said sample rate.</claim-text> <claim-text>62. A method as claimed in claim 61 wherein generating the data pulses comprises generating a pulse having a length equal to a selected number of cycles of a second clock signal which has a frequency which is a multiple of the frequency of the first clock signal.</claim-text> <claim-text>63. A method as claimed in any of claims 59-62 wherein generating said data pulses comprises, for at least some combinations of input audio data, varying between at least two different alternative data pulse lengths.</claim-text> <claim-text>64. A method as claimed in claim 63 comprising alternating between said at least two different alternative data pulse lengths.</claim-text> <claim-text>65. A method as claimed in claim 63 comprising randomly selecting between said at least two different alternative data pulse lengths.</claim-text> <claim-text>66. A method as claimed in any of claims 63 to 65 wherein a plurality of combinations of input data can each be encoded as two different lengths of data pulse, the two lengths being symmetric about a predetermined length.</claim-text> <claim-text>67. A method as claimed in any of claims 59 to 66 further comprising receiving at least one additional data channel and generating the data pulses such that the length of at least some individual data pulses encodes audio data for said plurality of audio streams and also said additional data channel.</claim-text> <claim-text>68. A method as claimed in claim 67 wherein said additional data channel is a control data channel.</claim-text> <claim-text>69. A method as claimed in claim 67 or claim 68 comprising, in the absence of data on said additional data channel, varying between possible alternative pulse lengths that encode the same audio data combination.</claim-text> <claim-text>70. A method as claimed in claim 69 comprising generating the data pulses so as to encode a first reserved additional data sequence prior to transmitting any data of the additional data channel, wherein the first reserved additional data sequence is not used when no data is available on the additional data channel.</claim-text> <claim-text>71. A method as claimed in claim 69 or claim 70 comprising, at the end of transmission of any data on the additional data channel, transmitting a second reserved sequence of additional data.</claim-text> <claim-text>72. A method as claimed in any of claims 59 to 71 comprising transmitting said data pulses over a first communications link and receiving pulse-length-modulated data pulses via said first communications link.</claim-text> <claim-text>73. A method as claimed in claim 72 comprising transmitting data pulses during a first portion of said regular time interval and receiving data pulses during a second, different portion of said regular time interval.</claim-text> <claim-text>74. A method as claimed in claim 72 comprising transmitting data pulses and receiving data pulses simultaneously.</claim-text> <claim-text>75. An audio system for transferring audio data for a plurality of audio channels over a single wire connection comprising a pulse-length-modulator configured to produce a series of data pulses at regular intervals wherein the length of each data pulse encodes audio data for each of said plurality of audio channels.</claim-text> <claim-text>76. A data transfer system for transferring data for a plurality of separate data channels over a single wire connection comprising a pulse-length-modulator configured to produce a series of data pulses at regular intervals wherein the length of each data pulse encodes data from each of said plurality of audio channels.</claim-text> <claim-text>77. Audio interface circuitry comprising: a pulse-length-modulator responsive to audio data for a plurality of audio channels to generate data pulses at a regular time interval; wherein the length of the data pulses encode said audio data; and wherein the length of an individual data pulse encodes audio data for said plurality of audio channels.</claim-text> <claim-text>78. An audio interface for receiving and encoding a plurality of streams of 1-bit audio data samples and for transmitting a stream of encoded data pulses via a single communication link." 79. An audio interface for receiving and encoding a plurality of streams of 1-bit audio data samples and simultaneously transmitting on a clock edge of a stream of encoded data pulses a plurality of sampled 1-bit audio data samples via a single communication link.80. Audio interface circuitry as hereinbefore described with reference to Figures 2 - 18 of the accompanying drawings.</claim-text>