GB2491156A - processing pipeline control - Google Patents
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- GB2491156A GB2491156A GB1108769.9A GB201108769A GB2491156A GB 2491156 A GB2491156 A GB 2491156A GB 201108769 A GB201108769 A GB 201108769A GB 2491156 A GB2491156 A GB 2491156A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
- G06F3/023—Arrangements for converting discrete items of information into a coded form, e.g. arrangements for interpreting keyboard generated codes as alphanumeric codes, operand codes or instruction codes
- G06F3/0238—Programmable keyboards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/048—Interaction techniques based on graphical user interfaces [GUI]
- G06F3/0487—Interaction techniques based on graphical user interfaces [GUI] using specific features provided by the input device, e.g. functions controlled by the rotation of a mouse with dual sensing arrangements, or of the nature of the input device, e.g. tap gestures based on pressure sensed by a digitiser
- G06F3/0489—Interaction techniques based on graphical user interfaces [GUI] using specific features provided by the input device, e.g. functions controlled by the rotation of a mouse with dual sensing arrangements, or of the nature of the input device, e.g. tap gestures based on pressure sensed by a digitiser using dedicated keyboard keys or combinations thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C17/00—Arrangements for transmitting signals characterised by the use of a wireless electrical link
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/422—Input-only peripherals, i.e. input devices connected to specially adapted client devices, e.g. global positioning system [GPS]
- H04N21/42204—User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
- H04N21/42653—Internal components of the client ; Characteristics thereof for processing graphics
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/422—Input-only peripherals, i.e. input devices connected to specially adapted client devices, e.g. global positioning system [GPS]
- H04N21/42204—User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor
- H04N21/42226—Reprogrammable remote control devices
- H04N21/42227—Reprogrammable remote control devices the keys being reprogrammable, e.g. soft keys
- H04N21/42228—Reprogrammable remote control devices the keys being reprogrammable, e.g. soft keys the reprogrammable keys being displayed on a display screen in order to reduce the number of keys on the remote control device itself
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Abstract
A graphics processing unit (2, Fig. 1) includes a texture pipeline 6 having a first pipeline portion 18 and a second pipeline portion 20. A subject instruction, which is part of a program thread and uses target data, is recirculated within the first pipeline portion 18 until descriptor data to be loaded from a memory (4, Fig. 1) by that subject instruction has been fetched and cached within a shared descriptor cache (22, Fig. 1). First gating stage 28 determines when the descriptor has been stored within the cache, and then passes the subject instruction to the second pipeline portion 20. Second gating stage 30 recirculates the subject instruction in the second portion until further processing operations have completed. The descriptor data is locked within the cache until there are no pending subject instructions within pipeline 6 related to that descriptor data. Intervening stages 24 are included between first and second pipeline portions. State data of subject instructions specifying storage locations of the target data within descriptor cache are stored as the instructions pass through the pipeline. State data identifies instructions within a group that shares target data, for example relating to four adjacent pixels processed as a quad.
Description
PROCESSING PIPELiNE CONTROL This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems including processing pipelines and to the control of the processing pipelines within such data processing systems.
It is known to provide data processing systems that incorporate processing pipelines so as to increase the degree of parallel execution within the data processing system and accordingly increase the number of instructions executed per cycle. Increasing the number of pipeline stages within a processing pipeline increases the number of program instructions that can be executed in parallel.
However, processing pipelines with a large number of pipeline stages have difficulty in efficiently handling instructions which fail. For an example, should a load instruction progressing along a processing pipeline fail to receive its loaded data within the expected time, then one approach would be for it to stall the processing pipeline. This would be highly inefficient. Another approach, if there are no later instructions dependent upon the failed load instruction, is to allow the load instruction to progress along the processing pipeline as a processing "bubble" in step with the other program instructions progressing through the pipeline and accordingly not disturb the execution of those other processing instructions. A problem with this approach is that the presence of the bubble within the pipeline reduces the number of program instructions which are being executed in parallel and accordingly reduces the overall executed instructions per cycle value.
Viewed from one aspect the present invention provides apparatus for processing data comprising: a memory configured to store data; a cache configured to store data fetched from said memory; and a processing pipeline having a plurality of pipeline stages and configured to perform data processing operations specified by program instructions passing along said processing pipeline, wherein said processing pipeline comprises a first pipeline portion having a plurality of pipeline stages followed by a second pipeline portion having a plurality of pipeline stages; said first pipeline portion includes a load stage configured to respond to a subject instruction using target data, when said target data is not already stored within said cache, by fetching said target data from said memory and storing said target data within said cache; said first pipeline portion includes a first gating stage following said load stage and configured to determine if said target data is present within said cache and; (i) if said target data is not present within said cache, then to recirculate said subject instruction through said first pipeline portion; and (ii) if said target data is present within said cache, then to pass said subject instruction to said second pipeline portion; said second pipeline portion includes a further processing stage configured to respond to said subject instruction by performing a further processing operation using said target data; and said second pipeline portion includes a second gating stage following said further processing stage and configured to determine if said ftn-ther processing operation is completed and: (i) if said further processing operation is not completed, then to recirculate said subject instruction through said second pipeline portion; and (ii) if said further processing operation is completed, then to retire said subject instruction from said processing pipeline.
The invention provides a processing pipeline which includes a first pipeline portion and a second pipeline portion. The first pipeline portion serves to load target data in to a cache memory and then check that the target data has been loaded, If the target data has not been loaded, then the subject instruction is recirculated (returncd to a proceeding pipeline stage) within the first pipeline portion and is not passed on to the second pipeline portion. This prevents a processing bubble being passed to the second pipeline portion and gives the first pipeline portion further time to complete the subject instruction. The second pipeline portion itself serves to perform further processing operations and includes a second gating stage which checks to determine whether or not those further processing operations have been completed. If the further processing operations have not been completed, then the subject instruction is recirculated within the second pipeline portion to give more time for the further processing operations to complete. If the second gating stage determines that the further processing operation is complete, then the subject instruction may be retired. The processing pipeline thus includes two loops, one formed by the first pipeline portion and one formed by the second pipeline portion. The subject instruction recirculates within the first pipeline portion until the target data for that subject instruction is stored within the cache. Once the target data has been gathered and is available within the cache, then the subject instruction is released in to the second pipeline portion within which it can recirculate, if necessary, until the further processing operations performed by that second pipeline portion are completed and the subject instruction retired.
In preferred embodiments of the invention the target data may be locked within the cache until all program instructions that use the target data have been retired from the processing pipeline.
In this way, efficiency may be raised since target data which has been placed in to the cache by the operation of the first pipeline portion will be held within that cache until it is no longer required.
This reduces the likelihood of processing bubbles arising within the second pipeline portion.
While it will be appreciated that the target data can take a wide variety of different forms, in some embodiments the target data is descriptor data specifying one or more properties of further target data, with the further processing operation serving to fetch the further target data from the memory in dependence upon the target data stored within the cache. The further processing operations are thus ones in which a fetch of data from memory is indirectly specified in dependence upon target data and accordingly, it is important that the target data should be stored within the cache memory by the operation of the first pipeline portion before it is worthwhile attempting to perform the further processing operations to fetch the further target data in the second pipeline portion.
The first gating circuitry and the second gating circuitry served to recirculate the subject instruction to a proceeding stage which may be one of a first stage or an intermediate stage within the pipeline portion concerned.
It is possible that the second pipeline portion may follow directly after the first pipeline portion. However, in other embodiments the processing pipeline comprises one or more intervening stages between the first pipeline portion and the second pipeline portion.
It will be appreciated that the present technique may be applied to processing pipelines of a wide variety of different forms and applications. However, the present technique is well suited to embodiments in which the processing pipeline is a texture pipeline within a graphics processing unit. Such a texture pipeline typically has a high requirement for loading data from memory with further processing operations within the texture pipeline being dependent upon previously loaded data. Within this context the present technique which ensures that the target data is stored within the cache before permitting the subject instruction to progress beyond the first pipeline portion and thereby improves efficiency by reducing the number of processing bubbles which arise within the processing pipeline downstream of the first pipeline portion.
The further target data may be texture data and the target data may be descriptor data specifying one or more parameters of the texture data. These parameters may, for example, be used to locate the storage address of texture data to be utilised for a particular pixel.
The target data may be reused by a large number of subject instructions and efficiency may be improved if the target data stored within the cache is shared. State data stored in respect of each subject instruction as it passed through the processing pipeline can include values specifying storage locations within the cache of the shared target data.
The subject instruction may be one of a group of subject instructions that share target data and are processed together with the state data identifying each subject instruction within the group of program instructions (e.g. the group of subject instructions may relate to four adjacent pixel values to be processed together as a quad).
The target data for the group of subject instructions will be locked in the cache until all of the group of subject constructions have completed their use of the shared target data.
The efficiency of processing pipelines is generally increased when the subject instructions within the processing pipeline are taken from different program threads such that there is no interdependence between the subject instructions. Thread dispatching circuitry may be configured to dispatch subject instructions in to the processing pipeline for processing and thread retirement circuitry may be used to retire subject instructions from the processing pipeline when they have completed.
Viewed from another aspect the present invention provides apparatus for processing data comprising: memory means for storing data; cache means for storing data fetched from said memory means; and processing pipeline means for performing data processing operations specified by program instructions passing along said processing pipeline means, said processing pipeline means having a plurality of pipeline stage means for performing data processing operations, wherein said processing pipeline means comprises a first pipeline portion having a plurality of pipeline stage means followed by a second pipeline portion having a plurality of pipeline stage means; said first pipeline portion includes load stage means for responding to a subject instruction using target data, when said target data is not already stored within said cache means, by fetching said target data from said memory means and storing said target data within said cache means; said first pipeline portion includes, following said load stage means, first gating stage means for determining if said target data is present within said cache means and: (1) if said target data is not present within said cache means, then to recirculate said subject instruction through said first pipeline portion; and (ii) if said target data is present within said cache means, then to pass said subject instruction to saId second pipeline portion; said second pipeline portion includes further processing stage means for responding to said subject instruction by performing a further processing operation using said target data; and said second pipeline portion includes, following said further processing stage means, second gating stage means for determining if said further processing operation is completed and: (i) if said further processing operation is not completed, then to recirculate said subject instruction through said second pipeline portion; and (ii) if said further processing operation is completed, then to retire said subject instruction from said processing pipeline means.
Viewed from a further aspect the present invention provides a method of processing data comprising the steps of: storing data within a memory; storing within a cache data fetched from said memory; and performing within a processing pipeline data processing operations specified by program instructions passing along said processing pipeline, said processing pipeline having a plurality of pipeline stages, wherein said processing pipeline means comprises a first pipeline portion having a plurality of pipeline stages followed by a second pipeline portion having a plurality of pipeline stages; and further comprising: using a load stage within said first pipeline portion to respond to a subject instruction using target data, when said target data is not already stored within said cache, by fetching said target data from said memory and storing said target data within said cache; using a first gating stage following said load stage within said first pipeline portion to determine if said target data is present within said cache and: (i) if said target data is not present within said cache, then recirculating said subject instruction through said first pipeline portion; and (ii) if said target data is present within said cache, then passing said subject instruction to said second pipeline portion; using a further processing stage within said second pipeline portion to respond to said subject instruction by performing a further processing operation using said target data; and using a second gating stage following said further processing stage within said second pipeline portion to determine if said further processing operation is completed and: (i) if said further processing operation is not completed, then recirculating said subject instruction through said second pipeline portion; and (ii) if said further processing operation is completed, then retiring said subject instruction from said processing pipeline means.
Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 schematically illustrates a graphics processing unit including a plurality of processing pipelines; Figure 2 schematically illustrates a texture pipeline including a first pipeline portion and a second pipeline portion; Figure 3 schematically illustrates the relationship between descriptor data and texture data processed by the texture pipeline; Figure 4 schematically illustrates a shared descriptor cache and a group of program instructions that share descriptor data; and Figure 5 is a flow diagram schematically illustrating the operation of the texture pipeline of Figure 2.
Figure 1 schematically illustrates a graphics processing unit 2 coupled to a memory 4. The memory 4 stores program data, texture data, descriptor data and other data required for graphics processing, as will be familiar to those in the field of graphics processing. The graphics processing unit 2 includes a plurality of processing pipelines including a texture pipeline 6, a load store pipeline 8, a first arithmetic pipeline 10 and a second arithmetic pipeline 12. Thread dispatch circuitry 14 dispatches program instructions in to an appropriate processing pipeline 6, 8, 10, 12 and thread retirement circuitry 16 retires program instructions from the processing pipelines 6, 8, 10, 12, as well as retiring processing threads when they are completed in their entirety. It will be appreciated that the pipeline arrangement Figure 1 is simply an example of a processing apparatus including a processing pipeline and many other different forms of processing apparatus may be used as well as many other different forms of graphics processing unit.
The texture pipeline in 6 in Figure 1 is illustrated as having a first pipeline portion 18 and a second pipeline portion 20. The first pipeline portion 18 is responsible for fetching descriptor data from the memory 4 and storing it within a shared descriptor cache 22 which is closely coupled to the texture pipeline 6. The second portion of the pipeline 20 is responsible for fetching texture data from the memory 4 in dependence upon the descriptor data stored within the descriptor cache 22, Further portions of the texture pipeline 6 may perform other processing operations, such as filtering and pixel manipulation.
Tn Figure 1, the memory 4 is illustrated as a unified block. However, it will be appreciated that in practice the memory 4 may comprise a memory hierarchy formed of multiple levels of cache memory, main memory and non-volatile data storage, such as a hard disk drive.
Figure 2 schematically illustrates the texture pipeline 6 in more detail. In particular, the texture pipeline 6 includes a first pipeline portion 18, a plurality of intervening pipeline stages 24 and a second pipeline portion 20. The first pipeline portion 18 includes a load stage 26 which is responsive to a subject instruction (e.g. an instruction seeking to load the texture of a pixel) to issue a request to the memory 4 to fetch descriptor data to be subsequently used in determining an address of texture data to be retrieved. A later stage within the first pipeline portion 18 serves to poll whether or not the memory has returned the requested descriptor data and, if the data has been returned, then a cache load stage serves to load the returned descriptor data in to the shared descriptor cache 22. A first gating stage 28 within the first pipeline portion 18 serves to determine whether or not the descriptor data (target data) has been loaded in to the shared descriptor cache 22 when the subject instruction reaches the first gating stage 28. If the descriptor data (target data) is present within the shared descriptor cache 22, then the subject instruction is passed on to the intervening stages 24 and then on to the second pipeline portion 20. If the descriptor data is not present within the shared descriptor cache 22, then the subject instruction is recirculated by returning it to the top of the first pipeline portion 18 so that it may pass through the first pipeline portion again and accordingly get more time for the descriptor data to be returned form the memory 4. This avoids passing the subject instruction which does not yet have its required descriptor data present within the shared descriptor cache 22 on to the subsequent portions of the pipeline comprising the intervening stages 24 and the second pipeline portion 20 thereby avoiding introducing unwanted processing bubbles within these later portions of the texture pipeline 6.
When a subject instruction has been passed by the first gating stage 28, it progresses to the intervening stages 24 where further processing operations are performed, such as derivative generation determining the rate of change of pixel values, texture map level selection and address generation for the texture data to be loaded from the memory 4. The subject instruction is then passed to the second pipeline portion 20 which includes further processing stages which perform further processing operations, such as loading the texture data from the memory 4. A second gating stage 30 at the end of the second pipeline portion 20 determines whether or not the further processing operations to be performed by the further processing stages have been completed. In a similar way as for the first pipeline portion 18, the further processing operations may be completed when the texture data has actually returned. If the further processing operations have not been completed, then the subject instruction is recirculated within the second pipeline portion 20 so as to permit more time for the texture data to be returned. When the texture data has been returned, it may be subject to processing operations within the texture pipeline 6 subsequent to the second pipeline portion, such as applying a filter operation to the retrieved texture data and writing the derived colour value to a register.
Figure 3 schematically illustrates the relationship between descriptor data and texture data.
The descriptor data may comprise image descriptors 32, surface descriptors 34 and sampler descriptors 36. All of these descriptors 32, 34, 36 are stored within the memory 4 and are used by the texture pipeline 6 to determine what portions of texture data 38 to read from the memory 4 and how to process that retrieved texture data. In particular, the image descriptor data retrieved for a subject instruction may include data specifying which of a plurality of representations of a texture are to be used given the scaling of that texture that is currently employed, the format of the texture data (e.g. ROB etc.), the size of the texture data and a pointer to a surface descriptor for the texture data concerned. The surface descriptor contains a pointer to the memory address of the start of the relevant instance of the texture data to be employed together with a pitch value indicating the line pitch of that instance of the texture data.
The relationship illustrated in Figure 3 between the descriptor data and the texture data is one example of a relationship between target data stored in to a cache within a first pipeline portion 18 and further target data retrieved in dependence upon the cache target data by a second pipeline portion 20. The present techniques are not limited to this example, or indeed the field of graphics processing.
Figure 4 schematically illustrates the shared descriptor cache 22 comprising a plurality of cache lines each storing a shared instance of descriptor data and having an associated index value.
In this example the shared descriptor cache 22 is indexed, but in other example embodiments it is possible that stored tag values could be used to identitS' particular descriptor data it is desired to retrieve from the shared descriptor cache 22. Also illustrated in Figure 4 is that each cache line of the shared descriptor cache 22 includes a lock counter field 40 which stores a count value indicating how many of subject instructions within the texture pipeline 6 that are undergoing processing require to use the descriptor concerned. Each time a subject instruction seeks to load a descriptor, whether or not that descriptor is already cached, the lock count will be incremented so as to indicate that a subject instruction which wishes to use that descriptor is present within the texture pipeline 6.
Each time a subject instruction is retired from the texture pipeline 6 such that is has completed its use of the descriptors it references, then the relevant lock count values for those descriptors are decremented. Thus, when the lock count reaches zero, all of the subject instructions within the texture pipeline 6 will have completed their use of that descriptor and it may be unlocked within the shared descriptor cache and accordingly subject to cache line replacement to make way for other descriptor values.
Also illustrated in Figure 4 is thread group state 42. Groups of subject instructions may be processed together and share the descriptors they use. In this case, the thread group state identifies each of the subject instructions with identifiers TSO, 151, TS2, TS3 as well as storing, in this example embodiment, index values pointing to the cache lines where the descriptors to be used by the subjeQt instructions within that thread group are located.
Figure 5 is a flow diagram schematically illustrating the operation of the texture pipeline of Figure 2. At step 44, processing waits until a subject instruction is received in the first pipeline portion 18. Step 46 then determines whether or not the descriptor data for that subject instruction is already present within the shared descriptor cache 22, If the descriptor data is already present, then processing advances to step 48. If the descriptor data is not already present within the shared descriptor cache 22, then step 50 serves to initiate a descriptor load from the memory 4 to the shared descriptor cache 22. Step 52 stores any returned descriptor data to the shared cache 22. Step 54 is performed by the first gating stage 28 and determines whether all the descriptor data required by the subject instruction is now present within the shared descriptor cache or the descriptor data is not yet present. If it is not present, then the subject instruction is recirculated and processing returns to step 50.
If the all the descriptor data is determined to be present within the shared descriptor cache 22, then processing proceeds to step 48 where a subject instruction is passed to the second pipeline portion 20, possibly, via one or more intervening stages 24. Step 56 determines the texture map level to be used given the resolution of the portion of the image to be drawn relative to the texture map data stored. Step 58 then initiates a load of the texture data. This load of the texture data is from an address within the memory 4 which is calculated in dependence upon the descriptor data which is stored within the shared descriptor cache 22. Step 60 is performed by the second gating stage 30 and determines whether or not the further processing operations are complete. If the further processing operations are not complete, then processing returns to step 56. If the further processing operations are complete, then processing proceeds to step 62 where a filtering operation is performed before the colour pixel value calculated is written to a register at step 64, as the result of the subject instruction which has been processed by the texture pipeline 6.
It will be appreciated that the processing performed by the texture pipeline 6 will also incorporate the cache locking as previously described in relation to Figure 4, with the lock value being incremented and decremented so as to track the number of "in flight" subject instructions within the texture pipeline.
Claims (19)
- CLAIMS1. Apparatus for processing data comprising: a memory configured to store data; a cache configured to store data fetched from said memory; and a processing pipeline having a plurality of pipeline stages and configured to perform data processing operations specified by program instructions passing along said processing pipeline, wherein said processing pipeline comprises a first pipeline portion having a plurality of pipeline stages followed by a second pipeline portion having a plurality of pipeline stages; said first pipeline portion includes a load stage configured to respond to a subject instruction using target data, when said target data is not already stored within said cache, by fetching said target data from said memory and storing said target data within said cache; said first pipeline portion includes a first gating stage following said load stage and configured to determine if said target data is present within said cache and: (i) if said target data is not present within said cache, then to recirculate said subject instruction through said first pipeline portion; and (ii) if said target data is present within said cache, then to pass said subject instruction to said second pipeline portion; said second pipeline portion includes a further processing stage configured to respond to said subject instruction by performing a further processing operation using said target data; and said second pipeline portion includes a second gating stage following said further processing stage and configured to determine if said further processing operation is completed and: (i) if said further processing operation is not completed, then to recirculate said subject instruction through said second pipeline portion; and* (ii) if said further processing operation is completed, then to retire said subject instruction from said processing pipeline.
- 2. Apparatus as claimed in claim 1, wherein said target data is locked within said cache until all program instructions that use said target data have been retired from said processing pipeline.
- 3. Apparatus as claimed in any one of claims I and 2, wherein said target data is descriptor data specifying one or more properties of further target data and said further processing operation fetches said further target data from said memory in dependence upon said target data stored within said cache.
- 4. Apparatus as claimed in claim 3, wherein said second pipeline portion determines a storage location within said memory of said further target data using said target data.
- 5. Apparatus as claimed in any one of the preceding claims, wherein said first gating stage recirculates said subject instruction by returning said subject instruction to one of a first stage within said first pipeline portion and an intermediate stage within said first pipeline portion.
- 6. Apparatus as claimed in any one of the preceding claims, wherein said second gating stage recirculates said subject instruction by returning said subject instruction to one of a first stage within said second pipeline portion and an intermediate stage within said second pipeline portion.
- 7. Apparatus as claimed in any one of the preceding claims, wherein said processing pipeline comprises one or more intervening stages between said first pipeline portion and said second pipeline portion.
- 8. Apparatus as claimed in any one of the preceding claims, wherein said processing pipeline is a texture pipeline within a graphics processing unit.
- 9. Apparatus as claimed in claim 8, wherein said further target data is texture data and said target data is descriptor data specifying one or more parameters of said texture data.
- 10. Apparatus as claimed in any one of claims 8 and 9, wherein said graphics processing unit comprises one or more further processing pipelines.
- 11. Apparatus as claimed in any one of the preceding claims, wherein said processing pipeline is configured to store state data for said subject instruction as it passes through said processing pipeline, said state data including values specifying storage locations within said cache of said target data.
- 12. Apparatus as claimed in claim 11, wherein said subject instruction is one of a group of subject instructions that share target data, said state data identifying each subject instruction within said group of program instructions.
- 13. Apparatus as claimed in claim 11, wherein said target data is locked in said cache until at least all of said group of subject instructions that share said target data have completed their use of said shared target data.
- 14. Apparatus as claimed in any one of the preceding claims, wherein said subject instruction is part of a program thread and said processing pipeline is configured to process in parallel a plurality of subject instructions each from a different program thread.
- 15. Apparatus as claimed in claim 13, comprising thread dispatching circuitry configured to dispatch said subject instruction to said processing pipeline for processing.
- 16. Apparatus for processing data comprising: memory means for storing data; cache means for storing data fetched from said memory means; and processing pipeline means for performing data processing operations specified by program instructions passing along said processing pipeline means, said processing pipeline means having a plurality of pipeline stage means for performing data processing operations, wherein said processing pipeline means comprises a first pipeline portion having a plurality of pipeline stage means followed by a second pipeline portion having a plurality of pipeline stage means; said first pipeline portion includes load stage means for responding to a subject instruction using target data, when said target data is not already stored within said cache means, by fetching said target data from said memory means and storing said target data within said cache means; said first pipeline portion includes, following said load stage means, first gating stage means for determining if said target data is present within said cache means and: (i) if said target data is not present within said cache means, then to recirculate said subject instruction through said first pipeline portion; and (ii) if said target data is present within said cache means, then to pass said subject instruction to said second pipeline portion; said second pipeline portion includes further processing stage means for responding to said subject instruction by performing a further processing operation using said target data; and said second pipeline portion includes, following said further processing stage means, second gating stage means for determining if said further processing operation is completed and: (i) if said further processing operation is not completed, then to recirculate said subject instruction through said second pipeline portion; and (ii) if said further processing operation is completed, then to retire said subject instruction from said processing pipeline means.
- 17. A method of processing data comprising the steps of: storing data within a memory; storing within a cache data fetched from said memory; and performing within a processing pipeline data processing operations specified by program instructions passing along said processing pipeline, said processing pipeline having a plurality of pipeline stages, wherein said processing pipeline means comprises a first pipeline portion having a plurality of pipeline stages followed by a second pipeline portion having a plurality of pipeline stages; and further comprising: using a load stage within said first pipeline portion to respond to a subject instruction using target data, when said target data is not already stored within said cache, by fetching said target data from said memory and storing said target data within said cache; using a first gating stage following said load stage within said first pipeline portion to determine if said target data is present within said cache and: (i) if said target data is not present within said cache, then recirculating said subject instruction through said first pipeline portion; and (ii) if said target data is present within said cache, then passing said subject instruction to said second pipeline portion; using a further processing stage within said second pipeline portion to respond to said subject instruction by performing a further processing operation using said target data; and using a second gating stage following said further processing stage within said second pipeline portion to determine if said further processing operation is completed and: (i) if said further processing operation is not completed, then recirculating said subject instruction through said second pipeline portion; and (ii) if said further processing operation is completed, then retiring said subject instruction from said processing pipeline means.
- 18. Apparatus for processing data substantially as hereinbefore described with reference to the accompanying drawings.
- 19. A method of processing data substantially as hereinbefore described with reference to the accompanying drawings.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1108769.9A GB2491156B (en) | 2011-05-25 | 2011-05-25 | Processing pipeline control |
JP2012094511A JP6017171B2 (en) | 2011-05-25 | 2012-04-18 | Processing pipeline control |
US13/459,347 US9927882B2 (en) | 2011-05-25 | 2012-04-30 | Processing pipeline control |
CN201210172501.9A CN102855122B (en) | 2011-05-25 | 2012-05-25 | Apparatus and method for processing data |
Applications Claiming Priority (1)
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GB1108769.9A GB2491156B (en) | 2011-05-25 | 2011-05-25 | Processing pipeline control |
Publications (3)
Publication Number | Publication Date |
---|---|
GB201108769D0 GB201108769D0 (en) | 2011-07-06 |
GB2491156A true GB2491156A (en) | 2012-11-28 |
GB2491156B GB2491156B (en) | 2019-08-07 |
Family
ID=47080881
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GB1108769.9A Active GB2491156B (en) | 2011-05-25 | 2011-05-25 | Processing pipeline control |
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Country | Link |
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US (1) | US9927882B2 (en) |
JP (1) | JP6017171B2 (en) |
CN (1) | CN102855122B (en) |
GB (1) | GB2491156B (en) |
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US10085016B1 (en) * | 2013-01-18 | 2018-09-25 | Ovics | Video prediction cache indexing systems and methods |
US9679347B2 (en) | 2014-02-18 | 2017-06-13 | Qualcomm Incorporated | Shader pipeline with shared data channels |
CN105488565A (en) | 2015-11-17 | 2016-04-13 | 中国科学院计算技术研究所 | Calculation apparatus and method for accelerator chip accelerating deep neural network algorithm |
US11379944B2 (en) * | 2020-06-23 | 2022-07-05 | Nvidia Corporation | Techniques for performing accelerated point sampling in a texture processing pipeline |
CN113747060B (en) * | 2021-08-12 | 2022-10-21 | 荣耀终端有限公司 | Image processing method, device and storage medium |
CN115185860B (en) * | 2022-09-14 | 2022-12-02 | 沐曦集成电路(上海)有限公司 | Cache access system |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4965764A (en) * | 1987-03-04 | 1990-10-23 | Nec Corporation | Memory access control system |
US6236413B1 (en) * | 1998-08-14 | 2001-05-22 | Silicon Graphics, Inc. | Method and system for a RISC graphics pipeline optimized for high clock speeds by using recirculation |
US6259460B1 (en) * | 1998-03-26 | 2001-07-10 | Silicon Graphics, Inc. | Method for efficient handling of texture cache misses by recirculation |
US20080276079A1 (en) * | 2006-02-09 | 2008-11-06 | Luick David A | Mechanism to minimize unscheduled d-cache miss pipeline stalls |
US7542043B1 (en) * | 2005-05-23 | 2009-06-02 | Nvidia Corporation | Subdividing a shader program |
US20090198972A1 (en) * | 2008-01-31 | 2009-08-06 | Arm Norway As | Microprocessor systems |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4433374A (en) | 1980-11-14 | 1984-02-21 | Sperry Corporation | Cache/disk subsystem with cache bypass |
JPS641046A (en) * | 1987-03-04 | 1989-01-05 | Nec Corp | Memory access control system |
JP2780372B2 (en) | 1989-08-29 | 1998-07-30 | 株式会社日立製作所 | Control method for assembling cache in disk control device |
US6771264B1 (en) * | 1998-08-20 | 2004-08-03 | Apple Computer, Inc. | Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor |
US6901483B2 (en) * | 2002-10-24 | 2005-05-31 | International Business Machines Corporation | Prioritizing and locking removed and subsequently reloaded cache lines |
JP3655908B2 (en) * | 2003-02-26 | 2005-06-02 | 株式会社東芝 | Instruction rollback processor system, instruction rollback method, and instruction rollback program |
US7027062B2 (en) * | 2004-02-27 | 2006-04-11 | Nvidia Corporation | Register based queuing for texture requests |
US7640392B2 (en) | 2005-06-23 | 2009-12-29 | Qualcomm Incorporated | Non-DRAM indicator and method of accessing data not stored in DRAM array |
US8207972B2 (en) * | 2006-12-22 | 2012-06-26 | Qualcomm Incorporated | Quick pixel rendering processing |
US7984269B2 (en) * | 2007-06-12 | 2011-07-19 | Arm Limited | Data processing apparatus and method for reducing issue circuitry responsibility by using a predetermined pipeline stage to schedule a next operation in a sequence of operations defined by a complex instruction |
CN101354641B (en) | 2008-08-20 | 2010-08-11 | 炬力集成电路设计有限公司 | Access control method and device of external memory |
-
2011
- 2011-05-25 GB GB1108769.9A patent/GB2491156B/en active Active
-
2012
- 2012-04-18 JP JP2012094511A patent/JP6017171B2/en active Active
- 2012-04-30 US US13/459,347 patent/US9927882B2/en active Active
- 2012-05-25 CN CN201210172501.9A patent/CN102855122B/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4965764A (en) * | 1987-03-04 | 1990-10-23 | Nec Corporation | Memory access control system |
US6259460B1 (en) * | 1998-03-26 | 2001-07-10 | Silicon Graphics, Inc. | Method for efficient handling of texture cache misses by recirculation |
US6236413B1 (en) * | 1998-08-14 | 2001-05-22 | Silicon Graphics, Inc. | Method and system for a RISC graphics pipeline optimized for high clock speeds by using recirculation |
US7542043B1 (en) * | 2005-05-23 | 2009-06-02 | Nvidia Corporation | Subdividing a shader program |
US20080276079A1 (en) * | 2006-02-09 | 2008-11-06 | Luick David A | Mechanism to minimize unscheduled d-cache miss pipeline stalls |
US20090198972A1 (en) * | 2008-01-31 | 2009-08-06 | Arm Norway As | Microprocessor systems |
Also Published As
Publication number | Publication date |
---|---|
US20120303900A1 (en) | 2012-11-29 |
GB201108769D0 (en) | 2011-07-06 |
US9927882B2 (en) | 2018-03-27 |
JP2013016150A (en) | 2013-01-24 |
CN102855122B (en) | 2017-03-01 |
GB2491156B (en) | 2019-08-07 |
JP6017171B2 (en) | 2016-10-26 |
CN102855122A (en) | 2013-01-02 |
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