GB2488307A - A two stage, fully differential operational amplifier in which each stage has a respective common mode feedback loop - Google Patents

A two stage, fully differential operational amplifier in which each stage has a respective common mode feedback loop Download PDF

Info

Publication number
GB2488307A
GB2488307A GB1100917.2A GB201100917A GB2488307A GB 2488307 A GB2488307 A GB 2488307A GB 201100917 A GB201100917 A GB 201100917A GB 2488307 A GB2488307 A GB 2488307A
Authority
GB
United Kingdom
Prior art keywords
common mode
stage
differential
feedback loop
mode feedback
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB1100917.2A
Other versions
GB201100917D0 (en
Inventor
Ian Vidler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elonics Ltd
Original Assignee
Elonics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elonics Ltd filed Critical Elonics Ltd
Priority to GB1100917.2A priority Critical patent/GB2488307A/en
Publication of GB201100917D0 publication Critical patent/GB201100917D0/en
Publication of GB2488307A publication Critical patent/GB2488307A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
    • H03F3/45641—Measuring at the loading circuit of the differential amplifier
    • H03F3/45654—Controlling the active amplifying circuit of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
    • H03F3/45641—Measuring at the loading circuit of the differential amplifier
    • H03F3/45659—Controlling the loading circuit of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45404—Indexing scheme relating to differential amplifiers the CMCL comprising capacitors containing, not in parallel with the resistors, an addition circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45418—Indexing scheme relating to differential amplifiers the CMCL comprising a resistor addition circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45424—Indexing scheme relating to differential amplifiers the CMCL comprising a comparator circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45512—Indexing scheme relating to differential amplifiers the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45528—Indexing scheme relating to differential amplifiers the FBC comprising one or more passive resistors and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45594—Indexing scheme relating to differential amplifiers the IC comprising one or more resistors, which are not biasing resistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45631—Indexing scheme relating to differential amplifiers the LC comprising one or more capacitors, e.g. coupling capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45641—Indexing scheme relating to differential amplifiers the LC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45642—Indexing scheme relating to differential amplifiers the LC, and possibly also cascaded stages following it, being (are) controlled by the common mode signal derived to control a dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45648—Indexing scheme relating to differential amplifiers the LC comprising two current sources, which are not cascode current sources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45702—Indexing scheme relating to differential amplifiers the LC comprising two resistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

A two stage, fully differential operational amplifier in which each stage has a respective common mode feedback loopA CMOS op-amp has a first differential gain stage DS1 having a first common mode feedback loop CMFB1, followed by a second differential gain stage DS2 having a second common mode feedback loop CMFB2. The first common mode feedback loop CMFB1 includes an amplifier 5 to monitor and correct the output of the first differential gain stage DS1 and the second common mode feedback loop CMFB2 includes an amplifier 15 to monitor and correct the output of the second differential gain stage DS2. There is an output buffer stage OS and the second common mode feedback amplifier 15 corrects the output of the second differential gain stage DS2 by monitoring the output of the buffer stage OS. The bandwidth of the op-amp is extended by the use of two gain stages, the first of which has a peak in its frequency response which compensates for the roll-off in the frequency response of the second stage. As a result, the overall 3-dB bandwidth is increased. The arrangement overcomes problems of common mode stability in prior art fully differential op-amps. Frequency compensation is discussed.

Description

Two-stage op-amp The present invention relates to the field of electronic circuits and in particular to op-amps useable for example in telecommunications receivers.
Single chip TV/radio tuners are increasingly found in set top boxes, LCD (Liquid Crystal Display) TVs and mobile products. They have many advantages e.g. low cost, few external components, low power and are physically smaller than traditional metal can tuners.
One important parameter of the tuner is the ability to reject unwanted signals whilst amplifying wanted signals. This function is usually per-Formed by high spec op-amps in a filter / amplifier configuration known as an IF (intermediate frequency) block. The IF block is normally a low pass filter or complex band pass (polyphase) filter placed after the mixer inside the silicon chip tuner. Typically a 7th order Chebyshev filter can be implemented with 14 op-amps. Specifications which are important for the op-amps are gain product bandwidth, noise, spurious free dynamic range (SFDR), linearity, power supply rejection and phase flatness for using in a polyphase (band pass) filter network.
Standard op-amp configurations such as folded cascade amplifiers and two stage amplifiers are known. However, existing approaches have limitations: Standard folded cascade amplifiers have poor bandwidth, phase response and noise.
Standard two stage op-amps use a common source transistor amplifier with Miller compensation for a second stage. This does not have good bandwidth and the Miller capacitor can be quite large to maintain stability.
SUMMARY OF EMBODIMENTS OF THE PRESENT INVENTION
According to an aspect of the present invention, there is provided an op-amp comprising: -a first differential gain stage having a first common mode feedback loop; and -a second differential gain stage in series with the first differential gain stage and having a second common mode feedback loop.
The bandwidth of the op-amp is extended by the use of two gain stages, the first of which has a peak in the frequency response which compensates for the roll-off in the second stage frequency response. As a result the overall 3-dB bandwidth is pushed up in frequency.
Preferably: -the first common mode feedback loop comprises a first common mode feedback amplifier configured to monitor and correct an output of the first differential gain stage; and -the second common mode feedback loop comprises a second common mode feedback amplifier configured to monitor and correct an output of the second differential gain stage.
Preferably, the op-amp further comprises an output buffer stage and the second common mode feedback amplifier is configured to monitor and correct the output of the second differential gain stage by monitoring and correcting an output of the output buffer stage. The output voltage of this buffer stage follows its input voltage, but will have additional drive ability.
Preferably, the first common mode feedback amplifier is configured to control an active load of the first differential gain stage. The current in the load is increased or decreased as appropriate to maintain a common mode level equal to a reference voltage.
Preferably, the second common mode feedback amplifier is configured to control an active load of the second differential gain stage. This maintains a steady common mode voltage at the output of the final buffer stage Preferably, the first differential gain stage comprises differential input pair transistors complementary to those of the second differential gain stage.
This complementary structure maintains the dynamic range and DC biasing conditions of the circuit within the given supply voltage.
Preferably, the first differential gain stage comprises first compensation circuitry configured to provide: -differential mode frequency compensation for the first differential stage; -common mode frequency compensation for the first common mode voltage feedback loop; and -a common mode voltage for the first common mode voltage feedback loop.
Preferably, the first common mode feedback loop comprises second compensation circuitry configured to provide frequency compensation in the first common mode voltage feedback loop.
The first and second compensation circuitry reduce the common mode bandwidth and differential mode bandwidth of the first differential stage to prevent oscillations at high frequency, thus improving the stability of the first common mode feedback loop.
Preferably, the op-amp further comprises third compensation circuitry configured to provide differential mode frequency compensation for the second differential stage (DS2).
Preferably, the op-amp further comprises fourth compensation circuitry configured to provide: -differential mode frequency compensation for the second differential stage; -common mode frequency compensation for the second common mode voltage feedback loop; and -a common mode voltage for the second common mode voltage feedback loop.
The third and fourth compensation circuitry reduce the common mode bandwidth and differential mode bandwidth of the second differential stage to prevent oscillations at high frequency, thus improving the stability of the second common mode feedback loop.
Preferably, the op-amp further comprises an output buffer stage that comprises the fourth compensation circuitry.
Preferably, the second common mode feedback loop comprises fifth compensation circuitry configured to provide frequency compensation in the second common mode voltage feedback loop.
Preferably, the op-amp is a complementary metal-oxide-semiconductor (CMOS) op-amp.
Preferably, the op-amp is operable in a non-inverting closed-loop configuration.
LIST OF ATTACHED FIGURES
The present invention will now be described by way of example only with reference to the accompanying Figures, in which: Figure 1 illustrates a prior art folded cascade op-amp architecture with a one stage amplifier with one common mode feedback loop; Figure 2 illustrates a two-stage op-amp according to an embodiment of the present invention; Figure 3 illustrates the two-stage op-amp of Figure 2 according to an embodiment of the present invention, with detailed labelling of circuit features; Figure 4 illustrates a common mode feedback amplifier having a pmos input suitable for correcting at the output of the first differential gain stage; Figure 5 illustrates a common mode feedback amplifier having an nmos input suitable for correcting at the output of the output buffer stage; Figure 6 illustrates plots of frequency vs. amplitude showing the effect of an embodiment of the present invention; and Figure 7 illustrates a top level system diagram of an op-amp.
DETAILED DESCRIPTION OF THE INVENTION
Op-amps are blocks which amplify signals and which, with external resistors and capacitors, can be made into complex high-order filters with distributed programmable gain.
An embodiment of the present invention is a two stage op-amp using two full differential stages with each stage having its own common mode feedback to enhance the gain bandwidth product & passband phase response. The op-amp has two differential gain stages in series, with a final output buffer stage. Two separate common mode feedback amplifiers are used, one monitoring and correcting the output of the first gain stage and the second monitoring and correcting the output of the final buffer stage.
An embodiment of the present invention provides a two stage op-amp implemented by two fully differential stages (one pmos and the other nmos or one nmos and the other pmos transistors) with two common mode feedback loops (one on each stage). The op-amp is typically used in the inverting configuration and the first differential amplifier stage compensates for the second amplifier stage frequency and phase response. This results in a superior op-amp with increased bandwidth and better passband phase response than the amplifiers based on known op-amps with comparable power consumption.
Figure 1 illustrates a prior art folded cascade op-amp architecture with a one stage amplifier with one common mode feedback loop.
With reference to Figure 2, two differential stages DSI and DS2 are shown with two common mode feedback loops CMFBI and CMFB2. The common mode is the DC voltage on the input & output which is the same (common) to the Vin/out_p (positive input/out) & Vin/out_n (negative input/output). This is an important feature of a fully differential amplifier and a negative feedback amplifier is used to maintain the DC voltage in the middle of the rails. If the common mode voltage drifts to one supply rail the differential signal will be squashed and severe harmonic distortion will occur resulting in dramatic loss of signal quality.
The embodiment has two loops as the common mode is inverting in the first stage and then inverted again in the second stage. If one loop is used (in put first stage to output second stage) the common mode oscillates because there is no negative feedback path. This problem is a reason why two fully differential amplifiers have not been used to form one amplifier in previous approaches. Another important issue is stability of each of the loops. Simple capacitors and resistors are used for differential and common mode stability. These are marked on Figure 3 as A' for stage I and B' for stage 2 these effectively reduce the common mode bandwidth thus stopping it oscillating at high frequencies. The same applies for the differential stability.
Embodiments of the present invention are different to the standard cascade amplifier architectures from CMOS (Complementary design text books, such as shown in Figure 1. Referring back to Figure 1, a difference is the folded cascade, which follows the first differential output stage, and the common mode voltage is thus inverted (only once) from input to output, hence only one negative feedback loop-amplifier required.
With reference to Figure 3, the first differential stage DSI has a current source 1, a differential input pair 2 and active loads 4. The resistors and capacitors in the compensation network circuitry 3 provide differential and common frequency compensation and also the common mode voltage for the common mode feedback (CMFB). Additional frequency compensation for the common mode feedback path is provided by the resistor and capacitor circuitry 6.
According to area and compensation requirements, the capacitors in the compensation networks 3, 13 could be replaced by a resistor and capacitor in series. Similarly, the common mode compensation 6, 14 and the differential compensation 9 could optionally have the resistor removed.
The current source 1 may be a simple or cascaded current source. The active load 4 may be cascaded current loads. The current in the load is controlled by the CMFB amplifier 5 (in the first common mode feedback loop CMFB1) and increased or decreased as appropriate to maintain a common mode level equal to Vrefl.
The differential output of the first differential gain stage DS1 is passed to the second differential gain stage D52, comprised of similar blocks to the first DS1, but using complementary devices. This complementary structure maintains the dynamic range and DC biasing conditions of the circuit within the given supply voltage. If this constraint is not required then a similar structure to the first stage could be maintained.
The second stage is comprised of a current source 7, which may be a simple or cascaded current source, a differential input pair 8 and an active load 10. There is also a differential frequency compensation network 9, which in this case is illustrated as a resistor and capacitor.
The current in the active load 10 is controlled by the second CMFB amplifier 15 (in the second common mode feedback loop CMFB2) in order to maintain a steady common mode voltage at the output of the final buffer stage. The voltage reference Vref2 used for the second CMFB amplifier 15 may, in most cases, be different to the reference voltage Vrefl used for the first CMFB amplifier 5.
The final output buffer stage is comprised of two nmos devices 11 which, along with the current sources 12, make up a source follower stage. The output voltage of this stage will follow its input voltage, but will have additional drive ability. The capacitors in the compensation network 13 provide the required differential frequency compensation. The common mode voltage for the common mode feedback (CMFB) is provided by the resistors in the compensation network 13. Frequency compensation for the common mode feedback path is provided by the resistor and capacitor 14.
Although a pmos input is shown for the first differential stage all of transistors could be replaced by their complementary devices in the signal path, inverting each stage throughout the chain, provided the dynamic range and DC biasing requirements are satisfied.
Thus with reference to Figure 3, the CMOS op-amp has a first differential gain stage (DSI) having a first common mode feedback loop (CMFBI) and a second differential gain stage (DS2) in series with the first differential gain stage (DS1) and having a second common mode feedback loop (CMFB2).
The first common mode feedback loop (CMFBI) has a first common mode feedback amplifier (5) configured to monitor and correct an output of the first differential gain stage (DS1) and the second common mode feedback loop (CMFB2) has a second common mode feedback amplifier (15) configured to monitor and correct an output of the second differential gain stage (DS2). There is an output buffer stage (OS) and the second common mode feedback amplifier (15) is configured to monitor and correct the output of the second differential gain stage (D52) by monitoring and correcting an output of the output buffer stage (OS).
The first common mode feedback amplifier (5) is configured to control an active load (4) of the first differential gain stage (DS1). The second common mode feedback amplifier (15) is configured to control an active load (10) of the second differential gain stage (D52).
The first differential gain stage (DS1) has differential input pair transistors complementary to those of the second differential gain stage (D52).
The first differential gain stage (DS1) has compensation circuitry (3) configured to provide differential mode compensation for the first differential stage (DS1) and common mode frequency compensation for the first common mode voltage feedback loop (CM FBI) and to provide it with a common mode voltage. The first common mode feedback loop (CMFBI) has compensation circuitry (6) configured to provide frequency compensation in it.
The op-amp has compensation circuitry (9) configured to provide differential mode compensation for the second differential stage (DS2).
The op-amp has compensation circuitry (13), in this embodiment in the output buffer stage (OS), configured to provide differential mode compensation for the second differential stage (D52) and common mode frequency compensation for the second common mode voltage feedback loop (CMFB2) and to provide it with a common mode voltage. The second common mode feedback loop (CMFB2) also has compensation circuitry (14) configured to provide frequency compensation in it.
The functions of the compensation circuitry (labelled 3, 6, 9, 13, 14 in Figure 3) are summarised in Table 1.
Compensation First Second Third Fourth Fifth circuitry: Labelin 3 6 9 13 14 Figure 3: Provides first second second differential differential differential differential compensation gain stage gain stage gain stage to: (DSI) (DS2) (D52) Provides first first second second common common common common common mode mode mode mode mode compensation feedback feedback feedback feedback to: loop loop loop loop (CMFBI) (CMFB1) (CMFB2) (CMFB2) Provides first second common common common mode voltage mode mode to: feedback feedback loop loop (CMFB1) (CMFB2) Table 1: Functions of the compensation circuitry.
With reference to Figures 4 and 5, the common mode feedback amplifiers are illustrated. These are a typical, simple amplifier structure, though different circuit architectures could be implemented to achieve a similar effect. The amplifier of Figure 4 has a pmos input and is suitable for correcting at the output of the first differential gain stage 5 with reference to Figure 3. The amplifier of Figure 4 has a nrnos input and is suitable for correcting at the output of the output buffer stage 15 with reference to Figure 3.
One of the benefits of embodiments of the present invention is that the bandwidth of the op-amp is extended by the use of two gain stages, the first of which has a peak in the frequency response which compensates for the roll-off in the second stage frequency response. As a result the overall 3-dB bandwidth is pushed up in frequency.
Figure 6 illustrates this with plots of amplitude vs. frequency response in dB. The plots compare embodiments of the present invention (Figures 2 and 3) and a standard folded cascade, both in the same configuration, as illustrated in Figure 7. Theoretically with an ideal op-amp the 3 dB cut off should be 15.9 MHz (lI2pi*RC). In Figure 7, R = 10K and C = lpF.
The frequency response at high gain (18dB) 62 is 15.7MHz for an embodiment of the present invention. This compares to the standard folded cascade amplifier value 64 of 12 MHz. The correct value with ideal op-amps should be 15.9 MHz. This increased performance is achieved by the first stage compensating the second stage. The frequency boost is in illustrated in Figure 6 where the first stage output 66 is shown.
The performance benefit of the additional bandwidth is particularly apparent when many op-amps are cascaded in an IF (Intermediate Frequency) strip used to implement a high order active filter. For example, in a 7th order complex bandpass Chebyshev filter the invention allows a passband ripple of 0.5dB to be achieved whereas a circuit using previous approaches with comparable power consumption may achieve only 5dB ripple. The primary cause of this difference is that active band pass filters rely on near perfect phase and magnitude response of each op-amp to achieve the total designed filter response. This problem becomes worse for higher filter orders and when the In-phase (I) and Quadrature (Q) paths are used to create the filter.
This peaking observed from the first stage is as a result of the first stage amplifier's operation in a closed loop environment. Within a standard closed loop inverting op-amp configuration, the capacitive differential compensation in stage one will result in a peak in frequency response observed at the output of stage one. This effect will not be observed in the same way if the op-amp is tested without feedback.
ADVANTAGES OF EMBODIMENTS OF THE PRESENT INVENTION
The op-amp of the present invention provides a solution which has enhanced bandwidth and good phase response whilst maintaining good performance in all the other specifications mention above. One of the challenges of using fully differential op-amps is to achieve common mode stability. Embodiments of present invention overcomes this by having two feedback loops using simple components to achieve good stability.
Typically the use of a single loop with two different stages can result in instability.
Particular advantages are: * Enhanced bandwidth (e.g > 200MHz gain product bandwidth).
* Flatter phase response.
Flatter pass band response when used in high order filters.
* Enhanced image rejection when used in a polyphase bandpass filter network. This is of particular advantage to TV/radio tuners as interfering signals could fall in the image of the filter.
* Low noise.
* Low power (<1.5 mW in 0.13u process).
* High linearity & SFDR (>70dB).
* Programmable gain, close ioop 0 to 20dB. (open loop > 60dB).
* Good common mode stability.
* Low cost (small area).
* No external calibration is required for process variations.
* High performance particularly in band pass (poly phase) filter networks applications as standard op-amps architecture have poor performance in passband flatness and image rejection parameters for high order filters.
* Low power (reduce size of set top boxes and has an ecological advantage).
* CMOS process (low cost and can be integrated with digital blocks thus reducing the size even further).
Further modifications and improvements may be added without departing from the scope of the invention herein described.

Claims (14)

  1. Claims 1. An op-amp comprising: -a first differential gain stage having a first common mode feedback loop; and -a second differential gain stage in series with the first differential gain stage and having a second common mode feedback loop.
  2. 2. The op-amp of claim 1, wherein: -the first common mode feedback loop comprises a first common mode feedback amplifier configured to monitor and correct an output of the first differential gain stage; and -the second common mode feedback loop comprises a second common mode feedback amplifier configured to monitor and correct an output of the second differential gain stage.
  3. 3. The op-amp of claim 2, further comprising an output buffer stage and wherein the second common mode feedback amplifier is configured to monitor and correct the output of the second differential gain stage by monitoring and correcting an output of the output buffer stage.
  4. 4. The op-amp of claim 2 or claim 3, wherein the first common mode feedback amplifier is configured to control an active load of the first differential gain stage.
  5. 5. The op-amp of any of claims 2 to 4, wherein the second common mode feedback amplifier is configured to control an active load of the second differential gain stage.
  6. 6. The op-amp of any previous claim, wherein the first differential gain stage comprises differential input pair transistors complementary to those of the second differential gain stage.
  7. 7. The op-amp of any previous claim, wherein the first differential gain stage comprises first compensation circuitry configured to provide: -differential mode frequency compensation for the first differential stage; -common mode frequency compensation for the first common mode voltage feedback loop; and -a common mode voltage for the first common mode voltage feedback loop.
  8. 8. The op-amp of any previous claim, wherein the first common mode feedback loop comprises second compensation circuitry configured to provide frequency compensation in the first common mode voltage feedback loop.
  9. 9. The op-amp of any of any previous claim, further comprising third compensation circuitry configured to provide differential mode frequency compensation for the second differential stage.
  10. 10. The op-amp of any of any previous claim, further comprising fourth compensation circuitry configured to provide: -differential mode frequency compensation for the second differential stage; -common mode frequency compensation for the second common mode voltage feedback loop; and -a common mode voltage for the second common mode voltage feedback loop.
  11. 11. The op-amp of claim 10, further comprising an output buffer stage that comprises the fourth compensation circuitry.
  12. 12. The op-amp of any previous claim, wherein the second common mode feedback loop comprises fifth compensation circuitry configured to provide frequency compensation in the second common mode voltage feedback loop.
  13. 13. The op-amp of any previous claim, wherein the op-amp is a complementary metal-oxide-semiconductor op-amp.
  14. 14. The op-amp of any previous claim, wherein the op-amp is operable in a non-inverting closed-loop configuration.
GB1100917.2A 2011-01-19 2011-01-19 A two stage, fully differential operational amplifier in which each stage has a respective common mode feedback loop Withdrawn GB2488307A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB1100917.2A GB2488307A (en) 2011-01-19 2011-01-19 A two stage, fully differential operational amplifier in which each stage has a respective common mode feedback loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1100917.2A GB2488307A (en) 2011-01-19 2011-01-19 A two stage, fully differential operational amplifier in which each stage has a respective common mode feedback loop

Publications (2)

Publication Number Publication Date
GB201100917D0 GB201100917D0 (en) 2011-03-02
GB2488307A true GB2488307A (en) 2012-08-29

Family

ID=43736673

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1100917.2A Withdrawn GB2488307A (en) 2011-01-19 2011-01-19 A two stage, fully differential operational amplifier in which each stage has a respective common mode feedback loop

Country Status (1)

Country Link
GB (1) GB2488307A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103825565A (en) * 2012-11-16 2014-05-28 上海华虹宏力半导体制造有限公司 Operational amplifier
EP3021482A1 (en) * 2014-11-17 2016-05-18 MediaTek, Inc Operational amplifier based circuit with compensation circuit block used for stability compensation
WO2016085668A1 (en) * 2014-11-25 2016-06-02 Qualcomm Incorporated Compensated common-mode feedback for an amplifier
GB2533310A (en) * 2014-12-15 2016-06-22 Nordic Semiconductor Asa Active RC filters
US10277072B2 (en) 2014-01-08 2019-04-30 Mediatek Singapore Pte. Ltd. Wireless power receiver with programmable power path
EP4057506A4 (en) * 2019-11-28 2022-11-02 Huawei Technologies Co., Ltd. Operational amplifier, chip and electronic device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110289820B (en) * 2019-07-25 2024-06-11 唐太平 Operational amplifier circuit

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060284678A1 (en) * 2005-06-21 2006-12-21 Analog Devices, Inc. Flip around switched capacitor amplifier
US20070241793A1 (en) * 2004-03-18 2007-10-18 Intersil Americas Inc. Current feedback amplifiers
US20080231365A1 (en) * 2007-03-21 2008-09-25 Lee Hyunjoong Operational amplifier
US20080284513A1 (en) * 2007-05-17 2008-11-20 Realtek Semiconductor Corp. Fully differential amplifier
US20080315951A1 (en) * 2007-06-19 2008-12-25 Jeffrey Rysinski Class ab differential amplifier with output stage common mode feedback
US7532072B1 (en) * 2007-03-02 2009-05-12 Linear Technology Corporation Method to control the output common mode in a differential OPAMP with rail-to-rail input stage

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070241793A1 (en) * 2004-03-18 2007-10-18 Intersil Americas Inc. Current feedback amplifiers
US20060284678A1 (en) * 2005-06-21 2006-12-21 Analog Devices, Inc. Flip around switched capacitor amplifier
US7532072B1 (en) * 2007-03-02 2009-05-12 Linear Technology Corporation Method to control the output common mode in a differential OPAMP with rail-to-rail input stage
US20080231365A1 (en) * 2007-03-21 2008-09-25 Lee Hyunjoong Operational amplifier
US20080284513A1 (en) * 2007-05-17 2008-11-20 Realtek Semiconductor Corp. Fully differential amplifier
US20080315951A1 (en) * 2007-06-19 2008-12-25 Jeffrey Rysinski Class ab differential amplifier with output stage common mode feedback

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103825565B (en) * 2012-11-16 2016-10-26 上海华虹宏力半导体制造有限公司 Operational amplifier
CN103825565A (en) * 2012-11-16 2014-05-28 上海华虹宏力半导体制造有限公司 Operational amplifier
US10277072B2 (en) 2014-01-08 2019-04-30 Mediatek Singapore Pte. Ltd. Wireless power receiver with programmable power path
EP3021482A1 (en) * 2014-11-17 2016-05-18 MediaTek, Inc Operational amplifier based circuit with compensation circuit block used for stability compensation
CN105610403A (en) * 2014-11-17 2016-05-25 联发科技股份有限公司 Operational amplifier based circuit
CN105610403B (en) * 2014-11-17 2019-01-08 联发科技股份有限公司 Circuit based on operational amplifier
US9979350B2 (en) 2014-11-17 2018-05-22 Mediatek Inc. Operational amplifier based circuit with compensation circuit block used for stability compensation
WO2016085668A1 (en) * 2014-11-25 2016-06-02 Qualcomm Incorporated Compensated common-mode feedback for an amplifier
US9385672B2 (en) 2014-11-25 2016-07-05 Qualcomm Incorporated Compensated common-mode feedback for an amplifier
CN107112962A (en) * 2014-12-15 2017-08-29 北欧半导体公司 Active RC filter
US10153742B2 (en) 2014-12-15 2018-12-11 Nordic Semiconductor Asa Active RC filters
WO2016097706A1 (en) * 2014-12-15 2016-06-23 Nordic Semiconductor Asa Active rc filters
GB2533310A (en) * 2014-12-15 2016-06-22 Nordic Semiconductor Asa Active RC filters
EP4057506A4 (en) * 2019-11-28 2022-11-02 Huawei Technologies Co., Ltd. Operational amplifier, chip and electronic device

Also Published As

Publication number Publication date
GB201100917D0 (en) 2011-03-02

Similar Documents

Publication Publication Date Title
GB2488307A (en) A two stage, fully differential operational amplifier in which each stage has a respective common mode feedback loop
US8787511B2 (en) Frequency and Q-factor tunable filters using frequency translatable impedance structures
US7705682B2 (en) Inductor sharing in radio frequency communications
US7948309B2 (en) DC-offset cancelled programmable gain array for low-voltage wireless LAN system and method using the same
Chen et al. A 2V pp, 80-200MHz fourth-order continuous-time linear phase filter with automatic frequency tuning
US20120182075A1 (en) Apparatus and method for miller compensation for multi-stage amplifier
US20120212288A1 (en) Band pass filter and calibration method for band pass filter
WO2010025556A1 (en) A passive transmitter architecture with switchable outputs for wireless applications
GB2415102A (en) PLL circuit and frequency-setting circuit
US9172354B2 (en) Analog active low-pass filters
US20110163808A1 (en) Amplifier with improved input resistance and controlled common mode
WO2014136402A1 (en) Mixer circuit
US20110163803A1 (en) Programmable Gain Amplifier and Embedded Filter
US9621139B2 (en) Single phase differential conversion circuit, balun, switch, and communication device
EP3096452B1 (en) Operational amplifier circuit with dc offset suppression
US20200382072A1 (en) Amplifier circuit with high-order damping circuit and the high-order damping circuit
US20120049920A1 (en) Iq signal generation circuit
US9692471B2 (en) Wireless receiver with high linearity
US20140266439A1 (en) Methods and systems to provide low noise amplification
US9698738B2 (en) Bandpass filter providing wide gain control range
US9419587B1 (en) Method and apparatus to reconfigure a filter
KR20080075522A (en) Enhanced mixer device
CN109873620B (en) Third-order low-pass filter
US10135404B2 (en) Calibration of push-pull amplifier to a low second order distortion
Kuo A 5th order Gm-C filter design with wide tuning transconductor

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)