GB2486378B8 - Sram delay circuit that tracks bitcell characteristics - Google Patents

Sram delay circuit that tracks bitcell characteristics

Info

Publication number
GB2486378B8
GB2486378B8 GB1205684.2A GB201205684A GB2486378B8 GB 2486378 B8 GB2486378 B8 GB 2486378B8 GB 201205684 A GB201205684 A GB 201205684A GB 2486378 B8 GB2486378 B8 GB 2486378B8
Authority
GB
United Kingdom
Prior art keywords
bitcell
tracks
delay circuit
sram delay
sram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB1205684.2A
Other versions
GB2486378A (en
GB2486378B (en
GB2486378A8 (en
GB201205684D0 (en
Inventor
Igor Arsovski
George Braceras
Robert M Houle
Harold Pilo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/581,440 external-priority patent/US8233337B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB201205684D0 publication Critical patent/GB201205684D0/en
Publication of GB2486378A publication Critical patent/GB2486378A/en
Publication of GB2486378B publication Critical patent/GB2486378B/en
Application granted granted Critical
Publication of GB2486378A8 publication Critical patent/GB2486378A8/en
Publication of GB2486378B8 publication Critical patent/GB2486378B8/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
GB1205684.2A 2009-10-19 2010-09-08 Sram delay circuit that tracks bitcell characteristics Expired - Fee Related GB2486378B8 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/581,440 US8233337B2 (en) 2009-10-19 2009-10-19 SRAM delay circuit that tracks bitcell characteristics
PCT/US2010/048052 WO2011049679A1 (en) 2009-10-19 2010-09-08 Sram delay circuit that tracks bitcell characteristics

Publications (5)

Publication Number Publication Date
GB201205684D0 GB201205684D0 (en) 2012-05-16
GB2486378A GB2486378A (en) 2012-06-13
GB2486378B GB2486378B (en) 2014-06-04
GB2486378A8 GB2486378A8 (en) 2016-03-23
GB2486378B8 true GB2486378B8 (en) 2016-03-23

Family

ID=46086104

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1205684.2A Expired - Fee Related GB2486378B8 (en) 2009-10-19 2010-09-08 Sram delay circuit that tracks bitcell characteristics

Country Status (1)

Country Link
GB (1) GB2486378B8 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072733A (en) * 1997-10-17 2000-06-06 Waferscale Integration, Inc. Programmable sense amplifier delay (PSAD) circuit which is matched to the memory array
US6473356B1 (en) * 2001-11-01 2002-10-29 Virage Logic Corp. Low power read circuitry for a memory circuit based on charge redistribution between bitlines and sense amplifier

Also Published As

Publication number Publication date
GB2486378A (en) 2012-06-13
GB2486378B (en) 2014-06-04
GB2486378A8 (en) 2016-03-23
GB201205684D0 (en) 2012-05-16

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Legal Events

Date Code Title Description
746 Register noted 'licences of right' (sect. 46/1977)

Effective date: 20140619

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20160908