GB2475636A

GB2475636A - An audio amplifier with a controllable split supply for the output stage

Info

Publication number: GB2475636A
Application number: GB1103080A
Authority: GB
Inventors: John Paul Lesso; John Laurence Pennock; Peter John Frith
Original assignee: Wolfson Microelectronics PLC
Current assignee: Cirrus Logic International UK Ltd
Priority date: 2006-12-22
Filing date: 2006-12-22
Publication date: 2011-05-25
Anticipated expiration: 2026-12-22
Also published as: GB2475636B; GB201103080D0

Abstract

The power supply 80 for an audio amplifier output stage 40 provides voltages which vary in dependence on a volume control signal S2 which controls the gain of amplifier stage 20. The power supply comprises a flying capacitor charge pump circuit (figures 5b, 16b) which provides opposite polarity supplies from a single polarity input. The charge pump may be fed through a controllable DC-DC buck converter (1010, figure 26), which can be bypassed when the battery voltage is low. The supply voltages may be regulated (figure 15). The charge pump may have dual modes (figures 10, 16b) wherein it can be controlled to provide outputs which are either equal to the input voltage or a fraction of the input voltage. Only one flying capacitor is required to provide a split supply of +/- VDD/2.

Description

Amplifier Circuit and Methods of Operation Thereof The present invention relates to circuitry for improving the efficiency of an amplifier.

The invention further relates to a method for improving the efficiency of an amplifying circuit.

When receiving information signals, such as audio signals for example, for outputting to one or more transducers, such as a speaker for example, the information signals generally need to be adjusted in amplitude. One method of achieving this adjustment includes using a control signal, an example of such a signal being a gain control signal, which varies the gain, and thus the amplitude, of the information signal prior to outputting to the transducer.

Figure 1 illustrates an example of a known amplifier 10 The amplifier 10 comprises a gain controller 20; an output stage 40; and a power supply 60.

The gain controller 20 receives an input information signal Si and an input control signal S2. The control signal S2 controls the gain controller 20 that outputs a gain controlled information signal S3 which is fed as an input signal into the output stage 40. The output stage 40 outputs an output signal S4 that is used to drive a load 70.

The output stage 40 and the gain controller 20 are supplied by the power supply 60 which takes power from some external power source and supplies dual, fixed level, supply voltages +V1 and -Vi.

The amplitude of the output signal S4 that drives the load 70 is varied i.e. amplified or attenuated, in response to the control input signal S2, by the combined gain of the gain controller 20 and output stage 40.

The power efficiency of the amplifier 10, i.e. the ratio of the power delivered to the load to the power taken from the power source, is an important parameter of the amplifier. It impacts both power consumption, which is important in battery-powered systems for example, and power dissipation, which influences cost in terms of heatsinking for example.

There are thus advantages in methods and circuits for improving the efficiency of amplifiers such as amplifier 10.

In a first aspect of the invention there is provided a signal amplifying circuit comprising: A main input terminal for receiving an input signal; A main output terminal for outputting an output signal; a signal path extending from the input terminal to the output terminal; a gain controer arranged to control the gain applied along said signai path in response to a Control signal; an output stage within said signal path for generating said output signal, said output stage having a gain that is substantially independent of its supply voltage, a variable voltage power supply comprising a charge pump circuit for providing a plurality of output voltages, the circuit comprising: -an input terminal and a common terminal for connection to an input voltage, -first and second output terminals for outputting said plurality of output voltages, said output terminals in use being connected to said common terminal via respective first and second loads and also via respective first and second reservoir capacitors, -first and second flying capacitor terminals for connection to a flying capacitor, -a network of switches that is operable in a plurality of different states for interconnecting said terminals, and -a controller for operating said switches in a sequence of said states, said sequence being adapted repeatedly to transfer packets of charge from said input terminal to said reservoir capacitors both directly and via said flying capacitors depending on the state, and thereby in a steady state to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage, and centred on the voltage at the common terminal; wherein said variable voltage power supply is arranged to vary a supply voltage of said output stage in response to said control signal.

In a further aspect of the invention there is provided a signal amplifying circuit comprising: A main input terminal for receiving an input signal; A main output terminal for outputting an output signal; a signal path extending from the input terminal to the output terminal; a gain controller arranged to control the gain applied along said signal path in response to a control signal; an output stage within said signal path for generating said output signal, said output stage having a gain that is substantially independent of its supply voltage, a variable voltage power supply comprising a charge pump circuit for providing a plurality of output voltages, the circuit comprising: -an input terminal and a common terminal for connection to an input voltage, -first and second output terminals for outputting said plurality of output voltages, said output terminals in use being connected to said common terminal via respective first and second loads and also via respective first and second reservoir capacitors, -one or more pairs of flying capacitor terminals, each pair comprising first and second flying capacitor terminals for connection to one or more flying capacitors, the number of flying capacitors equalling n, -a network of switches that is operable in a plurality of different states for interconnecting said terminals, and -a controller for operating said switches in a sequence of said states, said sequence being adapted repeatedly to transfer packets of charge from said input terminal to said reservoir capacitors both directly and via said flying capacitors depending on the state and thereby, in a steady state, to generate positive and negative output voltages each of a magnitude up to substantially a fraction of said input voltage; wherein said variable voltage power supply is arranged to vary a supply voltage of said output stage in response to said control signal.

The term "fraction" is used here in its mathematical sense, that is a ratio of two whole numbers.

In a further aspect of the invention there is provided a signal amplifying circuit comprising: A main input terminal for receiving an input signal; A main output terminal for outputting an output signal; a signal path extending from the input terminal to the output terminal; a gain controller arranged to control the gain applied along said signal path in response to a control signal; an output stage within said signal path for generating said output signal, said output stage having a gain that is substantially independent of its supply voltage, a variable voltage power supply comprising a charge-pump circuit for providing a plurality,of output voltages, said circuit comprising: -an input terminal and a common terminal for connection to an input voltage, first and second output terminals for outputting said plurality of output voltages, said first and second output terminals being, in use, connected to said common terminal via respective first and second loads and also via respective first and second reservoir capacitors, -at least first and second flying capacitor terminals for connection to at least one flying capacitor, -a network of switches that is operable in a plurality of different states for interconnecting said terminals, and -a controller for operating said network of switches in a sequence of said different states, wherein said controller is operable in first and second modes, the first of said modes generating positive and negative output voltages each of a magnitude up to substantially a fraction of said input voltage; wherein said variable voltage power supply is arranged to vary a supply voltage of said output stage in response to said control signal.

In a further aspect of the invention there is provided a signal amplifying circuit comprising: A main input terminal for receiving an input signal; A main output terminal for outputting an output signal; a signal path extending from the input terminal to the output terminal; a gain controller arranged to control the gain applied along said signal path in response to a control signal; an output stage within said signal path for generating said output signal, said output stage having a gain that is substantially independent of its supply voltage, -a variable voltage power supply comprising a charge pump circuit for providing a split-rail voltage supply, the charge pump circuit comprising: --a common terminal an input supply terminal for connection to a supply at an input voltage relative to said common terminal, first and second output terminals for carrying said split-rail supply, said output terminals in use being connected said common terminal via respective first and second loads and also via respective first and second reservoir capacitors, first and second flying capacitor terminals for connection to a first flying capacitor, -third and fourth flying capacitor terminals br connection to a second flying capacitor, a network of switches interconnecting said terminals and being operable in a number of different states, and -a controller for operating said switches in a sequence of said states, said sequence being adapted repeatedly to transfer packets of charge to said reservoir capacitors via said flying capacitors and thereby, in a steady state, to generate said split rail supply with positive and negative output voltages together spanning a voltage approximately equal to the input voltage, and centred on the voltage at the common terminal.

wherein said variable voltage power supply is arranged to vary a supply voltage of said output stage in response to said control signal.

In a further aspect of the invention there is provided a method of amplifying an input signal to generate a gain controlled output signal, said method comprising: receiving an input signal on a first input terminal of an amplifier circuit; receiving an control signal on a second input terminal of said amplifier circuit; applying a gain to said input signal in response to said control signal to produce said gain controlled output signal at an output terminal of an output stage of said amplifier circuit wherein said gain is independent of a supply voltage of said output stage; and varying said supply voltage applied to said output stage in response to said control signal wherein said supply voltage is supplied by a variable voltage power supply as incorporated in any of the amplifying circuits of claims.

The invention also provides for an audio apparatus, portable audio apparatus, communications apparatus, in-car audio apparatus or headphone amplifier incorporating an amplifier circuit or an output amplifier apparatus as described above.

The invention also provides for electronic apparatus comprising an output transducer and an amplifier circuit or an output amplifier apparatus as described above having its output terminal connected to drive said output transducer as said load.

The invention further provides for an RE transmitter apparatus comprising an amplifier circuit or an output amplifier apparatus as described above having its output stage adapted to drive an antenna as said load.

The invention further provides for a line driver for driving a signal through a transmission line, the line driver incorporating the signal amplifying apparatus as described above adapted for driving a transmission line as said load. Said line driver may comprise part of a modem device further comprising a modulator, demodulator and controller.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments of the invention are described hereinafter with reference to the accompanying drawings in which:

Figure 1 shows a prior art amplification circuit;

Figure 2a shows apparatus according to a first embodiment of the invention; Figure 2b illustrates a signal flow diagram of the first embodiment illustrated in Figure 2a.

Figure 3 shows waveforms associated with the embodiment of Figure 2a; Figures 4(a) to 4(c) show waveform relationships associated with the embodiment of Figure 2a; Figure 5a shows a Level Shifting Charge Pump circuit according to a first main embodiment of the invention; Figure 5b shows the same circuit as Figure 4a with detail of the switch array shown; Figures 6a and 6b show, respectively, the circuit of Figure 5 operating in (Mode 1), state 1 and an equivalent circuit of this state; Figures 7a and 7b show, respectively, the circuit of Figure 5 operating in (Mode 1), state 2 and an equivalent circuit of this state; Figures 8a and 8b show, respectively, the circuit of Figure 5 operating in (Mode 1), state 3 and an equivalent circuit of this state; Figure 9 is a timing diagram showing three switch control signals for the circuit of Figure 5 operating according to an operative embodiment of the invention (in Mode 1); Figure 10 shows a Dual Mode Charge Pump circuit according to a first main embodiment of the invention.

Figures ha and lib show, respectively, the circuit of Figure 5 operating in Mode 2, state 6 and an equivalent circuit of this state; Figures 12a and 12b show, respectively, the circuit of Figure 5 operating in Mode 2, state 2 and an equivalent circuit of this state; Figures 13a and 13b show, respectively, the circuit of Figure 5 operating in Mode 2, state 7 and an equivalent circuit of this state; Figure 14 is a timing diagram showing three switch control signals for the circuit of Figure 5 operating according to an operative embodiment of the invention in Mode 2; Figure 15 shows a variation on the circuit of Figure 5, operable in a closed loop configuration; Figure 16a shows a Level Shifting Charge Pump circuit according to a second main embodiment of the invention; Figure 16b shows the same circuit as Figure 16a with detai of the switch array shown; Figures 1 7a and 1 7b show, respectively, the circuit of Figure 16 operating in (Mode 1), state 1 and an equivalent circuit of this state; Figures 18a and 18b show, respectively, the circuit of Figure 16 operating in (Mode 1), state 2 and an equivalent circuit of this state; Figures 19a and 19b show, respectively, the circuit of Figure 16 operating in (Mode 1), state 3 and an equivalent circuit of this state; Figure 20 is a timing diagram showing three switch control signals for the circuit of Figure 16 operating according to an operative embodiment of the invention (in Mode 1); Figures 21a and 21b show a Dual Mode Charge Pump according to a second main embodiment of the invention, respectively operating in Mode 2, state 8 and an equivalent circuit of this state; Figures 22a and 22b show a Dual Mode Charge Pump according to a second main embodiment of the invention, respectively the circuit of Figure 16 operating in Mode 2, state 2 and an equivalent circuit of this state; l0 Figure 23 is a timing diagram showing two switch control signals for the circuit of Figure 16 operating according to an operative embodiment of the invention in Mode 2; Figure 24 shows a variation on the circuit of Figure 16, operable in a closed loop configuration; Figure 25 shows a variable voltage power supply of a type suitable for any of the novel amplifiers disclosed herein whereby a number of different input voltage values may be selected as an input voltage to any of the Level Shifting/Dual Mode Charge Pumps disclosed herein; Figure 26 shows a variable voltage power supply of a type suitable for any of the novel amplifiers disclosed herein; Figures 27a to 27e show apparatus according to a third embodiment of the invention with alternatives; Figures 28a-28c shows apparatus according at a fourth embodiment of the invention with alternatives; Figures 29a and 29b show two alternative apparatus according to a fifth embodiment of the invention; Figure 30 shows schematically a first system using the invention according to the second embodiment; and -Figure 31 shows schematically a second system using the invention according to the first embodiment.

DETAILED DESCRIPTION

Example embodiments of circuitry, apparatus and methods described below primarily concern audio applications. However, it will be appreciated by those skilled in the art that other applications to which the present invention is equally applicable are possible and a few such applicable applications are herein described and illustrated.

II

Basic Amplifier Design Figure 2a illustrates an embodiment of a novel amplifier 100 that has been designed to improve the efficiency over devices such as the amplifier 10 described above.

In this particular embodiment, the amplifier 100 comprises: the gain controller 20; the output stage 40 and the power supply 60 as described above. However, amplifier 100 differentiates itself in a first respect from amplifier 10 in that it includes a variable voltage second supply 80 in addition to the fixed voltage first power supply 60.

The gain controller 20 receives an audio input signal Si and a gain, e.g. a volume, control signal S2'. Amplifier 100 differentiates itself in a second respect from amplifier in that, the control signal S2' has a dual purpose. One such purpose is to control the gain controller 20. The controller 20 outputs a gain controlled sigra S3, used as an input signal into the output stage 40 which in turn outputs an output signal S4' that is used to drive a load 70 such as a speaker for example.

The output stage 40 is supplied by the variable voltage power supply 80 that is controlled in response to the control signal S2'. Therefore, the single control signal, S2', has the dual purpose of: (1) controlling the gain controller 20; and (2) controlling the variable voltage power supply 80. It should be noted that the output stage 40 is independent or substantially independent (ignoring power supply rejection issues and the like) of the variable voltage power supply 80. The operational efficiency of the amplifier 100 is affected by the voltage of its supplies and in particular the voltage supplied to the output, i.e. power, stage 40. Therefore, the single control signal, S2', controls both the gain of the amplifier 100 and its operational efficiency, as will be described in more detail below.

Moreover, the variable voltage power supply 80 is operatively arranged in such a way, as will be described in more detail below, that the output stage 40 supply voltages +Vout and -Vout are varied sufficiently enough in response to the control signal S2' to avoid clipping of the output signal S4'.

The variable voltage power supply 80 receives a fixed supply voltage from some power source (not illustrated), such as, but not necessarily, the fixed voltage first power supply 60. The variable voltage power supply 80 is implemented as a "Level Shifting Charge Pump" or "Dual Mode Charge Pump" circuit as described later. This charge pump may, in turn, receive its input voltage from a variable voltage DC-DC converter (such as a Buck Converter) either directly or via a linear regulator such as a Low drop Out regulator. This allows the charge pump outputs to be varied as required by controlling the DC-DC converter and therefore the input to the charge pump.

By way of one possible illustrative example of how the amplifier 100 may be used and controlled let us assume that the amplifier 100 is an audio amplifier for amplifying an audio input signal Si wherein: the variable voltage power supply 80 is a Level Shifting Charge Pump circuit; the gain controller 20 and output stage 40 are linear amplifiers, such as class AB amplifiers for example; the control signal S2' is a volume control signal; and the load 70 is a speaker.

The controi signal S2' controls the overa gain of the amplifier 100 in order to change the output volume of the speaker 70. The output volume may be changed in a conventional manner wherein the output volume, i.e. the amplitude of the output signal S4', is varied in response to a volume controller (not illustrated), such as a potentiometer for example, being manipulated by a user. Therefore, the input signal Si is scaled by a factor determined by the gain of the amplifier 100 which is controlled in response to the volume control signal S2'.

However, according to the novel amplifier 100, the volume control signal S2' also controls the variable voltage power supply 80. Therefore, the variable voltage power supply 80 produces both positive and negative ground reference supply voltages, respectively +Vout and -Vout, that vary in response to the volume control signal S2'.

For the ease of understanding and conciseness of the description, let us assume that ÷Vout and -Vout are of equal magnitude, Vout. This is not a necessary condition, but in most practical designs ÷Vout and -Vout would have equal or substantially equal magnitudes. It should be noted that In order to prevent the output signal S4' from ever clipping, i.e. distorting, the amplifier 100 should be designed and controlled such that: Vout = IVS4'I + Vx (Equation 1) where; Vout is the magnitude of output voltage of the variable voltage power supply 80; IVS4'I is the maximum voltage amplitude of the output signal S4'; and Vx is the headroom voltage between output signal S4' and supply voltage Vout that is required by the amplifier output stage 40 to avoid the output signal S4' clipping; and VS4' = VS1 max x G (Equation 2) where: VS1 max is a predetermined maximum permissible voltage amplitude of the input signal S; and G is the gain of the amplifier 100, as determined by the respective gains of the controller 20 and the output stage 40.

VSlmax will generally be predetermined from the design specification of the system, in terms of the maximum input voltage permissible to guarantee avoidance of clipping or to guarantee some other signal distortion specification. In some cases, an application may receive signals larger than the anticipated, i.e. designed, maximum signal and as a result, the output signal may clip or give extra distortion, but performance under such overload conditions is not important. In some cases, for example where the input signal is derived from a digital source or is output from a DAC, there may be a well-defined maximum signal level, set by the word-length or the full-scale reference voltage of the DAC, which the input signal can never exceed.

From Equations 1 & 2, it can be seen that the output voltage Vout of the variable voltage power supply 80 is preferably linearly dependent on the gain G of the amplifier for a given maximum input signal VSlmax.

It can be appreciated from the above description that when the volume, i.e. gain, control signal S2' is increased, the output signal S4' amplitude, and hence volume, increases as a result of the increased gain G of the amplifier 100. At the same time, the volume control signal S2' acts upon the variable voltage power supply 80 and changes its output voltages +Vout and -Vout accordingly in response to the control signal S2'. The way that the variable voltage power supply 80 changes the output voltages will become apparent later.

It should be noted that the headroom voltage Vx is preferably kept to a minimum, for a particular design embodiment, so as to minimise the power loss in the amplifier and help maintain overall efficiency.

The variable voltage power supply 80 may be designed such that its output voltages +Vout and -Vout change substantially continuously with the control signal S2'. This may include the possibility of a digital control (not illustrated) with fine resolution.

Alternatively, the variable voltage power supply 80 may be designed such that its output voltages +Vout and -Vout change between a plurality of discrete voltage levels as the control signal S2' changes.

Figure 2b illustrates a signal flow diagram of the embodiment illustrated in Figure 2a.

From Figure 2b it can be seen that: signal Sc is a function of signals Sa and Sb; signal Sd is a function of signal Sb; and signal Se is a function of only signal Sc since signal Se is independent, or substantially independent, of signal Sd, wherein: signal Sa represents the input signal Si; signal Sb represents the control signal S2'; signal Sc represents the gain controlled signal S3; signal Sd represents the voltage signal Vout; and signal Se represents the output signal S4'.

Figure 3 illustrates a waveform plot of voltage against time for the arrangement of Figure 2a over a time span during which the volume control signal S2' is reduced.

Period Ti of Figure 3 represents the amplifier 100 when its control signal S2' is set to its maximum value. It should be noted that during this period the efficiency of both the respective amplifiers 10 and 100 of Figures 1 and 2 would be the same, or substantially the same for the same signal conditions, since their respective supply voltages +/V1 and +/-Vout are equal.

Referring to Period Ti in conjunction with Figure 2a and considering just the positive excursion of the output signal S4' (since the same equally applies to the negative excursion), the power delivered to the load 70 at the peak voltage VS4maxl of the output signal S4' is the product of the load current ILl (not illustrated) and VS4'maxl: where IL1=VS4'maxi/RL and RL is the resistance of the load 70. The voltage VS4'maxl is specified to allow a certain headroom voltage Vx between the peak output signal voltage VS4'maxl and the supply voltage +Voutmax in order for the correct operation of the output stage 40, where Vx=+Voutmax-VS4maxl. The power dissipated by having this headroom voltage Vx is wasted power PW1 which is given by the product of the load current ILl and Vx. This power PW1 serves no purpose other than to ensure the correct operation, i.e. it avoids distortion through signal clipping, of the output stage 40.

It can be seen that during period Ti, where S4' is at or near the maximum signal level that either amplifier 10, 100 can comfortably cope with, the amplifier 100 of Figure 2a operates in substantially the same way and is therefore no more efficient than the amplifier 10 illustrated in Figure 1 since under the conditions of period Ti the respective amplifiers 10 and 100, supply voltages +/-V1 and ÷f-Vout are the same.

Period T2 of Figure 3 represents the anipUfier 100 when its control signal S2' is set to a value between its maximum and minimum values and therefore output signal S4' has a smaller amplitude than during period Ti.. Unlike for the period Ti, the respective efficiencies of the respective amplifiers 10 and 100 of Figures 1 and 2 are substantially different since the output voltage of amplifier 10 of Figure 1 remains, as always, at its fixed level +/-V1, as indicated by the dash-dot lines, whereas the dynamic output voltage +/-Vout of the variable voltage power supply 80 has been adjusted, by the control signal S2', to a new level +/-Voutbet. It can been seen that during this period T2 the efficiency of the amplifier 100 of Figure 2a has been improved quite substantially over that associated with the amplifier 10 of Figure 1 as can be deduced from comparing the amplitudes of the voltages Vx and Va during this period T2.

This improvement in efficiency can be seen by referring to Period T2 in conjunction with Figure 2a, over the positive excursion. The power delivered to the load 70 at the peak voltage VS4'max2 is the product of the load current lL2 (not illustrated) and VS4'max2: where 1L2=VS4'max2/RL. Again the power dissipated by having this headroom voltage Vx is wasted power. However, the amplifier 100 during period T2 operates differently to the amplifier 10 of Figure 1, in having supply rails at +/-Voutbet, while the supply voltages of amplifier 10 are fixed at +/-V1. Therefore it can be seen that the power PW2 saved by the amplifier 100, over amplifier 10, is given by the product of the load current lL2 and the voltage Va, where Va=V1-Voutbet.

Period T3 of Figure 3 represents the amplifier 100 when its volume control signal S2' is set to its minimum value, such that the output signal level is very low but possibly still audible. Again, unlike for period Ti, during this period T2 the respective efficiencies of the respective amplifiers 10 and 100 of Figures 1 and 2 are substantially different since the output voltage of amplifier 10 of Figure 1 remains at its fixed levels +/-V1, as indicated by the dash-dot lines, whereas the dynamic output voltage +/-Vout of the variable voltage power supply 80 has been adjusted, by the control signal S2', to a new level +/-Voutrnin. It can been seen that during this period T3 the efficiency of the amplifier 100 of Figure 2a has been improved substantially over thai associated with the amplifier 10 of Figure 1 as can be deduced from comparing the amplitudes of the voltages Vx and Vb during this period 13.

The improvement in efficiency is again illustrated by referring to Period T3 in conjunct;on with Figure 2a over the positive excursion. The power delivered to the load 70 at the peak voltage VS4'max3 is the product of the load current 1L3 (not illustrated) and VS4'max3, where 1L3=VS4'max3/RL. As before, the power dissipated by having this headroom voltage Vx is wasted power. However, the amplifier 100 during period 13 operates differently to the amplifier 10 of Figure 1, in having supply rails at +1-Voutmin, while the supply voltages of amplifier 10 are fixed at +/-V1. Therefore it can be seen that the power PW3 saved by the amplifier 100, over amplifier 10, is given by the product of the load current lL3 and the voltage Vb, where Vb=Vi-Voutmin.

Therefore, in general, for periods T2 and T3 the: instantaneous power PWi saved by amplifier 100 over amplifier 10 is the product of the instantaneous load current ILl and the voltage difference between Vi and Vout; and over a period of time the average saved power PWa is the product of the average load current ILa and the voltage difference between Vi and Vout.

Therefore, as can be deduced from Figure 3 in conjunction with Figure 2a, by adapting i.e. dynamically changing, the supply voltage +/-Vout of the output stage 40 in response to the gain control signal and therefore effectively the maximum swing of the output signal S4', preferably allowing for a headroom voltage Vx, improves the efficiency of the output stage 40 and amplifier 100 over that associated with the amplifier 10 of Figure 1.

It should be noted that in Figure 3 Vx is illustrated as being constant or substantially constant, however it to may also be possible to further improve the efficiency by allowing Vx to vary with the control signal. For instance a particular output stage may require less headroom when outputting lower output currents, so Vx and hence Vout can be reduced at control input settings related to lower gain settings.

It can therefore be seen that the amplifier 100 of Figure 2a advantageously reduces losses and improves efficiency when the control signal S2' is used to control the variable voltage power supply 80 so as to control the variation of the supply voltage +Vout/-Vout supplied to the power amplifying' output stage 40 in addition to controlling the gain G of the amplifier 100.

Figures 4(a)-4(c) illustrate example relationships between the control signal S2' and the supply voltage to the output stage +/-Vout as the control signal S2' is varied and used for controlling the variable voltage power supply 80 in two different modes.

Figure 4(a) is an example illustration of the control signal S2' as it is linearly varied from its minimum value to its maximum value, and then sometime later, back down to its minimum value.

Figure 4(b) illustrates the output voltage +/-Vout variation of the variable voltage power supply 80 for the case where this power supply is designed to only output a plurality of discrete output voltages. This may give a simpler and hence cheaper structure for the variable voltage power supply 80. For example, if the variable voltage power supply 80 is a capacitor charge pump with a plurality of sets of flying capacitors whose arrangement is programmable to give a discrete set of output voltages, then in this case the efficiency of the capacitor charge pump will be maximum at certain discrete output voltages, so it may be undesirable from an overall system efficiency point of view to generate intermediate voltages. In this situation, to control the output voltage as a function of the control signal S2' a set of threshold levels is defined as indicated by the references Trl-Tr3 in Figure 4(a). Since Vout must always guarantee the headroom Vx above the anticipated maximum output signal swing, yet there are only a few possible levels for Vout, Vout will generally be somewhat larger than the minimum value possible. The dashed line in Figure 4(b) that tracks the voltages represents the same waveforms as presented in Figure 4(c) and illustrates the "waste" of voltage, i.e. the inefficiency. So while this discrete voltage level' mode is more efficient than that associated with the amplifier 10, it is not as efficient as the mode associated with Figure 4(c).

Figure 4(c) illustrates an example variation of the output voltage +/-Vout of the variable voltage power supply 80 as a function of the control signal S2' when the control signal S2' controls the variable voltage power supply 80 such that a variation in the control signal S2' causes a substantially continuous and corresponding variation in the output voltage +/-Vout: that is to say the variation in the output voltage i-/-Vout follows a variation in the control signal S2' . Vout is controlled so that it tracks the maximum anticipated output swing, with extra headroom Vx.

Many modern amplifiers may have the gain digitally controlled, in which case there will still be discrete levels of the control signal, but many of them (say 256 for an 8-bit control word), so the resultant Supply voltage waveform ÷/-Vout will substantially be similar to that of Figure 4c. In such an embodiment, the loss of efficiency, due to the finite resolution in supply voltage +/-Vout, will be small and the supply voltage ÷/-Vout may be regarded as being varied in a substantially continuous manner.

Also illustrated, for comparison, in Figures 4a-4c is a dash-dot line that represents the fixed voltage level +/-V1 associated with the arrangement of Figure 1.

Variable Voltage Power Supply Design The variable voltage power supply 80 will now be described. As mentioned previously this power supply is a charge pump of a novel type referred to as a "Level Shifting Charge Pump" (LSCP) or a variation on this referred to as a "Dual Mode Charge Pump". These charge pump circuits address the problems of conventional charge pump circuits, such as Inverting Charge Pumps, namely, that they can only generate output voltages that have a rail-to-rail magnitude greater than the input voltage. This can be disadvantageous in certain applications, as it may not allow the circuitry being supplied to run efficiently, for example when such an Inverting Charge Pump circuit is being used to to power circuitry that amplifies a signal with a maximum amplitude much smaller than the amplifier circuitry's power supply +/-VDD. This means that such an inverting charge pump, should it be used as the Variable Voltage Power Supply 80 for the novel amplifier 100, may be inefficient at particularly low volumes where the appropriate output level of the charge pump for the volume set is somewhat less than its lowest possible input level. Furthermore, should the charge pump receive its input from a DC-DC converter, there would be significant losses in this DC-DC converter should it have to input lower voltages to the charge pump much of the time.

Figure 5a is a block diagram of a novel inverting charge pump circuit, which we shall call a "Level Shifting Charge Pump" (LSCP) 400. In this circuit there are two reservoir capacitors CR1 and CR2, a flying capacitor Cf and a switch array 410 controlled by a switch controller 420 (which may be software or hardware implemented) arranged a shown. In comparison to a conventional Inverting Charge Pump it is notable that reservoir capacitor CR1 is not connected directly to the input supply voltage VDD, but only via the switch array 410.

It should be noted that LSCP 400 is configured as an open-loop charge-pump.

Therefore. LSCP 400 relies on the respective loads (not illustrated) connected across each output N12-N11, N13-Ni1 remaining within predetermined constraints. The LSCP 400 outputs two voltages Vout+, Vout-that are referenced to a common voltage supply (node Ni 1).

LSCP 400 operates such that, for an input voltage +VDD, it generates outputs each of a magnitude which is a mathematical fraction of the input voltage VDD. In the embodiment below the outputs generated are of magnitude +VDD/2 and -VDD/2, although when lightly loaded, these levels will, in reality, be +/-VDD/2 -lload.Rload, where Iload equals the load current and Rload equals the load resistance. It should be noted that, in this case, the magnitude (VOD) of output voltage across nodes N12 & N13 is the same, or is substantially the same, as that of the input voltage (VDD) across nodes N10 & Nil Figure 5b shows a more detailed version of the LSCP 400 and, in particular, detail of the switch array 410 is shown. The switch array 410 comprises six main switches Si-S6 each controlled by corresponding control signal CS1-CS6 from the switch control module 420. The switches are arranged such that first switch Si is connected between the positive plate of the flying capacitor Cf and the input voltage source, the second switch S2 between the positive plate of the flying capacitor and first output node N12, the third switch S3 between the positive plate of the flying capacitor and common terminal Nil, the fourth switch S4 between the negative plate of the flying capacitor and first output node N12, the fifth switch S5 between the negative plate of the flying capacitor and common terminal Nil and the sixth switch S6 between the negative plate of the flying capacitor and second output node N13. Optionally, there may be provided a seventh switch S7 (shown dotted), connected between the input voltage source (node Nl0) and first output node N12.

It should be noted that the switches can be implemented in a number of different ways (for example, MOS transistor switches or MOS transmission gate switches) depending upon, for example, an integrated circuit's process technology or the input and output voltage requirements. I0

The LSCP 400 has three basic states of operation as shown below.

Figures 6a and 6b show the switch array 410 operating in a first state, "state 1".

Referring to Figure 6a, switches Si and S4 are closed such that capacitors Cf and CR1 are connected in series with each other and in parallel with the input voltage +VDD. Therefore, capacitors Cf and CR1 share the input voltage +VDD that is applied across them. Figure 5b shows an equivalent circuit for the state 1 operation with voltage +VDD effectively applied across nodes Nl0 & Nil.

It is preferable for applications that require symmetrical, but opposite polarity, output voltages, that the values of capacitors Cf and CR1 are equal such that each capacitor Cf, CR1 changes voltage by an equal increment when connected in series across a voltage source. If both capacitors are initially discharged, or indeed previously charged to any equal voltages, they will end up each with a voltage equal to half the applied voltage source, in this case one half of the input voltage VDD.

Figures 7a and 7b show the switch array 410 operating in a second state, "state 2".

Referring to Figure 7a, switches S3 and S6 are closed such that capacitors Cf and CR2 are connected in parallel with each other and between nodes Ni 1 and Ni 3.

Therefore, the voltage across capacitor Cf equalises with that across capacitor CR2 such that the voltages across capacitors Cf, CR2 equalise. Over a plurality of cycles, the voltages across the capacitors Cf and CR2 will converge to a voltage VDD/2.

Figure 6b shows an equivalent circuit for this state 2 operation.

It should be noted that the value of reservoir capacitor CR2 does not necessarily need to be the same as that of flying capacitor Cf. If capacitor CR2 is much larger than capacitor Cf, it will require more state sequences to charge up to or close to VDD/2.

The value of reservoir capacitor CR2 should be chosen depending upon expected load conditions and required operating frequency and output ripple tolerance.

As in the prior art Inverting Charge Pump, the presence of a significant load on the charge pump's respective output terminals will result in a respective voltage droop in Vout+, Vout-away from +/-VDD. If the load is symmetric, and there is equal current magnitude on both Vout+ and Vout-, then the symmetry of the system will result in both outputs drooping by the same amount.

However, if for example there is a significant load on Vout+ but no load or a light load on Vout-, then the voltage across capacitor CR1 will reduce. This will result in a larger voltage across capacitor Cf at the end of state 1 which will then be applied to capacitor CR2 in state 2. The flying capacitor Cf will then be connected in series with capacitor CR1 in state 3 but still having a larger voltage across it, even initially. Therefore, voltages Vout+ and Vout-will both tend to droop negatively, that is to say that the common mode is not controlled.

To avoid this effect, a third state, state 3, is introduced. Figures 8a and 8b show the switch array 410 operating in this state 3 operation. Referring to Figure Ba, in state 3, switches S2 and S5 are closed such that capacitors Cf and CR1 are connected in parallel with each other and between nodes Nil and N12. Therefore, both capacitors Cf and CR1 become charged up to an equal voltage, despite any difference between of their previous voltages. In steady state this becomes approximately VDD/2. Figure 7b shows an equivalent circuit for this state 3 operation.

The circuit, therefore ends state 3 with equalised voltages, after which it returns to state 1. Consequently the circuit will, at least, start state 1 with Vout÷ = ÷VDD/2, depending upon load conditions and switching sequence.

In states 2 and 3, the voltages across the various capacitors that are connected in parallel may not actually, in practice, completely equalise in a single sequence, particularly if the switching frequency is high, relative to the LSCP's R-C time constant.

Rather, in each sequence of states a contribution of charge will be passed from capacitor to capacitor. This contribution will bring each output voltage to the desired level under zero, or low, load conditions. Under higher load conditions, the output reservoir capacitors CR1, CR2 will typically achieve a lower voltage (with some ripple).

The size of each of the capacitors needs simply to be designed such that the reduction of common mode drift is within acceptable bands, for all expected load conditions and/or larger switches, with less on-resistance, could be employed.

It should be appreciated that the open-loop sequencing of the above three states does not necessarily need to be observed. For example the state sequences could be: 1, 2, 3,1,2,3.. (as described above); or 1,3,2,1,3,2...; or 1,2,1,3,1,2,1,3. It should also be apparent that it is not necessary that the third state be used as often as the other two states, for instance a sequence of 1, 2, 1, 2, 1, 2, 3, 1 can be envisaged.

It may even be envisaged to dispense with the third state altogether, albeit only in the case of well-balanced loads, or with alternative schemes for common-mode stabilisat ion.

Other switching and sequencing scenarios exist. For example, in one alternative operational Mode 1 embodiment: State 1 could be replaced by a fourth state, "state 4" whereby switches Si and S5 are closed (all other switches are open). In this state capacitor Cf charges up to input voltage +VDD. A fifth state, "state 5" would then operate with switches S2 and S6 closed (all other switches open) such that flying capacitor Cf is connected across reservoir capacitors CR1 and CR2 (which, in this scenario, may be equal in capacitance). It should be noted that this particular example of an alternative switching and sequencing scenario has the drawback that there is no common-mode control and therefore such a switching and sequencing scenario would suffer from common-mode drift. However, this common-mode drift can be "reset" by altering the switching sequence at appropriate intervals during the "normal" switching and sequencing cycle. These alterations can be predetermined, or initiated in response to observed conditions.

Figure 9 illustrates the non-overlapping control signals (CS1 -CS6) for controlling the switches (Si -S6) during the three states (1, 2 and 3) of the main operational embodiment. As discussed above, this represents only one example out of many possibilities for the controlling sequence.

It should be noted that the sizes of capacitors CI, CR1, CR2, can be selected to meet the required ripple tolerances (versus size/cost) and consequently the clock phase duration for each state need not necessarily be of ratio 1:1:1.

While the above describes an embodiment wherein the LSCP generates outputs of ÷1-VDDI2, it will be understood by the skilled person that the above teaching could be used to obtain outputs of any fraction of VDD by increasing the number of flying capacitors Cf and altering the switch network accordingly. The relationship between output and input in this case is Vout+/-= +/-VDD/(n+1) where n equals the number of flying capacitors Cf. It will also be appreciated that circuits with more than one flying capacitor as described will still be capable of generating outputs of +/-VDD/2 as well as outputs for every intermediate integer denominator between +/-VDD/2 and +1-VDD!(n÷1) depending on its control. For example, a circuit with two flying capacitors can generate outputs of VDD/3 and VDD/2, one with three flying capacitors can generate outputs of VDD/4, VDD/3 and VDD/2 and so on.

The circit of Figure 5a is also capable of dual mode operation, depending on is controlling circuitry/programming. When configured to be operable in two modes the circuit will be referred to as the Dual-Mode Charge Pump (DMCP). In this embodiment, there is provided a mode select circuit 430 within the control module 420. This a mode select circuit 430, depending on an input control signal Ic, selects one of two switch controller circuits/programs 420a, Figure 10 shows an alternative embodiment referred to as the Dual-Mode Charge Pump (DMCP) which is operable in two main modes. The charge-pump, in this example configured as an open-loop charge-pump, differs in that there is provided a mode select circuit 430 within the control module 420. This a mode select circuit 430, depending on an input control signal IC, selects one of two switch controller circuits/programs 420a, 420b to use, in order to control the switches in one of the two main modes. Alternatively, the mode select circuit 1430 and the controllers 1420a, 1420b can be implemented in a single circuit block (not illustrated). Another optional difference between the LSCP and DMCP is that the switch array 1100 now comprises seven switches Si to S7. Switches Si to S6 are arranged as before, while optional switch S7 is connected between the input voltage source and first output node N12.

The DMCP's two main modes are a first mode (Mode 1) where it produces a dual rail output of voltages +/-VDD/2, and a second mode (Mode 2) where it produces a dual rail output of +1-VDD (+VDD again being the input source voltage level at node Nb).

As before, the circuit can also produce outputs of any voltages up to these levels it arranged to operate in a closed loop configuration.

Furthermore, in Mode 2, the circuit is operable in two sub-Modes, referred to as Modes 2a and 2b. Optional switch S7 is only used in Mode 2b. Consequently, if switch S7 is not included Mode 2 is only operable in sub-Mode 2a.

In Mode 2a the DMCP has two basic states of operation. Figure 11 a shows the circuit operating in the first of these states, "state 6". In this state, switches Si, S2 and S5 are closed (53, S4 and S6 are open). This results in capacitors Cf and CR1 being connected in parallel across the input voltage +VDD, between nodes N10 & Ni 1.

Therefore, capacitors Cf and CR1 each store the input voltage +VDD. Figure ii b shows an equivalent circuit for the state 6 operation.

Figure i2a shows the Circuit operating iii the second of these states, "state 2". This is the same state as state 2 in Mode 1 whereby switches S3 and S6 are closed, S2, S4 and S5 are open). Therefore capacitors Cf and CR2 are connected in parallel between common node Nil and second output node N13. Therefore, capacitors Cf and CR2 share their charge and Node 13 exhibits a voltage of -VDD after a number of state sequences. Figure 12b shows an equivalent circuit for this state 2 of operation.

Figure 13a shows an additional state, "state 7", which can be introduced into this Mode 2a operation where switches Si and S5 are closed (S2, S3, S4 and S6 are open). This state 7 Connects the flying capacitor Cf across the input voltage +VDD.

This state can be followed by states 6 then 2 arid then back to 7 etc. Figure 13b shows an equivalent circuit for this state 7of operation.

Mode 2a allows for a number of different sequence implementations depending on, for example, load conditions. The state sequences may be: 6, 2, 6, 2, 6.. or 6, 2, 7, 6, 2, 7.. etc. It is equally envisaged that one of the states be used less frequently than the others (as was described above in relation to Mode 1), for instance if the load on the two output nodes Ni2, Ni3 are unbalanced, states 6 or 2 could be included less frequently than the others, as capacitor CR1 may need to be charged less frequently than capacitor CR2 or vice versa.

As mentioned above, Mode 2b is an alternative sub-mode of operation which is possible when the DMCP is provided with switch S7. This switch may used to replace the combined functionality of switches Si and S2 for generating the positive output voltage at node N12 in applications where the high-side load, i.e. the load connected between nodes N12 and Ni 1, does not require a lot of current, such as where the load has a high input resistance as with a Line Output" for a mixer for example. In such a case the size, the drive requirements etc, of switch S7 can be reduced and modified compared to those of switches Si and S2. It should be noted that switch S7 could be permanently switched on which has the advantages in that there is less power required to drive the switches and switch S7 would not, in the case of a MOS switch implementation, inject any charge into either nodes 10 or 12 due to the parasitic gate-drain and gate-source capacitances. It should also be noted that switch Si is still required to operate so as to generate the negative output voltage -VDD. Still further, it should be noted that switch S2 may be operated on an infrequent basis so as to aiso connect the flying capacitor Cf and high-side reservoir capacitor CR1 in parallel.

In a main operational embodiment, in Mode 2b, switch S7 is permanently (or near permanently) closed. State 6 is again used to charge the flying capacitor Cf and capacitor CR1 in parallel, this now being achieved by having switches Si, S5 and S7 closed only. A modified state 2 is then used to transfer this charge to capacitor CR2 as before, but this time with capacitor CR1 still having voltage VDD across it due to S7 being closed. Again, a number of different sequence implementations are possible and some of these states may be used less frequently than others depending on load.

Figure 14 illustrates the non-overlapping control signals (CS1 -CS3 & CS5 -CS7) for controlling the switches (Si -S3 and S5 -S7) during the three states of Mode 2a.

Again, this represents only one example out of many possibilities for the controlling sequence.

SI S2 S3 S4 S5 S6 S7 Statel 1 0 0 1 0 0 0 State2 0 0 1 0 0 1 1 State3 0 1 0 0 1 0 0 State4 1 0 0 0 1 0 0 State5 0 1 0 0 0 1 0 --if present State 6 1 1 0 0 1 0 o Mode 2a --Mode2b State6 1 0 0 0 1 0 1 State 7 1 0 0 0 1 Table 1 Table 1 illustrates the switch (Si -S7) states for the seven states described above, with a "0' representing an open switch and a "1" representing a closed switch. States 1, 2, 3 are used in the main operational embodiment of Mode 1, while the states 4 and 5 are used in an alternative operational embodiment of Mode 1. States 2, 6+ and 7 are used Mode 2a of the DMCP and states 2 and 6+÷ (in each case with switch S7 closed) are used in Mode 2b of the DMCP. It follows that the switch network and controller do not need to implement all states 1 to 7, if only a subset of the described modes will be used in a particular implementation.

Figure 15 illustrates a similar LSCP/DMCP 900 circuit as illustrated in Figure 4 or Figure xx except that the DMCP 900 also includes two comparators 910a, 910b for regulating the two output voltages.

It should be noted that DMCP 900 represents a closed-loop DMCP. Each of the comparators 910a, 910b compares their respective charge pump output voltages (Vout+, Vout-) with a respective threshold voltage (Vmin+, Vmin-) and outputs a respective charge signal CHCR1 and CHCR2. These charge signals CHCR1, CHCR2 are fed into the switch control module 1420 to control the switch array 1410 causing the DMCP to operate charging either the relevant reservoir capacitor. If either output voltage droops past its respective threshold, the charge pump is enabled; otherwise the charge pump is temporarily stopped. This reduces the power consumed in switching the switches, especially in conditions of light load.

This scheme allows output voltages up to +/-VDD/2. It should be further noted that in this configuration, the DMCP 900 may be used to generate higher voltages, but with a drop in efficiency. In this case, the reference voltages (Vmin+Nmin-) can be adjusted to adjust the output voltages accordingly. The flying capacitor Cf is charged up to +VDD (via switches Si and S5) and then connected in parallel across either reservoir capacitor CR1 (via switches S2, S5) or CR2 (via switches S3, S6) to raise their voltages to the levels set by the reference voltages. Such an operation increases the ripple voltages on the reservoir capacitors CR1, CR2 but it also reduces switching losses. However, by scaling the reservoir capacitors CR1, CR2 relative to the charging tO capacitor Cf, the ripple voltages can be reduced. It is possible, therefore, for the gain control signal S2' of Figure 2 to control the reference voltages (Vmin+Nmin-) and therefore control the output voltages Vout+ and Vout-of the variable voltage power suplply 80.

Figure 16a is a block diagram of a second main embodiment of the Level Shifting Charge Pump 1400. As with the previous embodiment there are two reservoir capacitors CR1 and CR2, a switch array 1410 controlled by a switch controller 1420 (which may be software or hardware implemented) However, there are now two flying capacitors Cf 1 and Cf2. LSCP 1400 again operates to produce outputs of +/-VDD/2 in a first mode and +/-VDD in a second mode. While this embodiment uses an extra flying capacitor, it has the advantage over the LSCP/DMCP 400 with a single flying capacitor in that the output voltages Vout+/-now have improved cross-regulation characteristics.

Figure 16b shows a more detailed version of the circuit 1400 and, in particular, detail of the switch array 1410 is shown. The switch array 1410 comprises eight switches Si-SB each controlled by corresponding control signal CS1-CS8 from the switch control module 1420. The switches are arranged such that first switch Si is connected between the positive plate of the first flying capacitor Cf 1 and the input voltage source, the second switch S2 between the positive plate of the first flying capacitor Cf 1 and first output node N12, the third switch S3 between the positive plate of the flying capacitor and the positive plate of the second flying capacitor Cf2, the fourth switch S4 between the negative plate of the first flying capacitor Cf 1 and common terminal Ni 1, the tifth switch S5 between the negative plate of the first flying capacitor Cf 1 and the positive plate of the second flying capacitor Cf2, the sixth switch S6 between the negative plate of the first flying capacitor Cf 1 and the negative plate of the second flying capacitor Cf2, the seventh switch between the negative plate of the second flying capacitor Cf2 and common terminal Ni 1 and an eighth switch between the negative plate of the second flying capacitor Cf2 and second output terminal N13. It should be noted that the switches can be implemented in a number of different ways (for example, MOS transistor switches or MOS transmission gate switches) depending upon, for example, an integrated circuit's process technology or the input and output voltage requirements.

The LSCP 1400, in one operational embodiment, has three basic states of operation as shown below.

Figures 17a and 17b show the switch array 1410 operating in a first state, "state 1".

Referring to Figure 15a, switches Si, S5 and S7 are closed such that capacitors Cf 1 and Cf2 are connected in series with each other and in parallel with the input voltage +VDD (N10 & Ni 1). Therefore, capacitors Cf 1 and Cf2 share the input voltage ÷VDD that is applied across them. Figure i7b shows an equivalent circuit for this state 1 operation with voltage ÷VDD effectively applied across nodes Ni 0 & Nil.

It is preferable, for applications that require symmetrical, but opposite polarity, output voltages, that the values of capacitors Cf i and Cf2 are of equal such that each capacitor changes voltage by an equal increment when connected in series across a voltage source. If both capacitors are initially discharged, or indeed previously charged to any equal voltages, they will end up each with a voltage equal to half the applied voltage source, in this case one half of the input voltage VDD.

Figures 18a and i8b show the switch array 1410 operating in a second state, "state 2" Referring to Figure i8a, switches S2, S4, S5 and S8 are closed such that capacitors Cf 1 and CR1 and Cf2 and CR2 are respectively connected in parallel with each other.

Therefore, the voltage across capacitor Cf 1 equalises with that across capacitor CR1 such that the voltages across capacitors Cf 1, CR1 equalise. Over a plurality of state sequences, the voltages across capacitors Cf 1, CR1 will converge to a voltage VDD/2.

Similarly, the voltages across capacitors Cf2 and CR2 will also equalise and eventually converge to VDO/2. Figure 1 8b shows equivalent circuits for this state 2 operation.

It should be noted that the value of reservoir capacitors CR1 and CR2 do not necessarily need to be the same as that of flying capacitors Cf 1 and Cf2. If capacitor CR1 and/or CR2 is much larger than capacitor Cf 1 and/or Cf2, they will require more state sequences to charge up to, or close to, VDD/2. The value of reservoir capacitors CR1, CR2 should be chosen depending upon expected load conditions and required operating frequency and output ripple tolerance.

As with the charge pumps 400, 900 described above, the presence of a significant load on the charge pump output terminals will result in a voltage droop in Vout+, Vout-away from ÷/-VDD/2. If the load is symmetric, that is there is equal current magnitude on both Vout+ and Vout-, then the symmetry of the system will result in both outputs drooping by the same amount.

However, if for example there is a significant load on Vout+ but no load or a light load on Vout-, then the voltage across capacitor CR1 will reduce, while that across CR2 will remain the same, or substantially the same. This wiii resuit in a reduction in the voltage across Cf 1 during state 2. As a result of this there will be a larger voltage across capacitor Cf2 at the end of state 1, which will then be applied to CR2 in state 2, while at the same time, capacitor Cf 1 will again be connected in series with capacitor CR1, but still having a smaller voltage across it, even initially. Therefore, the output voltages Vout+ and Vout-will both tend to droop negatively, that is to say, the common mode is not controlled.

To avoid this effect, a third state of operation is introduced.

Figures 19a and 19b show the switch array 1410 operating in this third state, "state 3".

Referring to Figure 1 9a, switches S3 and S6 are closed such that the two flying capacitors Cf 1 and Cf2 are connected in parallel with each other. Both capacitors Cf 1 and Cf2 become charged up to an equal voltage, despite any difference between of their previous voltages. In steady state this becomes approximately VDD/2. Figure 1 9b shows an equivalent circuit for the state 3 operation.

As mentioned in the previous embodiment, in states 2 and 3, the voltages across the various capacitors that are connected in parallel may not actually completely equalise in practice, particularly if the switching frequency is high relative to the LSCP's A-C time constant. Therefore, the same considerations as in the previous embodiment must be taken into account when considering capacitor sizes so that any reduction in the output voltage remains within acceptable bounds.

It should be appreciated that the open-loop sequencing of the above three states does not necessarily need to be observed. For example the state sequences could be: 1 2, 3,1,2,3... (as described above); or 1,3,2,1,3,2...; or 1,2,1,3, 1,2,1,3. ltshould also be apparent that it is not necessary that state 3 be used as often as the other two states, 1 and 2, for instance a sequence of 1, 2, 1, 2, 1, 2, 3, 1 can be envisaged.

It may even be envisaged to dispense with state 3 altogether albeit only in the case of well-balanced loads, or with alternative schemes for common-mode stabilisation.

Other switching and sequencing scenarios exist. For example, in one alternative operational embodiment: State 1 could be replaced by another state, "state 4" whereby switches Si and S4 are closed (all other switches are open) or a fifth state, state 5" where Si, S3 and S7 are closed. In these states either capacitor Cf 1 or Cf2 charges up to input voltage ÷VDD. A sixth stale, "sLate 6", with S2 and S8 ciosed (all other switches open) or a seventh state, "state 7", with switches, or S2, S3 or SB closed would then operate such that the charged flying capacitor Cf 1 or Cf2 is connected across reservoir capacitors CR1 and CR2 (which, in this scenario, may be equal in capacitance). It should be noted that this particular example of an alternative switching and sequencing scenario has the drawback that there is no common mode control and therefore such a switching and sequencing scenario would suffer from common mode drift. However, this common mode drift can be "reset" by altering the switching sequence at appropriate intervals during the "normal" switching and sequencing cycle. These alterations can be predetermined, or initiated in response to observed conditions.

Figure 20 illustrates the non-overlapping control signals (CS1 CS8) for controlling the switches (Si -S8) during the three states (1,2 and 3) of the main operational Mode 1 embodiment of this second main embodiment of the DMCP. As discussed above, this represents only one example out of many possibilities for the controlling sequence.

The circuit of Figure 5a/Figure 10 is again also capable of dual mode operation, depending on its controlling circuitry/programming. When configured to be operable in two modes the circuit will be referred to as the Dual-Mode Charge Pump (DMCP) 1400. In this embodiment, there is provided a mode select circuit 1430 within the control module 1420. This a mode select circuit 1430, depending on an input control signal Ic, selects one of two switch controller circuits/programs 1420a, 1420b to use, in order to control the switches in one of the two main modes. This mode select circuit can be seen on Figures ita and lib. Alternatively, the mode select circuit 1430 and the controllers 1420a, 1420b can be implemented in a single circuit block (not illustrated).

As with the DMCP of the first main embodiment, the DMCP's two main modes are a first mode where it produces a dual rail output of voltages +/-VDD/2, and a second mode where it produces a dual rail output of +1-VDD (VDD again being the input JO source voltage level at node Nb). As before, the circuit can also produce outputs of any voltages up to these levels if arranged to operate in a closed loop configuration.

In Mode 1 operation the circuit operates in exactly the same way as described in the embodiments of Figures 16 to 20, in order to produce the dual rail output at voltages ÷/-VDD/2, and will not be described further. In Mode 2 operation the switch array 1410 is operated in a different sequence such that the DMCP 1400 operates as an inverting charge pump. Also, switches S2 and S4 are permanently closed (which has the effect of permanently connecting flying capacitor Cf 1 in parallel with reservoir capacitor CR1) and switch S6 is permanently open.

Figure 21a shows the first of these states "state 8", in which, switches Si, S3 and S7 are closed, as well as the permanently closed S2 and S4. This results in capacitors Cf 1, Cf2 and CR1 being connected in parallel across the input voltage +VDD, between nodes N10 & Ni 1 (Cf 1 and CR1 are permanently connected in parallel in this mode).

Therefore, the three capacitors Gil, Cf2, CR1 are allowed to charge up to +VDD.

Figure 21b shows an equivalent circuit for this state 8 operation.

Figure 22a shows a circuit diagram for the second of these states, "state 2", which is also the second state of Mode 1 operation. It can be seen that switches S2, S4, S5 and S8 are closed. Figure 22b shows an equivalent Circuit for this state 2 operation.

This state 2 is described in detail above. However in this case each flying capacitor Cf 1, Cf2 is charged up to +VDD after state 8, and therefore when the voltages across capacitors CR1 and CR2 equalise with their respective flying capacitor Cf 1, Cf2, outputs Vout and Vout will sit at VDD and VDD-respectively.

Figure 23 illustrates the non-overlapping control signals (CS1 -CSB) for controlling the switches (Si -S8) during Mode 2 of this second main embodiment of the DMCP 1400. Again, this represents only one example out of many possibilities for the controlling sequence.

Si S2 S3 S4 S5 S6 S7 S8 Statel 1 0 0 0 1 0 i 0 State2 0 1 0 1 i 0 0 1 State3 0 0 1 0 0 1 0 0 State4 1 0 0 1 0 0 0 0 State5 1 0 1 0 0 0 1 0 State6 0 1 0 0 0 0 0 1

Table 2

Table 2 illustrates the switch (Si -SB) states for the eight states that this second main embodiment of the DMCP 1400 can operate in, with a "0" representing an open switch and a "1" representing a closed switch. States 1, 2 and 3 are used in the main operational embodiment of this DMCP 1410 in Mode 1, while the states 4, 5, 6 and 7 are used in an alternative operational embodiment of same basic mode. States 2 and 8 are used Mode 2 of this DMCP 1410. It follows that the switch network and controller do riot need to implement all states 1 to 8, if only a subset of the described modes will be used in a particular implementation.

Figure 24 illustrates a closed loop equivalent 1900 of this second main embodiment of the DMCP 1400 circuit, similar to DMCP 900. Again it is largely similar to the open loop DMCP 1400 but further includes two comparators 191 Oa, 191 Ob for regulating the two output voltages.

Each of the comparators 1910a, 1910b compares their respective charge pump output voltages (Vout+, Vout-) with a threshold voltage (Vmin+, Vmin-) and each respective comparator 191 Oa, 191Db outputs a respective charge signal CHCR1, CHCR2. These charge signals CHCR1, CHCR2 are fed into the switch control module 1420 to control the switch array 1410 causing the DMCP to operate charging either the relevant reservoir capacitor. If either output voltage droops past its respective threshold, the charge pump is enabled; otherwise the charge pump is temporarily stopped. This reduces the power consumed in switching the switches, especially in conditions of light load. It is apparent that, as both reservoir capacitors CR1, CR2 are charged in a single state (state 2), that there need only be a single charge signal CHCR which causes the DMCP to charge both reservoir capacitors CR1, CR2.

It should be further noted that in this Figure 24 configuration, the charge pump 1400 may be used to generate any required voltages, but with a drop in efficiency. In this case, the reference voltages (Vmin+Nmin-) can be adjusted to adjust the output voltages accordingly. The flying capacitors Cf 1, Cf2 are charged up to +VDD and then each is connected in parallel across one of the reservoir capacitors CR1 or CR2 to raise their voltages to the levels set by the reference voltages. Such an operation increases the ripple voltages on the reservoir capacitors CR1, CR2 but it also reduces switching losses. However, by scaling the reservoir capacitors CR1, CR2 relative to the flying capacitors Cf 1, Cf2, the ripple voltages can be reduced.

Figure 25 illustrates a variable voltage power supply 80 utilising any of the novel Dual Mode Charge Pumps 400, 900 1400, 1900 described above, wherein one of a number of different input voltage values may be selected as an input voltage to the DMCP 400, 900 1400, 1900. It shows an input selector 1000 having a number of different voltage inputs (÷Vin 1 to +Vin N), the actual input chosen being determined by control input Ic. The chosen voltage level then serves as the input voltage VDD for the Dual Mode charge pump 400, 900, 1400, 1900.

Figure 26 shows a more detailed variation of figure 25 and which may be used as the variable voltage power supply 40 of the novel amplifier 100. This shows a buck converter fed by an input voltage +V1 from, for example, a battery. The buck converter also receives a control signal Cb. The output of the buck converter is fed through a line regulator (in this case a low drop out regulator), before being input into any of the LSCP/DMCPs described above.

In use, the Buck Converter 1010 receives an input voltage +Va (5v for example) and outputs a lower voltage +Vb (3.2 for example). It is preferable to pass the output voltage +Vb of the Buck Converter 1010 through a Linear Regulator such as a Low Drop Out (LDO) 1020 regulator before inputting the voltage from the Buck Converter 1010 into the LSCP/DMCP. The LDO 1020 receives the output voltage Vb from the Buck Converter 1010 and outputs a slightly lower voltage +Vin (3v for example) which constitutes the input voltage of the LSCP/DMCP 400, 900, 1400, 1900.

It is preferable to use the LDO 1020 since both the Buck Converter 1010 and the LSCF'/DMCP 400, 900, 1400, 1900 are switching regulators and it is preferable to clean up the switching effects relating to the output voltage +Vout of the Buck Converter 1010 before it is fed into the LSCP/DMCP 400, 900, 1400, 1900.

The output voltage ÷Vout of the Buck Converter 1010 can be adjusted via an external control signal Cb, possibly by changing its duty cycle. In this way, the input to, and therefore the outputs from, the LSCP/DMCP 400, 900, 1400, 1900 is/are controllable.

When used as the Variable Voltage Power Supply for any of the novel amplifiers disclosed herein, it is envisaged that control signal Cb is, or is derived from, gain control signal S2. Additionally, the output voltages of the LSCPIDMCP 400, 900, 1400, 1900 can be adjusted (independently) via an external control signal Cp.

An additional feature is a bypass switch 1030 that may be employed in a situation where there is a need to connect the input voltage +V1 directly to the input of the LSCP/DMCP 400, 900, 1400, 1900. This feature is useful where +V1 is supplied from a battery that slowly discharges and gets to a voltage level that the Buck Converter 1010 cannot or cannot efficiently generate +Vout and hence ÷VIN.

Varaiations on the Basic Amplifier Design Figure 27a illustrates a variant embodiment of the circuit of Figure 2a. This embodiment works in essentially in the same manner as the embodiment described in relation to Figure 2a above. The main difference in this Figure 27a embodiment is that its output stage 45 combines the functions of the gain controller 20 and output stage of Figure 2a. Therefore, the Figure 27a output stage 45 receives the gain control signal S2' which, as will be described and illustrated below, may act on a feedback loop within the output stage 45.

Figures 6b-6e illustrate a number of different methods in which the amplifier 100 of Figure 27a can be controlled by the control signal S2'. Figures 6b-6e illustrate non-exhaustive examples and many other arrangements will be apparent to the skilled reader. Each of these Figures 6b-6e shows detailed elements comprising, or included in, the output stage 45 Figure 27a.

Figure 27b illustrates the output stage 45 comprising an amplifier 600 and variable resistors Ri and R2 arranged as illustrated. The control signal S2' acts to change the resistance of one or both resistors. The gain G of the amplifier 600 is varied by varying the resistance ratio of resistors Ri and R2. Consequently, only one of these resistors need be variable and controlled by the control signal S2'. If both the resistors are varied, then one resistor may be controlled by the control signal S2' and the other may be controlled by a derivative signal S22, produced for example by a signal inverter 610, so that when RI increases, R2 decreases, and vice versa. It should be noted that in this embodiment, resistors Ri and R2 represent a gain controller that is arranged to control the gain G of the amplifier 600 applied along the signal path, the signal path extending from the input terminal of the amplifier 600 to its output terminal, wherein the gain G is controlled in response to the control signal S2'. Control signal S2' may be a digital control word, in which case S22 may be say the lower bits of the control word, while Ri may be controlled by the higher bits of the control word.

Figure 27c illustrates a variation of the output stage 45 illustrated in Figure 27b. Figure 27c illustrates an embodiment having respective resistor and switch arrangements, as illustrated, that represent the resistors Ri and R2. In this particular embodiment, the respective control signals DS2', and its derivative DS22, are digital versions of the respective control signals S2' and S22 illustrated in Figure 27b. Also, control signal may be a multibit control signal as indicated by the line MB. Figure 27d illustrates a similar arrangement to that illustrated in Fig 6c.

Figure 27e illustrates another variation of the output stage 45 illustrated in Figure 27b.

Figure 27e illustrates a ganged potentiometer R2, R3. In this particular embodiment, the resistance of the ganged potentiometers R2 and R3 are dependent on the control signal S2. The control signal S2' controls these ganged potentiometers such that R2 is adjusted so as to vary the gain G of the amplifier 600 while R3 is adjusted so as to vary the output voltage Vout of the variable voltage supply 80. If S2' controls R2 to give a hgher resistance, the output signal voltage swing will increase. To allow for this, the wiper on R3 is moved to give a higher input reference voltage into variable power supply 80.

Figure 28a illustrates a variation on Figure 2a wherein the gain control is controlled digitally.

Figure 28a illustrates an amplifier 101 that comprises a digital signal processor (DSP) 500, such as a multiplier for example, and a digital to analogue converter (DAC) 520, such as a resistor/switch network, inserted in place of the gain controller 20 illustrated in Figure 2a. The DSP 500 and DAC 520 form an input stage 530. The DSP 500 receives a digital input signal DS1 from a data source (not illustrated), such as a solid-state memory or information carrier, such as a CD or DVD for example, and a digital gain control signal DS2'. The gain Control signal 0S2' acts upon the DSP 500 and as a result DSP 500 varies its digital input signal DS1 such that it outputs a gain controlled digital output signal DS1'. The DAC 520 receives the gain controlled digital signal DS1' and outputs a corresponding gain controlled analogue signal AS1 which is processed in the same manner as described above in connection with Figure 2a.

In this Figure 28a, the DAC is driven by a single supply 60 while the output is driven from the dual, i.e. split, variable voltage power supply 80', with a level shifter 30 required to translate signal AS1 at quiescent voltage +V1/2 to a ground-referenced signal AS1', but no level shifter is required between the ground-referenced output S4' and the grounded load 70.

In a further variation, the digital control signal DS2' may act directly on the structure of the DAC 520 rather than actually modulate a voltage, by, for example, selecting the size of a capacitor periodically connected to a fixed DAC full-scale reference, to scale a charge used to represent DAC full-scale signal, or by selecting the size of a resistance connected to a fixed DAC full-scale reference to scale a current used to represent a DAC full-scale signal, rather than by directly modulating a (decoupled) reference voltage.

It should be noted that the variable voltage power supply 80' in this particular embodiment should be designed to be controlled by a digital control signal DS2' as opposed to an analogue control signal. The design of such a digitally controlled variable voltage power 80' supply will be readily appreciated and facilitated by those skilled in the art.

Figure 28b illustrates a variation of the digital control and manipulation as performed by the DSP 500 and DAC 520 in Figure 28a.

Figure 28b illustrates the first DAC 520 as directly receiving the digital input signal DS1 from a data source (not illustrated) and outputhng the gain controlled analogue signal AS1'. A second DAC 525 replaces the DSP 500 and receives the digital control signal DS2'. The DACs 520 and 525 form an alternative input stage 530'. This second DAC 525 outputs an analogue gain control signal AS2' that is used to control the first DAC 520. For example AS2' may be used as the full-scale reference voltage for the DAC, so the output for a given digital input word (DS1) will scale directly with the reference Voltage Le. the gain Control signal AS2. it should be noted that either the digital gain control signal DS2' or its derived analogue equivalent AS2' may be used to control an appropriately arranged variable voltage power supply.

Figure 28c illustrates an embodiment wherein the gain control of amplifier 101 may act at multiple points in its signal path between signal input and output. An input digital signal DS1 is multiplied in DSP 500, the resultant scaled digital signal DS1' is input to either input stage 530 or its alternative 530 which scales the signal DS1' (perhaps as described above) to give an analogue signal AS1 which is then scaled by a gain controller 20 to give a signal AS2 which is then level shifted by a level shifter 30 to give a signal AS2', which is then further scaled within a variable gain output amplifier 45. Each of the elements 500, 530/30', 20, 45 receives from a controller block 700 a respective gain control signal, as illustrated, according to an overall input gain control signal DS2' which is also used to derive the appropriate power supply control signal to feed into variable power supply 80'. it would also be possible for the gain control signal DS2' to be a multibit control signal (as illustrated) comprising individual words to control each gain block, and for controller 700 to calculate the appropriate power supply control signal, according to a calculated cascaded gain. The controller 700 may be implemented by means of a look-up table, such an implementation be readily understood by those skilled in the art.

Figures 6 and 7 illustrate that the actual gain control may act at any point or multiple points, in the amplifier's (100, 101) signal path between signal input and output, whether it be in the digital or analogue domain, and preceding or combined with the ouput stage 40.

Figure 29a illustrates a variation on the embodiment of Figure 2a for, in the case of audio applications, stereo systems. It will be appreciated that the principles of variation in the embodiment of this Figure 29a are equally applicable to single ground referenced voltage systems such as illustrated in Figure 5.

Dual input signals Sil, S12 are fed into a gain unit 220 that comprise a gain controller 20 (not illustrated) and possibly a level shifter 30 (not illustrated) for each of the input signals Si 1 and Si 2 driven from a fixed supply 60 (not illustrated). The gain unit 220 outputs respective gain controlled signals S31', S32'. The two gain controllers 20 (not illustrated) are controlled by a common gain or volume or level control signal S2'. The respective gain controlled signals S31', S32' are fed into respective output stages 401, 402, which output respective output signals S41', S42' which are then fed into left and right speakers (not illustrated) or a stereo headphone (not illustrated). The power unit contains the power supplies 60 and 80 as illustrated in Figure 2a.

The headphones referred to above may be either physically connected, by means of electrical wires, to the amplifier 102 or they may not, in which case the headphones may, for example, receive the signals Sil' and S12' via, for example, infrared or RF signals.. In either of these headphone arrangement examples it will be appreciated by those skilled in the art that the amplifier 102 may in whole or in part be included as part of the headphones.

Figure 29b illustrates a variation of part of the amplifier 102 illustrated in Figure 29a.

Figure 29b iHustrates an amplifier 102' that receives two input control signals S21' and S22' that respectively control gain controllers (not illustrated) within the gain unit 220.

The two input control signals S21' and S22' are also fed into a controller unit 230 that detects the maximum value of the two control signals S21' and S22' such that the variable voltage power supply 80, and therefore the supply voltages ÷/-Vout, is varied in response to the greater of the two volume control signals S21' and S22'. The two control signals may represent separate volume control signals in an application where either a balance control or separate volume controls for each input signal is required.

An alternative arrangement (not illustrated) to that of Figure 29b is where the control signals S21' and S22' each control a variable voltage power supply that supplies power to the respective output stage to which the control signal relates.

A further alternative arrangement (not illustrated) to that of Figure 29b is where the gain unit 220 or respective elements thereof are fully or partially incorporated into the output stage unit 405 or respective elements thereof.

Figure 30 illustrated the amplifier 100' of Figure 5 with different transducers, i.e. loads, that represent non-exhaustive illustrations of basic applications for the novel amplifier.

It will be appreciated that illustrated example embodiments of this Figure 30, and Figure 31, are equally applicable to dual ground referenced voltage systems such as illustrated in Figure 2a.

In a first of two illustrated examples of Figure 30, the amplifier 100' may be employed in an audio system, such as: a portable music system (MP3) (including such devices combined with mobile telephone handsets or similar devices); Hi-Fi; In-Car Entertainment system; or a DVD player for example, whereby the system receives a volume, or level, control signal S2' that is altered by a user either via a potentiometer, i.e. a volume knob, or by a remote control device for example. In this particular example of an application, the output signal S5 of the amplifier 100' is used to drive a speaker SP. It will be appreciated to those skilled in the art that in modern audio systems it is quite usual to have a plurality of output signals such as, for example, in stereo systems or Dolby (RTM) pro logic 5.1 channel surround sound systems.

In a second illustrated example, the amplifier 100' may be employed in a transmitter system such as a mobile phone r.f. transmitter, whereby it receives a transmit power control signal S2'. In this particular example of an application, the output signal S5 of the amplifier 100' is used to drive a transmitter TR, such as an aerial for example.

Figure 31 illustrates a data transmitter/receiver system, such as a modem for example, wherein an amplifier 102 acts as a line driver for the data transmission/receiver system. A power supply 200, gain controller 20, line driver 401, system controller 700, signal modulator 710, signal demodulator 720, a transmit/receive controller 730 and transmission line 740 are arranged as shown.

Again the amplifier 102 works in the same way as the previous examples with the variable voltage power supply supplying the line driver 401 with a dynamic voltage +1-Vout. The control signal S2' from the system controller 700 controls the gain controller and the voltage level of the dynamic voltage +/-Vout. The modulator 710, which is also controlled by the system controller 700, provides the input signal Si to the amplifier. The transmit/receive controller 730 allows for two-way signal transmission between the output of the amplifier 102 and the transmission line 740. Controller 730 may be a two-to-four wire hybrid to allow full duplex, or a switching element to allow transmission in one direction at a time. The transmit/receive controller 730 also allows a received signal to be fed back to the data transmitter/receiver system via the demodulator 720.

Such a novel amplifier as herein described may be implemented using discrete components or may be implemented on an integrated circuit or a combination of both.

It should be noted that the above described embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims and drawings.

The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or an" does not exclude a plurality, and a single element may fulfil the functions of several elements recited in the claims. It should also be noted that the attenuation, or decrease, of a signal amplitude is a form of amplification, thus the word "amplify", amplifying", "amplified" and the like can be taken to mean an increase or a decrease in the amplitude of a signal. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

Claims A signal amplifying circuit comprising: a main input for receiving an input signal; a main output for outputting an output signal; a signal path extending from the input to the output; a gain controller arranged to control the gain applied along said signal path in response to a control signal; an output stage coupled to the gain controller within said signal path for generating said output signal, a variable voltage power supply comprising a charge pump circuit for providing, in use, a positive output voltage and a negative output voltage for supplying the output stage, the charge pump circuit comprising: -an input terminal and a common terminal for connection to an input voltage supply, -first and second output terminals for connection to first and second reservoir capacitors, said first and second output terminals outputting said positive and negative output voltages; -one or more pairs of flying capacitor terminals, each pair comprising first and second flying capacitor terminals for connection to one or more flying capacitors, the number of flying capacitors equalling n, -a network of switches for interconnecting said terminals, and -a controller for operating said switches in a sequence of states, wherein said variable voltage power supply, comprising said charge pump circuit, is operable to generate said positive and negative output voltages each of a magnitude up to substantially a fraction of said input voltage; wherein said fraction of said input voltage equals 1/(n+1).
2 An amplifying circuit as claimed in claim 1 wherein n=1 and said fraction of said input voltage is substantially a half.
3. An amplifying circuit as claimed in claim 1 wherein n>1 and said fraction of said input voltage is substantially 1/(n+1).
4. An amplifying circuit as claimed in claim 3 wherein said circuit is able to generate output voltages of magnitudes at different fractions of said input voltage.
5. An amplifying circuit as claimed in claim 4 wherein said different fractions of said input voltage include the inverse of some or all of each integer between 2 and (n+1)
6. An amplifying circuit as claimed in any preceding claim wherein said variable voltage power supply is operable in at least a first mode to generate first positive and negative voltages and a second mode to generate second positive and negative voltages, wherein said first positive and negative voltages each have a magnitude up to substantially a fraction equal to 1/(n+1) of said input voltage.7 An amplifying circuit as claimed in claim 6 wherein the second of said modes generates said second positive and negative output voltages each up to substantially said input voltage.8. A method of amplifying an input signal to generate a gain controlled output signal, said method comprising: generating a positive output voltage and a negative output voltage from a single input supply received across a supply input terminal and a common terminal, the positive and negative output voltages being output at first and second output terminals connected to said common terminal via respective first and second reservoir capacitors, the method comprising taking n flying capacitors connected to flying capacitor terminals, said flying capacitor terminals being connected between different ones of said terminals in sequence of states to generate first positive and negative output voltages, wherein said first positive and negative output voltages are each substantially equal in magnitude to a fraction of the voltage of said input supply, wherein said fraction is equal to 1/(n+1); the method further comprising: applying said positive and negative output voltages to an output stage of an amplifier circuit; receiving an input signal; receiving an control signal; and applying a gain to said input signal in response to said control signal to produce said gain controlled output signal at an amplifier output terminal of said output stage of said amplifier circuit wherein said gain is independent said positive and negative output voltages of said output stage.9 A method as claimed in claim 8 wherein n=1 and said fraction of said input voltage is substantially a half.A method as claimed in claim 8 wherein n>1.11 A method as claimed in claim 10 wherein said circuit is able to generate output voltages of magnitudes at different fractions of said input voltage.12. A method as claimed in claim 11 wherein said different fractions of said input voltage include the inverse of some or all of each integer between 2 and (n+1)