GB2470776A - Analogue Thin-Oxide MOSFET - Google Patents

Analogue Thin-Oxide MOSFET Download PDF

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Publication number
GB2470776A
GB2470776A GB0909686A GB0909686A GB2470776A GB 2470776 A GB2470776 A GB 2470776A GB 0909686 A GB0909686 A GB 0909686A GB 0909686 A GB0909686 A GB 0909686A GB 2470776 A GB2470776 A GB 2470776A
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United Kingdom
Prior art keywords
oxide
transistor
mask
gate oxide
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0909686A
Other versions
GB0909686D0 (en
Inventor
Rainer Herberholz
David Vigar
Sean Minehane
Mark Redford
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Technologies International Ltd
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Cambridge Silicon Radio Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cambridge Silicon Radio Ltd filed Critical Cambridge Silicon Radio Ltd
Priority to GB0909686A priority Critical patent/GB2470776A/en
Priority to TW098121178A priority patent/TW201044559A/en
Publication of GB0909686D0 publication Critical patent/GB0909686D0/en
Priority to US12/783,215 priority patent/US20100308415A1/en
Publication of GB2470776A publication Critical patent/GB2470776A/en
Priority to US13/045,754 priority patent/US20110156157A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A dual gate oxide CMOS integrated circuit is disclosed, comprising a thin gate oxide (core) transistor 10 with a first gate thickness 14 and first drain implant type; a thick gate oxide (IO) transistor 11 with a second gate thickness and second drain implant type 15; whereby the first gate oxide thickness 14 is smaller than the second gate oxide thickness and the second drain type 15 is of a lightly doped drain (LDD) type; and a analogue thin gate oxide (AVT) transistor 12 with the first gate oxide thickness 14 and the second drain implant type 15. Methods for producing such a device are disclosed, comprising the use of a mask set which provides "open" and "closed" sections which allow or block implantation at specific sites.

Description

Analogue thin-oxide MOSFET BackQ round This invention relates to analogue thin-oxide MOSFETs, and in particular to analogue thin-oxide MOSFETs formed using dual-oxide CMOS technology.
Development of CMOS technologies has focussed on short channel devices to provide MOSFETs with high switching speed and high integration density. Although this development has led to improved performance in digital devices, the MOSFETs are not optimised for analogue performance, which can suffer due to the optimisation for digital operation.
CMOS technologies generally provide two types of MOSFET, a thin-oxide (core) MOSFET 1 0 and a thick-oxide (10) MOSFET. The core devices are optimised as above, while the 10 devices are designed to provide a robust interface to external components at voltages higher than can be tolerated in the core devices.
The output resistance (variation of the output current as a function of the drain voltage) is an indicator of the analogue performance of MOSFETs. There are two main contributors to the 1 5 output resistance; Channel Length Modulation (CLM) and Drain-induced Barrier Lowering (DIBL). For short-channel devices, CLM is the dominant factor in output resistance. CLM causes the width of the depletion region to increase with increasing drain voltage, which decreases the effective channel length. In long channel devices CLM becomes insignificant in comparison to DIBL. However, pocket implants used to suppress CLM in short channel devices degrade the output resistance of long channel devices by increasing DIBL.
To provide good device matching, constant current sources and low noise in analogue systems, channel lengths several times longer than the minimum provided by core devices are generally required.
Process options for multiple threshold voltages in core devices are generally provided, but each option requires additional masking steps to adjust the channel doping. Furthermore, beyond the 65nm process node, pocket implants are generally used to define transistor type, rather than well and channel implants. Different device types therefore have very similar long-channel threshold voltages and so low-threshold short-channel devices are not useful to increase the available voltage headroom in long-channel devices for analogue circuits.
The 10 transistors of a process provide increased headroom if they are used as an analogue device at a higher operating voltage than the core, and they generally have lighter or no pocket implants. However, RF circuits may require transistors with a combination of analogue performance and the higher switching speed of the core devices.
Blocking LDD implants can be utilised to improve the output resistance at high drain voltages, but the poor link-up between the inversion channel and drain area degrades resistance in linear operation and increases the drain saturation voltage, thereby limiting the usefulness of such a route to an analogue transistor.
Additional types of transistor can be provided by the use of additional processing steps.
However, such an approach is expensive and development often lags behind leading-edge CMOS technologies.
There is therefore a need for a means to provide an improved performance analogue transistor, which addresses some or all of the shortcomings of prior techniques.
Summary
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
1 5 Where references are made to mask properties, the term open or opening is used to indicate that during wafer processing, the mask causes the creation of a related feature (i.e. oxide or implant) at that location. This term is used for convenience and is not intended to indicate that the physical mask has an actual opening, but is rather indicative of the function of the area of the mask.
A mask set for the manufacture of a dual gate oxide CMOS integrated circuit, comprising a first mask for the definition of LDD implants in a thick gate oxide transistor, a second mask for the definition of gate oxides, wherein the first mask is open for the definition of LDD implants at a first site and the second mask is closed for the definition of a thin gate oxide at that first site, for the formation of a transistor in the integrated circuit at that first site.
The mask set may further comprise a third mask for the definition of LDD implants in a thin gate oxide transistor.
The second mask may be closed for the definition of a thin gate oxide at a second site and the third mask is open for the definition of LDD implants at that second site, for the formation of a conventional thin-oxide transistor at that site, and the first mask may be open for the definition of LDD implants at a third site and the second mask is open for the definition of a thick gate oxide at that third site, for the formation of a conventional thick-oxide transistor at that site. For the avoidance of doubt, the first and third masks are not opened at the same site.
There is also provided a method for the manufacture of a dual-oxide CMOS integrated circuit, comprising the steps of forming a thin-oxide transistor using a first implant type and a first oxide configuration, forming a thick-oxide transistor using a second implant type and a second oxide configuration, and forming a third type of transistor using the first oxide configuration and the second implant type.
There is also provided a method for the manufacture of a dual gate oxide CMOS integrated circuit utilising the mask set described above, comprising the steps of implanting LDD implants at the first site using the first mask, and defining a thin oxide layer using the second mask at the first site.
1 0 There is also provided a dual gate oxide CMOS integrated circuit, comprising at least one thin-oxide transistor comprising a gate oxide having a first configuration and a first implant type, at least one thick-oxide transistor comprising a gate oxide having a second configuration and a second implant type, and at least one further transistor comprising a gate oxide of the first configuration and implants of the second type.
1 5 The first gate oxide configuration may be a thin-oxide gate principally for high speed performance or lower supply voltage and the second type of gate oxide may be a thick oxide gate principally for 10 devices or higher supply voltage.
There is also provided a method of designing a dual oxide CMOS integrated circuit using a CMOS technology, the CMOS technology comprising a thin gate oxide transistor utilising a first gate oxide configuration and a first implant type, and a thick gate oxide transistor utilising a second gate oxide configuration and a second implant type, the method comprising the step of defining at least one transistor using the first gate oxide configuration and the second implant type.
The preferred features may be combined as appropriate, as would be apparent to a skilled person, and may be combined with any of the aspects of the invention.
Brief Description of the DrawinQs
Embodiments of the invention will be described, by way of example, with reference to the following drawings, in which: Figure 1 shows a schematic diagram of three types of transistor provided by a modified CMOS technology; Figure 2 shows a schematic diagram of a mask set according to a modified CMOS technology; Figure 3 shows a graph of threshold voltage against channel length; Figure 4 shows IDsat and IDlin graphs for varying threshold voltages; Figure 5 shows gds graphs for varying channel lengths; Figure 6 shows gds graphs for varying drain voltages; Figure 7 shows a graph of intrinsic gain against overdrive voltage; and Figure 8 shows a graph exhibiting the matching of devices.
Detailed Description
Embodiments of the present invention are described below by way of example only. These examples represent the best ways of putting the invention into practice that are currently 1 0 known to the Applicant although they are not the only ways in which this could be achieved.
The description sets forth the functions of the example and the sequence of steps for constructing and operating the example. However, the same or equivalent functions and sequences may be accomplished by different examples.
It will be understood that the phrase CMOS technology is used herein to refer to a defined 1 5 set of processes and options for the design and manufacture of CMOS devices. The phrase is not intended to be restrictive and should be read to also include BiCMOS and other process variants to which the following disclosure also applies.
The use of the word implant or implant condition is used in this disclosure to refer to any method by which dopants are introduced into CMOS devices, for example, but not limited to, ion implantation. The methods and techniques described herein are independent of the methods used to introduce dopants.
Where references are made to mask properties, the term open or opening is used to indicate that during wafer processing, the mask causes the creation of a related feature (i.e. oxide or implant) at that location. This term is used for convenience and is not intended to indicate that the physical mask has an actual opening, but is rather indicative of the function of the area of the mask.
It has now been shown that a transistor having an improved performance can be fabricated by combining certain features from thin and thick oxide transistors in a dual oxide CMOS technology. Figure 1 shows a cross section of conventional thin-oxide (core) 10 and thick-oxide (10) MOSFET devices 11, together with an analogue thin-oxide transistor (AVT) 12 according to the current disclosure. The AVT is formed in the core p-well 13, and utilises the thin gate-oxide 14 of the core devices, but uses the LDD implants 15 of the 10 device.
This disclosure therefore relates to an extension of a conventional CMOS technology. The conventional CMOS technology provides two types of transistor, whereas the modified CMOS technology provides three types of transistor. Where the term conventional CMOS technology is used herein it is used to describe a technology providing base devices from which features may be combined according to the current disclosure. This description has been given in the context of a technology providing two transistor types for different supply voltages, but the conventional CMOS technology to which this disclosure is applied may 1 0 provide more than two transistor types. Similarly, the disclosure applies to all modifications and variants of the basic CMOS processes.
The provision of the AVT transistor 12 by the modified CMOS technology does not require any additional processing or development beyond the core 10 and 10 11 devices provided by the conventional CMOS technology. The AVT transistor can therefore be provided without 1 5 additional cost or manufacturing cycle time.
The AVT transistor may be provided by an extension of the Process Design Kit (PDK) in relation to the CMOS technology. The provision of new rules, design options and models allow the use of the new AVT transistor within designs using the modified CMOS technology.
As explained previously, the provision of the new transistor type does not require additional processing steps and so the wafer manufacturing process remains conventional, although new mask layouts are created by the new rules which lead to the definition of new, previously unavailable, combinations of devices in the ICs formed according to the modified CMOS technology.
Figure 2 shows a schematic diagram of a mask set for defining thin-oxide core, AVT and thick-oxide 10 transistors according to the modified CMOS technology. Openings in the mask show devices for which that process step is applied to for a particular device. As explained above, the word opening is not used to indicate a physical opening, but rather that that process step is applied to the indicated device. The active area, well & channel implants, gate-electrode and N or P+ masks are not shown as those steps are independent of the
subject of this disclosure.
For the core device 20 the NLDD_CORE implant mask 21 (LDD/pocket for thin gate oxide devices) is open but the NLDD_IO implant mask 22 (LDD/pocket mask for thick gate oxide devices) is closed. In contrast the NLDD_IO implant mask 22 is open for the 10 device 23, but the NLDD implant mask 21 is closed. The thick oxide mask 24 is open only for the thick-oxide 10 device 23. For the avoidance of doubt, for devices where the thick oxide mask is closed, a thin oxide is assumed to be present.
For the conventional devices, the NLDD_CORE mask 21 can therefore be written logically as [N+ AND ACTIVE-AREA NOT THICK-OXIDE], and the NLDD_IO mask 22 can be written logically as [N+ AND ACTIVE-AREA AND THICK-OXIDE].
The AVT device 25 utilises a new combination of features for the NLDD_IO mask 22, and introduces the combination [N+ AND ACTIVE-AREA AND AVT_LDD], where AVT_LDD is a marker layer marking AVT devices.
The AVT device of the current disclosure is thus obtained by new features of the PDK utilised 1 0 in the design of integrated circuits and in the mask manufacture process. The modified CMOS technology provides new combinations of mask openings to provide the AVT device without adding process steps. An AVT device is thus characterised by utilising a combination of features from the core and 10 devices provided by the conventional CMOS technology.
ICs utilising the modified CMOS technology incorporating the AVT device may be 1 5 characterised by presence of devices sharing features with more than one other type of device in the chip, in particular sharing an oxide layer with one type of device, and implants with another type of device. More particularly, the AVT device shares an oxide layer with a thin-oxide core transistor and implants with a thick-oxide 10 transistor. In a further embodiment a transistor may share an oxide layer with a thick-oxide 10 transistor and implants with a thin-oxide core transistor. Such a transistor may be defined using the techniques described above with modifications to the definition of the masks and processes to apply the relevant oxide and implants.
Data is presented below demonstrating the expected performance of AVT devices. Unless otherwise stated Figures 2 -7 below relate to a foundry 4Onm low-power CMOS technology using 1.1V thin-oxide devices and 2.5 thick-oxide devices Figure 3 shows a graph comparing the VTlin of thin-oxide core devices (LVT -Low Threshold Voltage, SVT -Standard Threshold Voltage, HVT -High Threshold Voltage), thick-oxide 10 devices and an AVT MOSFET according to the current disclosure, for varying drawn lengths.
At channel lengths significantly larger than the minimum length, the LVT, SVT and HVT devices all have very similar threshold voltages due to the use of pocket implants to generate the variants as opposed to channel implants. The pocket implants also lead to the reverse-short channel effect seen in the graph.
The AVT device provides a lower threshold voltage and retains the VT roll-off of the 10 device. The better gate control provided by the use of a thin-oxide gives a smaller difference in VT between L=lOp.m and O.23tm compared to the 10 device.
Figure 4 shows plots of IDsat and lD1 for the core, 10 and AVT devices as described previously in relation to Figure 2. The IDsat values for the AVT follow the general trend of the core devices while showing lower lD1 compared to an extrapolation of the core devices. This is caused by the higher resistance of the LDD implants from the 10 device used in the AVT.
Figure 5 shows plots of gds against drawn length for the SVT and AVT devices described previously. The SVT device has lower gds at short lengths due to better control of length 1 0 modulation, but the AVT has lower gds for longer devices due to reduced DIBL.
Figure 6 shows a graph of gds against VD for AVT and SVT devices. The data for the 65nm process node shows the degradation of a conventional thin-oxide core device at 4Onm compared to the 65nm device, highlighting the need for the AVT device provided by the modified CMOS technology.
1 5 Figure 7 shows intrinsic gain against gate overdrive voltage for SVT and AVT devices. The improvement of the intrinsic gain follows from the improved output conductance discussed above, while the differences in transconductance (gm) are minor. The improvement over SVT devices is most pronounced at small gate overdrive voltages, which is beneficial in analogue circuits.
Figure 8 shows a Pelgrom plot for the AVT device, showing improved device mismatch for the AVT compared to both SVT thin-oxide core devices and thick-oxide 10 devices.
The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.
Any range or device value given herein may be extended or altered without losing the effect sought, as will be apparent to the skilled person.
It will be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages.
Any reference to an item refers to one or more of those items. The term comprising is used herein to mean including the method blocks or elements identified, but that such blocks or elements do not comprise an exclusive list and a method or apparatus may contain additional blocks or elements.
The steps of the methods described herein may be carried out in any suitable order, or 1 0 simultaneously where appropriate.
It will be understood that the above description of a preferred embodiment is given by way of example only and that various modifications may be made by those skilled in the art.
Although various embodiments have been described above with a certain degree of particularity, or with reference to one or more individual embodiments, those skilled in the art 1 5 could make numerous alterations to the disclosed embodiments without departing from the spirit or scope of this invention.

Claims (8)

  1. Claims 1. A dual gate oxide CMOS integrated circuit, comprising at least one thin-oxide transistor comprising a gate oxide having a first configuration and a first implant type, at least one thick-oxide transistor comprising a gate oxide having a second configuration and a second implant type, and at least one further transistor comprising a gate oxide of the first configuration and implants of the second type.
  2. 2. A dual gate oxide CMOS integrated circuit according to claim 1, wherein the first gate 1 0 oxide configuration is a thin-oxide gate principally for high speed performance or lower supply voltage and the second type of gate oxide is a thick oxide gate principally for 10 devices or higher supply voltage.
  3. 3. A mask set for the manufacture of a dual gate oxide CMOS integrated circuit, comprising 1 5 a first mask for the definition of LDD implants in a thick gate oxide transistor, a second mask for the definition of gate oxides, wherein the first mask is open for the definition of LDD implants at a first site and the second mask is closed for the definition of a thin gate oxide at that first site, for the formation of a transistor in the integrated circuit at that first site.
  4. 4. A mask set according to claim 3, further comprising a third mask for the definition of LDD implants in a thin gate oxide transistor.
  5. 5. A mask set according to claim 4, wherein the second mask is closed for the definition of a thin gate oxide at a second site and the third mask is open for the definition of LDD implants at that second site, for the formation of a conventional thin-oxide transistor at that site, and the first mask is open for the definition of LDD implants at a third site and the second mask is open for the definition of a thick gate oxide at that third site, for the formation of a conventional thick-oxide transistor at that site.
  6. 6. A method for the manufacture of a dual-oxide CMOS integrated circuit, comprising the steps of forming a thin-oxide transistor using a first implant type and a first oxide configuration, forming a thick-oxide transistor using a second implant type and a second oxide configuration, and forming a third type of transistor using the first oxide configuration and the second implant type.
  7. 7. A method for the manufacture of a dual gate oxide CMOS integrated circuit utilising the mask set of claim 3, comprising the steps of 1 0 implanting LDD implants at the first site using the first mask, and defining a thin oxide layer using the second mask at the first site.
  8. 8. A method of designing a dual oxide CMOS integrated circuit using a CMOS technology, the CMOS technology comprising a thin gate oxide transistor utilising a first gate oxide configuration and a first implant type, and a thick gate oxide transistor utilising a second 1 5 gate oxide configuration and a second implant type, the method comprising the step of defining at least one transistor using the first gate oxide configuration and the second implant type.
GB0909686A 2009-06-05 2009-06-05 Analogue Thin-Oxide MOSFET Withdrawn GB2470776A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB0909686A GB2470776A (en) 2009-06-05 2009-06-05 Analogue Thin-Oxide MOSFET
TW098121178A TW201044559A (en) 2009-06-05 2009-06-24 Analogue thin-oxide MOSFET
US12/783,215 US20100308415A1 (en) 2009-06-05 2010-05-19 Analogue thin-oxide mosfet
US13/045,754 US20110156157A1 (en) 2009-06-05 2011-03-11 One-time programmable charge-trapping non-volatile memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0909686A GB2470776A (en) 2009-06-05 2009-06-05 Analogue Thin-Oxide MOSFET

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GB0909686D0 GB0909686D0 (en) 2009-07-22
GB2470776A true GB2470776A (en) 2010-12-08

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020153559A1 (en) * 2001-04-23 2002-10-24 Choh-Fei Yeap Integrated circuit structure and method therefore
US6482703B1 (en) * 2001-09-28 2002-11-19 Taiwan Semiconductor Manufacturing Company Method for fabricating an electrostatic discharge device in a dual gate oxide process
US20050194648A1 (en) * 2004-03-03 2005-09-08 Myoung-Soo Kim Semiconductor device including a transistor having low threshold voltage and high breakdown voltage
US20060099753A1 (en) * 2004-11-11 2006-05-11 Jung-Ching Chen Method of forming devices having three different operation voltages
US20080283922A1 (en) * 2007-05-17 2008-11-20 Kyoji Yamashita Semiconductor device and manufacturing method thereof
US20090142896A1 (en) * 2007-12-04 2009-06-04 Kun-Hyuk Lee Method for manufacturing semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020153559A1 (en) * 2001-04-23 2002-10-24 Choh-Fei Yeap Integrated circuit structure and method therefore
US6482703B1 (en) * 2001-09-28 2002-11-19 Taiwan Semiconductor Manufacturing Company Method for fabricating an electrostatic discharge device in a dual gate oxide process
US20050194648A1 (en) * 2004-03-03 2005-09-08 Myoung-Soo Kim Semiconductor device including a transistor having low threshold voltage and high breakdown voltage
US20060099753A1 (en) * 2004-11-11 2006-05-11 Jung-Ching Chen Method of forming devices having three different operation voltages
US20080283922A1 (en) * 2007-05-17 2008-11-20 Kyoji Yamashita Semiconductor device and manufacturing method thereof
US20090142896A1 (en) * 2007-12-04 2009-06-04 Kun-Hyuk Lee Method for manufacturing semiconductor device

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GB0909686D0 (en) 2009-07-22

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