GB2466222A

GB2466222A - Managing the resources processing data transfers in input/output chips using a FIFO memory to hold the details of resources that have been timed out.

Info

Publication number: GB2466222A
Application number: GB0822763A
Authority: GB
Inventors: Matthias Klein; Gerhard Zilles; Manfred Walz; Thomas Gentner; Andreas Wagner; Andreas Koenig
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2008-12-15
Filing date: 2008-12-15
Publication date: 2010-06-16
Anticipated expiration: 2028-12-15
Also published as: GB2466222B; GB0822763D0

Abstract

Disclosed is a system for managing the resources processing data transfers in a transaction based input/output chip of a computer system. A transaction is associated with a resource, 18 the transaction being a request packet and a corresponding response packet. The system has a transaction table 10 for holding one resource for each request until the resource has been processed and a resource management 12 for storing information about the availability of these resources, which has become available before a predetermined timeout period T has been exceeded. The system has a FIFO (first-in first-out) memory 14 for buffering those resources, which have been made available after the first timeout period and a second timeout period Q have been exceeded. An arbiter circuit 16 for chooses the resources from the resource management, if any are available, if not the timed-out resources from the FIFO memory are used.

Description

DES CR1 PT ION A method and a system for managing resources at processing of a data trauirer in a transaction based input/output chip

Background of the invention

1. Field of the invention

The present invention relates to a method and a system for managing resources at processing of a data transfer in a transaction based input/output chip of a computer system.

2. Description of the related art

A transaction based input/output chip of a computer system requires a resource for each transaction. Thus, the transaction is associated with one resource. The resource consists of storage to hold information that is required to handle a request packet and a corresponding response packet. Each new request requires one resource. After the response has been processed, the resource is available again. The number of the resources determines also the number of the outstanding requests at the same time.

During a normal operation, there exists a response packet for each request packet. However, there may be scenarios in which packets might get lost in the system. In this case there exists no corresponding response packet for the request packet. The transaction based input/output chip comprises resources held for any outstanding request. Thus, it must be ensured that the resource is not permanently lost in the case of a missing response due to a lost packet. Additionally, timing requirements of endpoints or devices in the input/output path below of the input/output chip must be fulfilled. For example, the device may require the input/output chip to deliver a response for any request within five milliseconds.

Both requirements are fulfilled via timeout mechanisms. This means that a timeout response is gPnrated by the input'cutput chip in that case, if a response has not come for an outstanding request within the specified timeout period. This exceeded timeout also leads to the resource f or this transaction being made available for new requests.

This mechanism works very well for lost packets. However, there exist scenarios, in which a response arrives, after the timeout period has passed. This received response is a so-called ghost packet. In the case that the resource freed up after the timeout period has already been used for a new request, when this very late response for a previous request arrives as a ghost packet, it might be misinterpreted as a response for the new request.

A known implementation for avoiding the ghost packet consists mainly of a mechanism using bits of a so-called tag field. The tag field is a field in the request packet, which is returned with the response. This tag field contains f or example a unique resource identifier to match the response packet with the original request packet. In order to avoid misinterpreting ghost packets, some bits might also be used for a sequence or recovery number, which is part of every resource and in particular increments with every timeout experienced for this resource. In the case described above, this would mean that the ghost packet is not misinterpreted as a response for the new request. The ghost response packet would have a lower recovery number than the associated resource, which had incremented its recovery number when the previous request held within this resource had timed out.

This mechanism provides a good protection against a data integrity problem due to ghost packets. However, it requires available bits in the tag field, which depends on the possibilities of the used protocols. The proposed mechanism implements a method to minimize the probability of misinterpretation of ghost packets and a resulting r3ta integrity problem in those cases, where there are not enough bits available in a tag for a sufficiently large sequence or recovery number to use this mechanism.

Object of the invention It is an object of the present invention to provide an improved method and a system for managing resources at processing of a data transfer in a transaction based input/output chip of a computer system.

Summary of the invention

The above object is achieved by a method as laid out in the independent claims. Further advantageous embodiments of the present invention are described in the dependent claims and are

taught in the description below.

According to the core idea of the invention these resources, which are available since their timeout has been exhausted, are buffered in a dedicated FIFO memory (first-in first-out memory).

The FIFO memory contains only those resources, which have been made available by having timed out. Preferably, the maximum number of the resources within the FIFO memory depends on the number of the resources to be managed.

Further, an arbiter circuit is provided in order to choose resources from two different pools. A first pool comprises the resources of the regular mechanism. The resources of the regular mechanism are those resources becoming available after the transaction related to this resource has completed regularly, meaning that the response packet has been received before the timeout period has been exceeded. A second pool comprises the resources from the FIFO memory. The arbiter preferably chooses the resources of the regular mechanism. However; f resourcos of the regular mechanism are not available, then the arbiter accesses to the resources in the FIFO memory.

The inventive method additionally decreases a premature re-usage of the resource by changing the regular resource assignment process. This resource assignment means that, whenever a new request arrives with a need for a resource, then the resource needs to be selected from the pool of the available resources. A resource, which has timed out, is not made available directly for new reajuests, but rather put into the dedicated FIFO memory.

The FIFO memory contains solely unblocked resources. The expression "unblocked resources" describes those resources have been made availab].eby having timed out.

Whenever a new request arrives and needs a resource, this resource is now only picked from the FIFO memory, if there is no other regular resource available. The term "regular resource" means in this case that the resource has been freed up by a normally received and processed response. In the majority of the input/output chips, there are most of the times more resources available than actually needed at the moment. This is a reserve for high traffic corner cases. Thus, in almost any case there are still regular resources available. As a consequence, a timed out resource might not be re-used for an extremely long time.

The probability of a misinterpreted and mistreated late response is therefore almost impossible.

In the case that timeout periods occur on a more regular basis, the FIFO memory might become filled up over time, while the numbers of the available regular resources decreases in parallel. In that scenario, it will finally happen that a formerly timed out resource must be used by being picked from the FIFO memory. Due to the nature of the FIFO memory, this will be that resource being timed out the longest time ago.

Brief description of the drawings

The above as well as additional objectives, features and advantages of the present invention will be apparent in the

following detailed written description.

The novel and inventive features believed characteristics of the invention are set forth in the appended claims. The invention itself, their preferred embodiments and advantages thereof will be best understood by reference to the following detailed description of preferred embodiments in conjunction with the accompanied drawing, wherein: Fig. 1 illustrates a schematic diagram of a transaction based input/output chip according to a preferred embodiment of the present invention.

Detailed description of the invention

Fig. 1 illustrates a schematic diagram of a transaction based input/output chip according to a preferred embodiment of the present invention. The input/output chip comprises a transaction table 10, a resource management 12, a FIFO memory (first-in first-out memory) 14 and an arbiter circuit 16.

The transaction table 10 comprises a plurality of resources 18.

One resource 18 iè held in the transaction table 10 for each request until the resource has been processed. The input/output chip requires one resource 18 for each transaction. The transaction table 10 is provided to match requests and responses.

The resource management 12 comprises the resources 18 of the regular mechanism. The resources 18 of the regular mechanism become available before a predetermn-1 timeout period has Leeri exceeded.

The FIFO memory 14 receives all those resources 18, which are being made available again after a predetermined timeout period has been exceeded. Instead of feeding those resources 18 back as available resources 18 to the standard mechanism, they are fed into the FIFO memory 14. The FIFO memory 14 includes a list of resources 18, which are now basically available and out of use, but which had been freed up by a timeout rather than a normally processed response. The FIFO memory 14 is fed as the second input into the arbiter circuit 16. Only, when there are no regular resources 18 available in the resource management 12 via the standard mechanism, a resource 18 from the FIFO memory 14 will be used.

The transaction includes a request packet and a response packet.

For each new request one resource 18 is available again, after a previous resource 18 has been processed. The number of the resources 18 determines the number of the requests, which may be in the transaction table 10 at the same time.

The arbiter circuit 16 is provided to choose resources from the resource management 12 or the FIFO memory 14. The arbiter circuit 16 preferably chooses the resources 18 of the resource management 12. However, if resources 18 of the regular mechanism are not available in the resource management 12, then the arbiter circuit 16 accesses to the resources 18 in the FIFO memory 14.

The arbiter circuit 16 is hooked up from the regular resource allocation mechanism. Each transaction table 10 contains a resource allocation mechanism in order to allocate available resources 18 in the case that a new request is processed, which needs a resource 18 to store the required information to create a response in a first protocol format A. Instead of using only the Stãiddrd mecflanjsm, the arbiter circuit 16 is now used.

The arbiter circuit 16 arbitrates between said standard mechanism and the resources 18 provided by the FIFO memory 14.

This arbitration is unfair, preferring said standard mechanism.

The FIFO memory 14 is only used in case that the standard mechanism is not able to provide a resource 18. This case occurs, when all available regular resources 18 are already in use.

For example, the function of the input/output chips might consist of translating between the first protocol format A and a second protocol format B. This means that the input/output chip receives a request packet a packet format in the first protocol format A and has to convert it into a request packet in a packet format of the second protocol format B. Later on, the input/output chip will receive a response packet for this request in the packet format of the second protocol format B and has to convert this response back into a response packet in the packet format of the first protocol format A. In the most cases, there is no direct mapping from this response, which is in second protocol format B, to a response matching the first protocol format A, since certain required information for this was lost during the conversion of the initial request packet from the first protocol format A into the second protocol format B. In order to be able to process the response correctly, the input/output chip contains the transaction table 10. The transaction table 10 stores the required information to create a response packet in the first protocol format A, when the initial request is converted into the second protocol format B. Now, when a response packet arrives in the second protocol format B, then the input/output chip uses the information contained in this response packet together with the stored information in the transaction table 10 in order to generate a correct response packet in the first protocol format A. The response packet comprises a pointer to the information within the transaction table 10. This may be realized in the form of a resource identifier in its tag field. This resource identifier points to the hardware resource containing the stored information needed to create a proper response packet in the first protocol format A, unless the input/out chip has a single outstanding operation structure, where the resource identifier can be obviously omitted.

For timeout protection, each of these resources 18 in the transaction table 10 has a timeout counter assigned to it. The timeout counter ensures that the resource 18 is freed up and that a timeout response packet is generated, after the specified timeout period has expired. The specified timeout period can be hardcoded or provided in a register.

According to a preferred embodiment of the present invention the already known timeout mechanism is complemented by a further timeout mechanism. Said further timeout mechanism includes a second timeout period Q besides a first timeout period T. The second timeout period Q also may be either hardcoded or contained in a register. Instead of sending a timeout response packet and making a resource immediately available after the first timeout period T has been exceeded, this procedure is split up into two steps. In a first step a timeout response is still created immediately after the first timeout period T has been exceeded. However, the resource is not made available at that same point in time, but rather when the second timeout period Q has been exceeded.

In tbis case the FIFO memory 14 receives all resources, which are being made available again after the first timeout period T has been exceeded, and as the case may be also the second timeout period Q has been exceeded.

After the second timeout period Q has been exceeded, the resource 18 is not being made available irnn'tediately and directly. Instead, the resources 18 are handled by the FIFO memory 14 and the arbiter circuit 16. The resources 18 are freed up by the second timeout periods Q differently from those resources 18 freed up in the regular way. The expression "regular way" means that the resources 18 have being made available after a response packet has been received and processed properly before the first timeout period T had been exceeded. In this case there won't be a ghost packet of course.

If many packets are lost at the same time, then the mechanism of the FIFO memory 14 provides a more flexible protection than the second timeout period Q for a high resource protection. Since having only a very high resource protection timeout period Q would protect very well against ghost packets, but also mean that the timed out resources 18 would not be available at all.

After the value of the second timeout period Q has been reached for each of them, the timed out resources 18 would be available at all. This can lead to problems like performance degradation or even functional failures in such cases, when only very few resources 18 are lost. Most of the resources 18 have timed out after the first timeout period T has been exceeded, but not yet reached the very high value of the second timeout period Q. The second timeout period Q can be significantly lower, so that there are resources 18 available again in such cases.

-10 -Thus, the preferred embodiment of the present invention implements a second timeout mechanism besides a first timeout mechanism. The second timeout mechanism blocks a resource 18 for second timeout period Q after it has timed out. This allows the first timeout period T for the resource to be relatively low in order to fulfil response time requirements from devices in the input/output path below, while at the same time the dedicated resource protection second timeout period Q can be sufficiently large in order to avoid the premature re-usage of the timed out resource in case of a late response, i.e. in order to avoid a ghost packet.

The inventive system and method comprises the implementation of the two additional components, namely the FIFO memory 14 and the arbiter circuit 16, in order to avoid ghost packets in the input/output chip.

The present invention can also be embedded in a computer program product which comprises all the features enabling the implementation of the methods described herein. Further, when loaded in computer system, said computer program product is able to carry out these methods.

Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.

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LIST OF REFERENCE NUMERALS

transaction table

12 resouie management circuit 14 first-in first-out (FIFO) memory 16 arbiter circuit 18 resource A first protocol format B second protocol format T first timeout period Q second timeout period

Claims

-12 -CLAIMS1. A system for managing resources at processing of a data Lransfer in a transaction based input/output chip of a computer system, wherein a transaction is associated with a resource (18) comprising a request packet and a corresponding response packet, and wherein said system comprises: -at least one transaction table (10) for holding one resource (18) for each request until said resource (18) has been processed, -a resource management (12) for storing those resources (18), which has become available before a predetermined timeout period (T) has been exceeded, -at least one FIFO (first-in first-out) memory (14) for buffering those resources (18), which have been made available by having timed out, and -an arbiter circuit (16) for choosing the resources (18) from the resource management (12), if the resources (18) in said resource management (12) are available, and for choosing the resources (18) from the FIFO memory, if the resources (18) in the resource management (12) are not available.
2. The system according to claim 1, wherein the maximum number of the resources (18) within the FIFO memory (14) depends on the number of the resources (10) to be managed.
3. The system according to claim 1 or 2, wherein a further timeout period (Q) is defined, which is higher than the timeout period (T).
4. The system according to claim 3, wherein those resources (18) are buffered in the FIFO memory (14), which have been made available after all predetermined timeout periods (T, Q) have been exceeded.

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5. The system according to any one of the preceding claims, wherein the system is realized in hardware, software or a cornbinatioij uf hardware and software.
6. A computer program product stored on a computer usable medium, comprising computer readable program means for causing a computer to implement a system according to anyone of the preceding claims 1 to 5.
7. A method for managing resources at processing of a data transfer in a transaction based input/output chip of a computer system, wherein a transaction is associated with a resource (18) comprising a request packet and a corresponding response packet, and wherein said method comprises the steps of: -holding one resource (18) for each request in at least one transaction table (10) until said resource (18) has been processed, -storing those resources (18) in a resource management (12), which resources (18) has become available after a predetermined timeout period (T) has been exceeded, -buffering those resources (18) in at least one FIFO (first-in first-out) memory (14), which resources (18) have been made available by having timed out, and -choosing the resources (18) from the resource management (12) by an arbiter circuit (16), if the resources (18) in said resource management (12) are available, and choosing the resources (18) from the FIFO memory by the arbiter circuit (16), if the resources (18) in the resource management (12) are not available.
8. The method according to claim 7, wherein the maximum number of the resources (18) within the FIFO memory (14) depends on the number of the resources (10) to be managed.

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9. The method according to claim 7 or 8, wherein a further timeout period (Q) is defined, which is higher than the original timeout period (T).
10. The system according to claim 9, wherein those resources (18) are buffered in the FIFO memory (14), which have been made available after all predetermined timeout periods (T, Q) have been exceeded.
11. The method according to any one of the preceding claims, wherein the method is realized in hardware, software or a combination of hardware and software.
12. A computer program product stored on a computer usable medium, comprising computer readable program means for causing a computer to perform a method according to anyone of the preceding claims 7 to 11.