GB2463464A - Providing a count output from two or more rotary encoder switches - Google Patents

Abstract

Apparatus comprises two or more rotary encoder switches 101, 102, 103, each of the two or more rotary encoder switches being commonly connected to first and second signal lines J, L, each switch being operable to provide signals on the first and second signal lines which are dependent on a direction of rotational actuation of the switch by a user. A receiver 100 is connected to the first and second signal lines so as to receive the signals from the two or more rotary encoder switches, the receiver comprising a counter circuit (see figure 2) operable to determine a count in response to changes in the signals, the receiver being arranged to provide the count at an output. The count may be provide to a lighting control circuit 107 (see also figure 5) such that plural lights may be controlled on the basis of the count provided by the receiver. Each rotary switch may include an output transducer 106, for example a light emitting diode (LED).

Description

Providing a Count

Description

This invention relates to providing a count using two or more rotary encoder switches.

It is known in the art to control lighting systems with electronic circuits and manually controllable switches. Such systems are becoming increasingly digital, and lighting control is now more commonly effected through a computer using a mouse or other input device.

The invention was made in this context.

In accordance with a first aspect of the invention there is provided apparatus comprising: two or more rotary encoder switches, each of the two or more rotary encoder switches being commonly connected to first and second signal lines, each switch being operable to provide signals on the first and second signal lines which are dependent on a direction of rotational actuation of the switch by a user; and a receiver connected to the first and second signal lines so as to receive the signals from the two or more rotary encoder switches, the receiver comprising a counter circuit operable to determine a count in response to changes in the signals, the receiver being arranged to provide the count at an output.

Apparatus constructed in accordance with this aspect of the invention can allow a change in the count to be effected through operation of any one of the plural rotary encoder switches. This has a number of useful applications. This is particularly useful in a lighting control application since it can be particularly convenient to allow a lighting setting to be changed from any of plural control locations. The provision of a count output provides considerably greater utility than a simple on-off' output. The apparatus of this invention has the further advantage of simplicity over a corresponding microprocessor and digital switch-based arrangement. The apparatus also can be constructed in such a way as to have lower power consumption than the corresponding microprocessor and digital switch-based arrangement.

The receiver may include a sub-circuit arranged to provide a signal to the counter circuit in response to a detection of a predetermined sequence of changes in the signals on the two or more signal lines. Here, the predetermined sequence of changes may be a first change on a first one of the two or more signal lines followed by a second change on a second one of the two or more signal lines followed by a third change on the first one of the two or more signal lines. This can provide a particularly effective way of allowing the receiver to avoid reacting to a input comprising rotation of a rotary encoder switch part way between successive rest positions.

In any of the above apparatuses, the receiver may comprise means for biasing the signal lines. This may allow the rotary encoder switches to be passive devices, i.e. it may allow the avoidance of a separate power supply for the rotary encoder switches.

Any of the above apparatuses may comprise a lighting control circuit arranged to control plural lights on the basis of the count provided by the receiver. This can be advantageous in that it may allow a user to effect control of a lighting system through simple manipulation of a rotary encoder switch.

In any of the above apparatuses, each of the two or more rotary encoder switches may be provided with an output transducer, the state of which is dependent on the output of the receiver. This can allow the state of output of the receiver to be indicated at the locations of the rotary encoder switches. This feature is particularly useful since it can allow changes in the count resulting from a user input at one rotary encoder switch to be visible at the locations of the other rotary encoder switches. This may reduce the risk of a user operating a rotary encoder switch in such a way as to make a change to an incorrect count output of the receiver.

In any of the above apparatuses, each of the two or more rotary encoder switches may be connected to the first and second signal lines in parallel. This may allow the use of standard, off-the-shelf rotary encoder switches. Put another way, this may allow the use of conventional rotary encoder switches.

Alternatively, each of the two or more rotary encoder switches is connected to the first and second signal lines in series.

A second aspect of the invention provides a method comprising: connecting two or more rotary encoder switches commonly to first and second signal lines, each switch being operable to provide signals on the first and second signal lines which are dependent on a direction of rotational actuation of the switch by a user; and receiving the signals from the two or more rotary encoder switches at a receiver connected to the first and second signal lines; using a counter circuit of the receiver to determine a count in response to changes in the signals; and providing the count at an output.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 shows a first embodiment of a lighting control system in accordance with the present invention; Figure 2 shows a receiver circuit forming part of the Figure 1 lighting control system; Figure 3 is a timing diagram used to illustrate operation of the Figure 2 circuit; Figure 4 shows a second embodiment of a lighting control system in accordance with the present invention; and Figure 5 shows a lighting control circuit forming part of the Figures 1 and 4 systems.

Figure 1 shows a lighting control system in accordance with the present invention.

In Figure 1, there are three encoder switches 101, 102, 103. However, this number of encoder switches is purely illustrative. There may instead be only one encoder switch, or there may be two or more than three encoder switches. Each of the encoder switches 101, 102, 103 is coupled in parallel to each of the eight cores of an eight core cable 104. The eight cores are labelled, from top to bottom, J, Ground, L, VCC, PE, QO, QI and Q2. Each core of the eight core cable 104 also is connected to a receiver circuit 100, which is explained in detail below.

Each of the rotary encoder switches 101, 102, 103 includes a user manipulable part 105. Through the user manipulable parts 105, users can operate the rotary encoder switches 101, 102, 103 as required. Operation occurs by rotating the user manipulable parts 105. The rotary encoder switches preferable are of the type in which the user manipulable part 105 can be rotated infinitely, i.e. there is no end stop.

Each of the rotary encoder switches 101, 102, 103 includes an output transducer 106. In this example, the output transducer 106 is a series of six light transducers, for instance light emitting diodes (LEDs).

Each of the rotary encoder switches 101, 102, 103 also includes a reset switch 108.

In this example, the reset switch 108 is a simple biased push-to-make switch, which may be incorporated into the rotary encoder switches 101, 102, 103 such as to be operable through manipulation of the user manipulable parts 105. For instance, the reset switch 108 may be operated by pushing (rather than rotating) the user-manipulable part 105 the a rotary encoder switch. Operation of the reset switch 108 by a user results in supply voltage being provided to the PE core (normally biased at ground potential) of the eight core cable 104.

Operation of the system is described briefly as follows. Rotation by a user of the user manipulable part 105 of any of the rotary encoder switches 101, 102, 103 is detected by the receiver circuit 100. An output of the receiver circuit 100 is a count, in this case of a number between 1 and 6, inclusive. The count is encoded in binary form on the cores QO, Qi and Q2. The count is communicated to the rotary encoder switches, 101, 102 and 103 by way of the eight core cable 104. The output transducer 106 of each of the rotary encoder switches 101, 102, 103 indicates the count provided by the receiver circuit 100.

The system is arranged such that manipulation of any one of the rotary encoder switches 101, 102, 103 results in a change in the count provided by the receiver circuit 100. Moreover, the output transducer 106 of each of the rotary encoder switches 101, 102, 103 indicates the count currently provided by the receiver circuit 100, even if the change in the count was effected by manipulation of one of the other rotary encoder switches.

Each of the rotary encoders switches 101, 102, 103 includes a number of detents.

Each of the rotary encoder switches 101, 102, 103 can rest only at a position corresponding to one of the detents, at which both the J and L lines are biased at supply voltage. The rotary encoder switches 101, 102, 103 are of the type wherein rotation from a detent of its user manipulable part 105 in a clockwise direction results in the switch causing a grounding of the line J followed by a grounding of the line L followed by an increase in Voltage on line J to supply Voltage followed by an increase in Voltage on line L to supply Voltage. This is achieved by the use of first and second normally open switches, which are referenced at 111 and 112 in the first rotary encoder switch 101 in Figure 1. Each of the rotary encoder switches 101, 102, 103 is arranged also such that rotation of the user-manipulable part 105 in the opposite direction, i.e. anti-clockwise, results in the Voltage on line L falling to ground prior to the Voltage on line J falling to ground, then the Voltage on line L rising to supply Voltage prior to the Voltage on line J rising again to supply Voltage.

It is this characteristic that allows the receiver circuit 100 to detect the direction in which the user-manipulable part 105 has been rotated, as is described in detail below.

The receiver circuit 100 is shown in detail in Figure 2.

Figure 2 shows clearly the eight separate inputs and outputs of the receiver circuit 100. VCC (supply Voltage) and ground potential are the uppermost and lowermost rails respectively in the Figure. QO, Qi and Q2 are shown at the bottom right of the figure. Inputs J and L are shown towards the top left of the figure. Preset enable (FE) in is shown towards the bottom left of the figure.

Resistor R3 is connected between supply Voltage and the anode of a diode Dl. The cathode of the diode Dl is connected to input J. The connection of DI and R3 ensures that J is biased towards VCC. Similarly, Resistor R4 is connected between supply Voltage and the anode of a diode D2. The cathode of the diode D2 is connected to input L. The presence of R4 and D2 ensures that L is biased towards VCC. J and L are connected to the cathodes of diodes D3 and D4 respectively.

The anodes of the diodes D3 and D4 are connected to ground. D3 and D4 protect the circuit to some extent from negative voltages which may appear on J or L. First and second PNP transistors TR1 and TR2 are biased at 14 Volts by first and second potential dividers, formed by resistors R6 and R8 and by resistors R7 and R9 respectively. The collectors of the first and second transistors TR1 and TR2 are connected to ground potential by resistors Ru and RIO respectively. The first and second transistors thus are connected in a common base configuration.

The emitter of transistor TR1 is connected to the node connecting resistor R3 and diode Dl by a resistor RI. Similarly, the emitter of transistor TR2 is connected to the node connecting resistor R4 and diode D2 by a resistor R5. In this way, the emitters of the first and second transistors TR1 and TR2 are connected to inputs J and L respectively. The emitters of the first and second transistors TR1 and TR2 also are connected to ground potential by way of capacitors CI and C2 respectively.

A clock enable latch sub-circuit is formed by a first NAND gate A3, first to third NOR gate A5, A7 and A8 and by an inverter A9. The first and second inputs of the NAND gate A3 are connected respectively to the emitters of the first and second transistors TR1 and TR2. The first and second inputs of the NOR gate A5 are connected respectively to the collectors of the first and second transistors TRI and TR2. The output of the NOR gate A5 is connected to a first input of the NOR gate A7. The output of the NAND gate A3 is connected to the input of the inverter A9.

The NOR gate A8 is connected to receive the output of the inverter A9 and the NOR gate A7 at its first and second inputs respectively. The output of the NOR gate A8 is connected to the second input of the NOR gate A7.

An up/down latch sub-circuit is formed by second and third NAND gates Al and A2. The second input of the NAND gate Al is connected to the emitter of the first transistor TRI by way of a resistor R2. The output of the NAND gate Al is connected to the first input of the NAND gate A2. The second input of the NAND gate A2 is connected to the emitter of the second transistor TR2 by way of a resistor R12. The output of the NAND gate A2 is connected to the second input of the NAND gate Al. The output of the NOR gate A5 is connected to anodes of diodes D5 and D6 respectively. The cathodes of the diodes D5 and D6 are connected to the second inputs of the NAND gates Al and A2 respectively.

The output of the NAND gate Al is connected to a first input of a further NAND gate A4 by way of series connected resistors Ri 5 and RI 6. The output of the NAND gate A2 is connected to a second input of the NAND gate A4 by way of series connected resistors Ri3 and R14. The anode of a diode D7 is connected to the node between the resistors R15 and R16. The cathode of the diode D7 is coupled directly to the first input of the NAND gate A4. The diode D7 thus is in parallel with the resistor R16. The anode of a diode D8 is connected to the node between the resistors R13 and R14. The cathode of the diode D8 is coupled directly to the second input of the NAND gate A4. The diode D8 thus is in parallel with the resistor Rl4.

The first and second inputs of the NAND gate A4 are connected to ground potential respectively by capacitors C4 and C3. The output of the NAND gate A4 is pulled towards Ground slightly by connection to Ground potential by a resistor R17.

The power inputs VDD and VSS of an integrated circuit ICi are respectively connected to the supply Voltage (VCC,) and Ground rails. The integrated circuit ICI is, in this example, an MC14O29B integrated circuit produced by ON Semiconductor of Phoenix, Arizona, USA. The MB14029B IC is a binary/decade up/down counter. It will be appreciated that any suitable arrangement could be used in place of the integrated circuit IC1.

A clock (CLK) input of the integrated circuit ICI is connected to the output of the NAND gate A4 by way of a resistor R18. The output of the NOR gate A7 is connected to the anode of a diode D9, the cathode of which is connected to the clock input of the integrated circuit ICI. A BID (binary/decade) input of the integrated circuit ICI is connected to Ground potential. P0 and P3 inputs of the integrated circuit IC1 also are connected to Ground potential. P1 and P2 inputs of the integrated circuit ICI are connected to supply Voltage.

A PE (preset enable) input of the IC is connected to each of the rotary encoder switches 101, 102, 103 by way of the eight core cable 104.

Carry Out and Q3 outputs of the integrated circuit IC1 are unconnected. Outputs Q 0, Qi and Q2 of the integrated circuit ICI are connected to a count management sub-circuit, which will now be described.

The output of the NAND gate A2 is connected to an U/D (up/down) input of the integrated circuit IC1.

A resistor R20 is connected on one side to supply Voltage and on the other side to anodes of diodes D10, DII, D12 and D16. The cathode of diode D16 is connected to Ground potential by way of a resistor R22. The cathode of diode D10 is connected to the U/D input of the integrated circuit ICI, and thus is connected directly to the output of the NAND gate A2. The cathode of the diode Dli is connected to output QI. The cathode of the diode D12 is connected to output Q2.

Cathodes of diodes D13, D14 and D15 are connected to a resistor R19, the other side of which is connected to Ground potential by a further resistor R21. The anode of the diode D13 is connected to the U/D input of the integrated circuit ICI.

The anode of the diode D14 is connected to the output QI of the integrated circuit ICI. The anode of the diode D15 is connected to the output Q2 of the integrated circuit IC1.

The base of a third transistor T3, this transistor being of the NPN type, is connected to the node at the junction of resistors R19 and R21. The emitter of the third transistor T3 is connected to Ground potential. The collector of the third transistor T3 is connected to supply Voltage by a resistor R23. The anode of a diode D17 is connected to the collector of the transistor TR3. The cathode of the diode D17 is connected to a Carry In input of the integrated circuit IC1 and to the node between the diode D16 and the resistor R22.

In this embodiment, supply Voltage is +15 Volts and Ground potential is -2 Volts, although these are merely examples.

Operation of the receiver circuit 100 of Figure 2 will now be described. In the following, a number of nodes are discussed. These nodes are defined as follows.

Node R is the second input of the NAND gate A3 and the emitter of the second transistor TR2, and is indirectly coupled to the L input. Node S is the first input of the NAND gate A3 and the emitter of the first transistor TR1, and is indirectly coupled to the J input. R' is the second input of the NAND gate A2, and is coupled to node R by resistor R12. 5' is the second input of the NAND gate Al, and is connected to node S by the resistor R2. R" is the second input of the NOR gate A5, and is coupled to the collector of the second transistor TR2. S" is the first input of the NOR gate A5, and is coupled to the collector of the first transistor TR1. A is the output of the NAND gate Al. B is the output of the NAND gate A2. A' is the first input of the NAND gate A4, and is indirectly coupled to A. B' is the second input of the NAND gate A4, and is indirectly coupled to B. Operation will now be described with reference also to Figure 3, which is timing diagram illustrating the Voltages of various nodes in the receiver circuit 100 of Figure 2. A3, A9, A5, A7 refer to the outputs of the respective gates. The uppermost eleven traces (down to A5) apply to both clockwise and anticlockwise rotation of an encoder switch 101, 102, 103. The next four traces relate to clockwise rotation and the last four relate to anticlockwise rotation.

-10 -In the timing diagram of Figure 3, the first two traces show Voltages at nodes S and R. When J or L changes Voltage, resistors RI and R5 together with capacitors CI and C2 (which respectively form slugging networks) slow down the changes in S' and R'; these changes are represented by the sloping portions of the two traces, although the actual changes are exponential, not linear as shown. The remaining traces show logic states at various nodes. The Figure shows the only significant order of logic changes for clockwise and anticlockwise rotation; their exact timing, which depends on the speed of rotation of the encoder, is irrelevant for the purposes of this explanation..

The inputJ and L are connected to the rotary encoder switches 101, 102, 103 shown in Figure 1. The condition at the beginning of the timing diagram is that all of the rotary encoder switches 101, 102, 103 are at a detent position.

In this, initial, state, S, R, R', S', R" and S" are all at logic level high'. As such, the inverter A9 is provided with a logic low', and the NOR gates A5 and A8 each provide a logic low' output. Since the output of the NOR gate A5 is logic low', the diodes D5 and D6 are not forward biased.

On the manipulation of one of the rotary encoder switches 101, 102, 103 in a clockwise direction by a user, the rotary encoder switch 101, 102, 103 causes the Voltage on J to start dropping from supply Voltage just before time TI.

At time TI, the fall in Voltage on node S causes the emitter voltage of TRI to fall below the level for forward biasing the TR1 base (at 14V), so that TR1 stops conducting, causing a drop in the Voltage at node S". The slope of S causes the logic states of S and S' (as seen by the inputs of A3 and Al) to fall later, when S has reached a lower level. The drop in Voltage at the node 5" causes the Voltage at the first input of the NOR gate A5 to cross the switching threshold. However, this does not cause a change in the state of any of the NOR gates A7 and A8, nor does it cause a change in any of the NAND gates Al, A2 and A3.

-11 -At time T2, the Voltage at the node S has fallen sufficiently to cross the switching threshold of the first input of the NAND gate A3. This causes the output of the NAND gate A3 to change from a logic low' to a logic high', and causes a change of the output of the inverter A9 to a logic low' from a logic high'. However, this does not result in any change in the output of the NOR gate A8.

Also at or about time T2, the Voltage at the node S' falls below the switching threshold for the second input of the NAND gate Al. This can be termed an active state for node S'. If the output of the NAND gate Al, i.e. node A, was at a logic low' and the output of the NAND gate A2, i.e. node B, was at a logic high, this change results in the output of each of these NAND gates reversing. If the NAND gates Al and A2 had outputs in logic states high' and low' respectively, there is no change resulting from the change in the Voltage at node S'.

If clockwise rotation continues, just before time T3, the Voltage on input L will fall and at time T3 the Voltage at node R has fallen sufficiently to result in the Voltage at the node R" falling below the switching threshold for the second input of the NOR gate A5. Because of the action of the capacitor C2, this occurs before the Voltage at node R falls by a similar amount. The resulting change at the second input of the NOR gate A5 causes a change in the output of the NOR gate from a logic low' to a logic high'. This results in a change in the output of NOR gate A7 from logic high' to logic low', and a change in the output of NOR gate A8 from logic low' to logic high'. This can be called an active state for the output of NOR gate A5. The logic high' output on the NOR gate A5 causes a positive potential to be supplied to the nodes R' and S'. Since the Voltage at node 5' was low, the change in the output of the NOR gate A5 results in the Voltage at the node 5' crossing the switching threshold for the second input of the NAND gate Al.

However, this does not result in any change at nodes A and B, i.e. the outputs of the NAND gates Al and A2.

At time T4, the Voltage on the node R input has fallen further, below the switching threshold for the second input of the NAND gate A3. However, this -12 -does not result in any change in the output of any of the logic gates of the receiver circuit 100.

If clockwise rotation continues, the voltage on input J rises and at time T5, the Voltage on the S node has risen sufficiently to allow the Voltage at node S to increase, (by charging of the capacitor CI through the resistors RI and R3), to the extent that it has crossed the switching threshold for the first input of the NAND gate A3. However, this does not result in the change in the output of any of the logic gates of the receiver circuit 100.

At time T6, the Voltage on the S node has risen further, to the extent that transistor TR1 conducts and the Voltage at node S" rises above the switching threshold for the first input of the NOR gate A5. This results in a change in the output of the NOR gate A5 from a logic high' to a logic low'. This has no effect on the output of the NOR gate A7. The removal of the logic high' from the output of the NOR gate A5 allows the Voltage at R' to fall from logic high' to logic low', which is the active state for this node. This is allowed because at this time the input L is at a low' Voltage, so current can flow through the resistors R12 and R5 and through the diode D2. The changing of the Voltage at the node R' from logic high' to logic low' results in a change at node B from a logic low' to a logic high'. This in turn results in a change in the output of the NAND gate Al (node A) from a logic high' to a logic low'. The change in the Voltage at node A does not result in a further change in the Voltage at node B. Just after the Voltage on L rises, at time T7 the Voltage on node R has risen (the capacitor C2 is charged by current flowing from supply Voltage through resistors R4 and R5) to the extent that the switching threshold for the second input of the NAND gate A3 is exceeded. This results in a change in the output of the NAND gate A3 from a logic high' to a logic low', and in a corresponding change in the output of the inverter A9 from a logic low' to a logic high', which is the active state for this node. This results in a change in the output Voltages of the NOR gates A7 and A8. At about the same time, the Voltage at node R' rises above the -13 -switching threshold for the second input of the NAND gate A2. However, this does not result in any change in the Voltage at node B. At time T8, the Voltage at node R has risen further to the point that TR2 conducts and the Voltage at node R" exceeds the switching threshold for the second input of the NOR gate A5. This does not result in a change in the output in any of the NAND gates Al, A2 and A3 nor in any of the NOR gates A5, A7 and A8.

Following time T8, the receiver circuit 100 is in the same state that it was prior to time TI, except that node A is at logic low and node B is at logic high whereas the Voltages at these nodes were previously unknown (depending on previous direction of rotation) and were, in any case, unimportant.

It will be appreciated from the above explanation that the output of the clock-enable latch output (at the output of NOR gate A7) changes from level low' to level high' at time T3 and changes from level high' to level low' at time T7.

Additionally, it will be appreciated that node A changes from logic high' to logic low' at time T6 and that node B changes from logic low' to logic high' at the same time. Furthermore, after the first cycle at least, node A changes from logic low' to logic high' at time T2, which is the same time at which node B changes from logic high' to logic low'.

The effect of the changes in the Voltages on nodes A and B on the NAND gate A4 will now be described. It will be appreciated from the above discussion that nodes A and B change substantially simultaneously, but in opposite directions, at time T6.

The following circuit operates more reliably when these changes at A and B are * made fast by using NAND gates Al and A2 with Schmitt-trigger inputs. At this time, node A changes from logic high' to logic low' and node B changes from logic low' to logic high'. Because of the connection of the diode D8 across the resistor R14, capacitor C3 is charged more quickly than capacitor C4 is discharged. This is because current can flow from the output of the NAND gate A2 through the resistor R13 and the diode D8 to the capacitor C3, but current from capacitor C4 needs to flow through resistors R16 and RIS, i.e. it cannot flow through the diode D7 because it is reverse-biased. The consequence of this is that the Voltage on the second input of the NAND gate A4 increases above the switching threshold some time before the Voltage on the first input of the NAND gate A4 falls below the switching threshold. As such, for a relatively short period of time (equal to the difference between the times of crossing of the thresholds on the second and first inputs of the NAND gate A4), the NAND gate A4 has two logic high' inputs.

During this short period of time, the output of the NAND gate A4 falls to logic low', but otherwise the output of the NAND gate is at logic high'.

The result of this operation is that the CLK input to the integrated circuit IC1 is provided with a relatively short negative pulse between time T6 and time T7, which pulse is not inhibited by diode D9 since the NOR gate A7 output is low. Since ICI requires a fast-rising signal at its clock input in order to provide reliable counting, a NAND gate with Schmitt-trigger inputs is best used for the NAND gate A4.

At time T2, node B changes from high' to low' and substantially simultaneously node A changes from low' to high'. At this time, the Voltage at the first input of the NAND gate A4 rises above the threshold relatively quickly due to the forward-biased diode D7. However, the Voltage at the second input of the NAND gate A4 falls less quickly, because current cannot flow through reverse-biased diode D8 and instead must flow through the resistor R14. However, since the clock enable latch output (at the output of NOR gate A7) is high (i.e. in its disable state), this does not result in a negative going pulse at the clock input of ICI.

As shown in Figure 2, node B is connected to the up/down input of an integrated circuit ICI. The integrated circuit ICI is arranged such that when the CARRY IN input receives a logic low' signal and a logic high' signal is received at the up/down input, it increments the count provided at the outputs QO to Q3 on every positive going edge of the clock signal. Because node B is a logic high' and the CARRY IN input receives a logic low' signal between time T6 and time T7, the positive edge of the clock signal occurring between T6 and T7 causes an increment in the count provided at the output QO to Q3 of the integrated circuit ICI. . The signal -15 -provided at the CARRY IN input of the integrated circuit ICI, and the mechanism by which it is provided, will now be described.

A resistor R20 is connected at one side to supply Voltage and at the other side to the anode of a diode D16. The cathode of the diode D16 is connected to a resistor R22, which is connected at its other side to Ground potential. The node between the diode D16 and the resistor R22 is connected directly to the CARRY IN input of the integrated circuit IC1. The node between the resistor R20 and the diode D16 is connected to the anode of a diode D1O, the cathode of which is connected directly to the up/down input of the integrated circuit ICI. The anode of the diode D1O is connected also to the anode of a diode Dli, the cathode of which is connected directly to the output Qi of the integrated circuit IC1. The anode of the diode D1O is also connected directly to the anode of a diode D12, the cathode of which is connected directly to output Q2 of the integrated circuit IC1.

A third transistor TR3 of the NPN type has its base electrode connected at the junction of resistors R19 and R21. The other side of R21 is connected to Ground potential. The other side of R19 is connected to the cathodes of diodes D13, D14 and D15. The anode of diode D13 is connected to the up/down input of the integrated circuit ICI. The anode of diode D14 is connected to the output QI of the integrated circuit IC1. The anode of diode D15 is connected to the output Q2 of the integrated circuit IC1. The collector electrode of the third transistor TR3 is connected to supply Voltage by a resistor R23. The anode of a diode D17 is connected to the collector of transistor TR3. The cathode of diode D17 is connected to the node between diode D16 and the resistor R22. The emitter electrode of the third transistor TR3 is connected directly to Ground potential.

Operation of this sub-circuit in the forward clockwise direction of rotation will now be described. The U/D input of IC1 is provided by the output of NAND gate A2, i.e. is set by node B. The connection of the diode D17 to the collector of the third transistor TR3 and to the CARRY IN input of the integrated circuit IC1 ensures that the integrated circuit -16 -IC1 receives a logic high' signal at the CARRY IN input when the third transistor TR3 is switched off. The base electrode of the third transistor TR3 is not connected directly to supply Voltage, but is indirectly connected to node B (the output of NAND gate A2), output QI of the integrated circuit IC1 and output Q2 of the integrated circuit IC1 via diodes D13, D14, D5 respectively and R19. If any of these signal sources is at logic high', current flows into the base of TR3 and TR3 is switched ON. When the negative clock pulse occurs, for clockwise rotation, node B is high, TR3 is ON, and D17 is reverse-biased so has no effect on GIN input of IC1.

The diodes D1O, DII, D12 are connected to the same signal three signal sources.

If each of these three signal sources is at a logic high' Voltage (which occurs when there is a count of six' at the outputs of ICI and a logic high' at the U/D input of Id, indicating an incremental count direction), each of the diodes Dl 0, DII and D12 is reverse biased. This causes diode D16 to be pulled high' by R20 and a logic high' signal to be provided to the CARRY IN input of the integrated circuit IC1.

The values of R20 and R22 are selected such that that of R22 is much greater than that of R20, so that in this state the Voltage at GIN is pulled sufficiently high by D16 to be interpreted as a logic high'. (The high value of R22 also ensures that R23 and Dl 7 pull GIN to logic high' when TR3 is OFF). This inhibits further counting by the ICI in the decrement count direction. As such, further rotation of the rotary encoder switches in the anticlockwise direction does not result in any further changes in the count output, although rotation of the rotary encoder switches in the clockwise direction does results in the count being incremented.

* The presence of an output count of one' and a decrement count direction is indicated by node B (the output of NAND gate A2), the output Qi of the integrated circuit ICI and the output Q2 of the integrated circuit ICI all being low'.

In this state, R19 is not pulled high' by any of D13, D14 and D15, so the base of transistor Q3 is grounded by R21. This pulls the anode of D17 high', so causes a logic high' signal to be provided to the CARRY IN input of the integrated circuit ICI. This inhibits further counting by the ICI in the decrement count direction.

-17 -As such, further rotation of the rotary encoder switches in the anticlockwise direction does not result in any further changes in the count output, although rotation of the rotary encoder switches in the clockwise direction does results in the count being incremented.

The generation of a clock signal is disabled by action of the NAND gate A3 and the inverter A9, in particular by the generation of a logic high' signal by the NOR gate A7 which is provided to the clock input of the integrated circuit IC1 by the diode D9, thus preventing the input from being pulled negative by a negative pulse on R18.

When both J and L are active (i.e. logic low'), the generation of a clock signal is enabled by action of the NOR gate A5 (at logic high'); A7 at logic low. In addition, a logic high' at the output of the NOR gate A5 is provided to the second inputs of the NAND gates Al and A2 by action of the diodes D5 and D6 respectively. This disables R' and S', which prevents switching of the NAND gates Al and A2.

The above description relates to operation when a rotary encoder switch 101, 102, 103 is rotated in a clockwise direction. Operation when a rotary encoder switch 101, 102, 103 is rotated in an anti-clockwise direction will now be described, again with reference to Figure 2. In the following it will be appreciated that the time axis of Figure 2 is reversed, so that time progresses from TI at the tight side of the Figure through T8, T7 and so on to TI at the left side of the Figure. As such, the signal on the L input line becomes active before the J input line becomes active.

This direction will be hereinafter referred to as the reverse direction.

Much of the operation of the receiver circuit 100 in the reverse direction is the same, albeit reversed, although there are some key differences. These are well illustrated by the output of the NOR gate A7, by nodes A and B and by the CLK signal, which are shown at the bottom of Figure 2 with an arrow facing to the left, denoting reversal of the time axis.

-18 -The NAND gates Al and A2 operate such that the voltage at node A changes from high' to low' at time T7 and changes from low' to high' at time T3. The voltage at node B changes from low' to high' at time T7 and changes from high' to low' at time T3. The low' (enabled) state at the output of NOR gate A7 extends from time T6 to time T2. Consequently, the negative going pulse that might have been caused after time T7 by the changing of nodes A and B is suppressed by the output of NOR gate A7 being high' at that time. Instead, the changing of nodes A and B at time T3 results in a negative going clock pulse shortly after time T3, and before time T2 when A7 is low' (enable).

In this way, a rising edge is experienced at the CLK input of ICI only after the J and L signals have passed through three transitions. This provides protection against inadvertent changing of the count provided at the outputs of the ICI.

Because node B is low' at the time of the clock pulse, the count is decremented by the rising edge of the CLK signal, i.e. the sequence of mood settings is moved through in the opposite direction.

If the rotary encoder switch 101, 102, 103 is rotated through three transitions of J and L then is rotated back in the other direction, two clock pulses are generated.

However, the U/D input on one of these clock pulses is high' and on the other clock pulse is low' so the overall count is unchanged. This is the case regardless of whether the initial rotation is clockwise or anticlockwise rotation.

If the rotary encoder switch 101, 102, 103 is rotated so that both J and L are active then is rotated back in the other direction before a third transition, no clock pulse is generated. This is the case regardless of whether the initial rotation is clockwise or anticlockwise rotation.

-19 -A consequence of this method of clock pulse generation vis-àvis the various transitions is that if a clock pulse has been generated by the last transition effected, then, whatever the subsequent direction of rotation, no clock pulse can occur until at least the 2nd transition.

This prevents plural uncontrolled pulses being generated by rapid transitions back and forth across the same contact change point, i.e. back and forth between any adjacent two of the four contact states shown at the top of figure 3 where continuous rotation makes the first state (only J active) and the last state (J and L inactive) also effectively adjacent; these transitions may be generated by inappropriate back and forth rotation of the user manipulable part 105 or by an intermittent contact (to ground) on one of the lines J or L. It will be appreciated by the skilled person that the application of a signal resulting from a user input to a clock input of an integrated circuit is unconventional.

Convention is to apply a signal resulting from an oscillator, for instance a periodic square wave signal, to clock input of integrated circuits. This feature results in lower power consumption, compared to a hypothetical corresponding circuit including a conventionally clocked integrated circuit.

Since in the receiver circuit 100 logic devices change state only when a rotary encoder switch 101, 102, 103 is operated, power consumption of the circuit is relatively low. The power consumption compares particularly favourably to a hypothetical microprocessor-controlled arrangement implementing corresponding functionality.

The arrangement of the receiver circuit 100 results in there being a separation between active periods of 5' and R'. This is advantageous since it can allow the receiver circuit 100 to avoid reacting to a input comprising rotation of a rotary encoder switch part way between successive rest positions, for instance rotation part way before returning to the start position. This can be advantageous in that it can avoid there being a change in the count where a rotary encoder switch is accidentally moved slightly, for instance through an external vibration or other -20 -mechanical input, or where the user changes their mind about effecting a change before completing rotation of a rotary encoder switch between successive positions.

Secondly, the arrangement can have relatively low power consumption. Low power consumption can result from the fact that the counter circuit is clocked' in response to user input instead of by a normal, periodic, clock signal.

The count output of the receiver circuit 100 comprises a number between I and 6 inclusive in binary form on the outputs QO, Qi, and Q2. This output is utilised in two separate ways.

Firstly, the count is fed back to the encoder switches 101,102, 103. The encoder switches incorporate simple logic which translates the count into a visible output on one of the six LEDs constituting the output transducer 106. Only one LED is illuminated at a given time. The LED at the same position is illuminated on all of the encoder switches 101, 102, 103 because they all receive the same count from the receiver circuit. Both logic and L.E.D. are supplied by VCC.

Secondly, the count is provided to a lighting control circuit, shown at 107 in Figure I and shown in some detail in Figure 5.

Referring to Figure 5, the lighting control circuit 107 includes QO, Qi, Q2 and power inputs, 24 preset potentiometers 500 (in a grid of four by six) and first to sixth lamp control outputs 501. In alternative embodiments, there are a different number of lamp control outputs 501 and a different plurality of preset potentiometers 500. The maximum number of preset potentiometers 500 is equal to the number of possible input count values multiplied by the number of lamp control outputs. In this embodiment, however, no present potentiometers are provided for two of the count input values, as is explained in more detail below.

A preset potentiometer 500 is a manually controllable variable potentiometer. It is called a preset because it is usually adjusted once, and that setting remains for a considerable period of time.

-21 -A first column of preset potentiometers 500 relates to a second mood setting. Each of the preset potentiometers 500 in that column relates to a different one of the lamp control outputs 501. The setting of that preset potentiometer 500 sets the voltage applied to the lamp control output 501, and thus sets the brightness of the connected lamp or lamps (not shown). Since different preset potentiometers 500 in the column can have different settings, different lamps (not shown) can be provided with different voltages via the lamp control outputs 501, and thus have different brightnesses.

None of the present potentiometers relate to a first mood setting. Instead, the first mood setting sets the Voltage applied to each of the lamp control outputs 501 at 0 Volts. As such, the first mood setting does not produce any light from any of the lamps connected to the lamp control outputs 501.

A second column of preset potentiometers 500 relates to a third mood setting.

Each of the preset potentiometers 500 in that column relates to a different one of the lamp control outputs 501. Since different preset potentiometers 500 in the column can have different settings, different lamps (not shown) can be provided with different voltages via the lamp control outputs 501, and thus have different brightnesses. These brightnesses can be different to the brightnesses provided in the first mood setting.

The other two columns of preset potentiometers 500 similarly are settable independently of the different preset potentiometers 500 of the other columns.

None of the present potentiometers relate to a sixth mood setting. Instead, the sixth mood setting sets the Voltage applied to each of the lamp control outputs 501 at the maximum available Voltage. As such, the sixth mood setting produces maximum illumination from all of the lamps connected to the lamp control outputs 501.

-22 -The result of this is the provision of six different mood settings, each of which is independent of the others. As such, the lighting control circuit 107 can alternatively be termed a "mood select" circuit.

The mood setting is selected by the receiver circuit 100 by providing a count value corresponding to the mood setting. Thus, indirectly, the mood setting is selectable by operation of any of the rotary encoder switches by a user.

Consequent of the relevant features described above, a user can switch the brightnesses of plural lamps between a number of (mood) settings by simple manipulation of a rotary encoder switch 101, 102, 103. Additionally, the mood setting can be changed by control of any of the rotary encoder switches 101, 102, 103. Moreover, the brightnesses for the second to fifth mood settings are adjustable, through control of the preset potentiometers.

The provision (by connection of preset enable to VCC by a reset switch 108) of a logic high signal at the FE input of the integrated circuit ICI causes the count output to be reset to value 6. In this way, actuation of any of the reset switches 108 causes the count to be reset to 6, i.e. to the mood setting in which all of the lamps are at maximum brightness.

In the above embodiments, the encoder switches 101, 102, 103 are dual output devices. These are sometimes known as incremental rotary encoders, quadrature encoders or relative rotary encoders.

A suitable rotary encoder switch is a switch of the PEC1 1 series produced by Bourns, Inc. of 1200 Columbia Ave., Riverside, CA 92507-2114, USA. Numerous other switches also have the appropriate functionality. It is preferred that the switches are endless switches (i.e. are switches without stops). It is relatively straightforward to provide for an off-the-shelf rotary encoder switch an output transducer 106.

-23 -In some embodiments (not shown), the rotary encoder switches are not provided with detents. Instead, the rotary encoder switches are not biased towards any stops.

The system operates in the same way with the use of such rotary encoder switches, although there is no tactical feedback to the user. The user may be informed of the position of the rotary encoder switch by way of markings on the switch and the user-manipulable part thereof. Feedback to the user is provided by way of the optical output 106.

It will be appreciated that the rotary encoder switches provide a gray code' output, in the sense that there is only one change at a given rotational position. This contributes to allowing the receiver circuit 100 to accurately and reliably detect operation of the encoder switched 101, 102, 103 and to accurately and reliably count the number of detents that are moved between.

In Figure 1, the rotary encoder switches 101, 102, 103 are connected in parallel with respect to the output lines J and L. In alternative embodiments, rotary encoder switches are connected in series. This is shown schematically in Figure 4. Referring to Figure 4, first to third rotary encoder switches 410, 402, 403 are shown connected in series on lines J and L. A ground line is connected at one end of each of the J and L lines. This arrangement utilises a receiver circuit 400 which is the same as the circuit shown in Figure 2. The other features shown in Figure 1 are present in the Figure 4 system but are omitted from the Figure for convenience.

As can be seen, each of the rotary encoder switches 401, 402, 403 includes a J switch 407 and an L switch 408. Each J switch 407 and each L switch 408 is in a closed position at the detents of the rotary encoder switches 410, 402, 403. Each J switch 407 and L switch 408 is connected in series in an appropriate one of the lines J and L. Each of the rotary encoder switches 401, 402, 403 includes a user-manipulable part 405. Each of the rotary encoder switches 401, 402, 403 also includes an output transducer 406. When a rotary encoder switch 401, 402, 403 is operated by rotation of its user-manipulable part 405, one of the switches 407, 408 opens before the other switch (on the other line). The switches 407, 408 are then -24-closed again, in the same order, as the rotary encoder switch 401, 402, 403 is rotated further.

The rotary encoder switches 401, 402, 403 are not conventional switches. The various manners in which a rotary encoder switch 401, 402, 403 as described could be produced will be apparent to the person skilled in the art.

It should be realised that the foregoing examples should not be construed as limiting. Other variations and modifications will be apparent to persons skilled in the art upon reading the present application. Such variations and modifications extend to features already known in the field, which are suitable for replacing the features described herein, and all functionally equivalent features thereof.

Moreover, the disclosure of the present application should be understood to include any novel features or any novel combination of features either explicitly or implicitly disclosed herein or any generalisation thereof and during the prosecution of the present application or of any application derived therefrom, new claims may be formulated to cover any such features and/or combination of such features.

Claims (9)

1. -25 -Claims 1. Apparatus comprising: two or more rotary encoder switches, each of the two or more rotary encoder switches being commonly connected to first and second signal lines, each switch being operable to provide signals on the first and second signal lines which are dependent on a direction of rotational actuation of the switch by a user; and a receiver connected to the first and second signal lines so as to receive the signals from the two or more rotary encoder switches, the receiver comprising a counter circuit operable to determine a count in response to changes in the signals, the receiver being arranged to provide the count at an output.
2. 2. Apparatus as claimed in claim 1, wherein the receiver includes a sub-circuit arranged to provide a signal to the counter circuit in response to a detection of a predetermined sequence of changes in the signals on the two or more signal lines.
3. 3. Apparatus as claimed in claim 2, wherein the predetermined sequence of changes is a first change on a first one of the two or more signal lines followed by a second change on a second one of the one or more signal lines followed by a third change on the first one of the two or more signal lines.
4. 4. Apparatus as claimed in any preceding claim, wherein the receiver comprises means for biasing the signal lines. This may allow the rotary encoder switches to be passive devices, i.e. it may allow the avoidance of a separate power supply for the rotary encoder switches.
5. 5. Apparatus as claimed in any preceding claim, comprising a lighting control circuit arranged to control plural lights on the basis of the count provided by the receiver.
6. 6. Apparatus as claimed in any preceding claim, wherein each of the two or more rotary encoder switches is provided with an output transducer, the state of which is dependent on the output of the receiver.
7. 7. Apparatus as claimed in any preceding claim, wherein each of the two or more the rotary encoder switches is connected to the first and second signal lines in parallel.
8. 8. Apparatus as claimed in any of claims I to 6, wherein each of the two or more the rotary encoder switches is connected to the first and second signal lines in series.
9. 9. A method comprising: connecting two or more rotary encoder switches commonly to first and second signal lines, each switch being operable to provide signals on the first and second signal lines which are dependent on a direction of rotational actuation of the switch by a user; and receiving the signals from the two or more rotary encoder switches at a receiver connected to the first and second signal lines; using a counter circuit of the receiver to determine a count in response to changes in the signals; and providing the count at an output.