GB2459751A

GB2459751A - Self contained memory subsystem

Info

Publication number: GB2459751A
Application number: GB0905031A
Authority: GB
Inventors: Dieter Staiger; Harald Huels
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2008-05-06
Filing date: 2009-03-25
Publication date: 2009-11-11
Also published as: GB0905031D0

Abstract

A primary printed circuit board (100) is electrically coupled to at least one subsystem (180), such as a memory subsystem (180), such as DIMM, wherein the subsystem (180) comprises at least one subsystem module (220) plugged into a connector (218). The subsystem (180) is fully self contained and is arranged on at least one separate subsystem board (210) electrically connected to the primary printed circuit board (100). A thermal link system may be provided to direct heat to one or more dedicated inner layers or the housing, using a flow of cooling fluid and may use heat pipes and/or vapour chambers. The board portions may be perpendicular and connected using a third flexible board portion. The first board area may consist of signal intergrity-sensitive electrical wiring and connected to the second area provided for memory support electronics. Memory subsystems may be symmetrically placed on either side or juxtaposed at the centre of the memory block to create a subsystem block. The subsystem block may be stacked.

Description

COMPUTER SYSTEM COMPRISING A SUBSLEM

AND SUBSYSTEM FOR A COMPUTER SYSTEM

FIELD OF THE INVENTION

The invention relates to a computer system comprising a subsystem and a subsystem for a computer system according to the preambles of the independent claims.

BACKGROUND OF THE INVENTION

Today, advanced microprocessors and in-plan near-future microelectronic devices developed by the leading processor technology companies are highly constrained with respect to memory bandwidth and memory size. In particular, the near future multi-core chips show significant increase in demand on memory size and data bandwidth.

Going along with the increased demand on memory capacity, the processor board real-estate and herewith the overall physical size of the computing system per server becomes an additional critical measurement, for instance by adding infrastructure cost to the overall system.

In order to increase the memory density e.g. on motherboards, standard memory modules such as DINN (D1IVIN = dual inline memory module) are replaced by so called very-low-profile modules (VLP modules). Such a very-low--profile module exhibits a smaller form factor than a standard DINN device and is therefore costly. The VLP-DIs used for increased packaging density allow to increase the amount of DINNs per given mother-board size by e.g. a factor of 1.5 to 2. This applies for a so called 1U Rackmount servers and single wide Blades. This factor is even higher for housings greater than lu.

Standard DINNs are small planar boards populated with memory modules, address-and control-registers and clock distribution/fan_out chips plugged into standard connectors on the server motherboard and can be produced at high quantities and a lower price compared to VLP-DINNs. VLP-DIs are typically used in height constraint form factors such as single wide Blades and therefore they are produced in low quantities.

As a side effect caused by such costly high capacity memory DINNs, low-end server manufacturers offering cost effective high volume servers request high DI socket count motherboards in order to benefit from the mature mass produced low performance and low capacity but very low cost memory DINNs.

Server systems like Blades or so called lU/nU rack systems or high-volume standard motherboard rack systems are typically highly motherboard real estate limited and therefore are highly production cost sensitive.

Besides using VLP-DIs and taking into account higher cost and reduced on-market variety of available modules is to give up Blade positions or increase the rack server system height to accommodate the increased demanded number of DINN sockets.

The US patent 6,950,312 B2 discloses a packaging assembly of electronic units comprising a multi-planar board system in which each single planar board provides electrical contacts and/or signal drive to its successive planar board via a flexible cable forming the only connection between successive planar boards. In its packaged position the planar boards are laid upon one another without affixing them with each other or affixing them with the housing of the electronic unit, wherein the packaging of the planar boards preferably forms a daisy chain.

In future computer systems the clock frequencies of the memory subsystems will be the bottleneck for the total performance of the computer system.

Fig. 1 depicts a prior art computer system comprising a memory subsystem. The memory subsystem requires about 1/3 of the real estate of the printed circuit board. As the DIrvfl4 area exhibits the highest wiring density of the board, the number of layers of the printed circuit board is determined by the requirements of the DI area.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an improved computer system comprising one or more subsystems which particularly allows for using standard DINM devices with improved memory density. Another object is to provide an improved subsystem for a computer system, particularly comprising standard DIMM with a high memory density. Further objects are to provide an improved subsystem board and an improved subsystem block for a subsystem.

These objects are achieved by the features of the independent claims. The other claims and the specification disclose advantageous embodiments of the invention.

According to the invention a computer system comprising a primary printed circuit board and one or more subsystems electrically coupled to the primary printed circuit board, wherein the subsystem comprises at least one subsystem module plugged into a connector. it is proposed that the subsystem is arranged on at least one separate subsystem board electrically connected to the primary printed circuit board. Preferably the at least one separate subsystem board is plugged onto the printed circuit board. Favorably, the subsystem is fully self contained and can be connected to a processor board by standardized connectors in standardized locations. The fully self contained subsystem will have all required support functions implemented. For a preferred self contained memory subsystem those functions are particularly one or more power supplies for multiple voltages, signal conditioning, signal fan out, signal buffering, signal termination, timing and skew adjustments. Favorably, control units can also be included, such as manufacturer specific memory controller interface e.g. serialized memory busses, as well as cooling and RAS.

Particularly, the subsystem can be a memory subsystem, preferably a memory subsystem comprising one or more memory DIs and corresponding JEDEC (JEDEC Solid State Technology Association; formerly known as Joint Electron Device Engineering Council) standardized connectors. To wider extend the complete architecture can also be utilized to carry instead of memory DINNs other small form factor cards like processors or active components like digital signal processors (DSP). It is also possible to mix DIMMs and processors and/or DSPs in the subsystem. In such an embodiment the one or more processors and/or DSPs can be addressed via the memory controller.

Advantageously, the fully self contained subsystem is decoupled from the primary printed circuit board. Particularly for a memory subsystem, one or more memory modules, particularly Dilvilvis, a power subsystem and subsystem support as well as RAS electronics (RAS = Reliability, Availability, Serviceability) are implemented on the separate subsystem board (memory board).

Thus, the subsystem can particularly be embodied as a fully

self-contained field-replaceable unit.

The design of the printed circuit board can be independent from the wiring requirements of the subsystem, particularly the memory subsystem. Moving the complex timing and speed critical wiring to the independent memory subsystem related PCB (PCB printed circuit board) is significantly reducing the motherboard complexity going along with costs savings due to reduced number of layers in the PCB. Using low loss material for the memory subsystem planar only will gain in signal quality. The primary printed circuit board which comprises the processor units can be made of a cheaper material than the board used for the fully self contained subsystem, particularly the memory subsystem. The invention allows for a standardization of the design of the fully self contained subsystem which can be used for various primary printed circuit board designs.

Preferably, the fully self contained subsystem, e.g. a memory subsystem, can comprise at least one subsystem block, e.g. at least one memory block, containing one or more of separate subsystem boards. An advantage is that the subsystem's functional capacity of the fully self contained subsystem can easily be enhanced by standardized subsystem blocks.

According to an advantageous embodiment of the invention the fully self contained subsystem can be connected to a dedicated subsystem area on the primary printed circuit board, thus facilitating the design of the computer System.

A further favorable development of the invention provides a thermal link system which can direct heat generated in the one or more subsystem modules into one or more dedicated inner layers inside the primary printed circuit board and/or into a housing encapsulating the primary printed circuit board and the fully self contained subsystem. This results in an effective removal of heat out of f the fully self contained subsystem. The heat from the fully self contained subsystem can be directed in a way to circumvent the processor area thus avoiding a deterioration of the cooling of the processor area. In combination with the placement of the preferred memory subsystem upstream of the processor area in the cooling fluid flow (particularly air flow) the thermal link system facilitates cooling of the computer system even at high heat load.

Favorably, the thermal link system can scale with the memory capacity, and subsystem size as well as capacity, respectively, and is particularly scalable to diverging server requirements.

The thermal link system is cost effective and reliable.

Favorably, a thermal link element can be arranged between the primary printed circuit board and the housing of the computer system.

According to an advantageous development of the invention, the thermal link system reduces the heat significantly through by-passing energy resulting in cooler air to the processors. The memory subsystem can be effectively cooled with reduced interference of the cooling of the processors on the primary printed circuit board. The heat conductivity within the thermal link system can be improved further if the first and/or the second thermal link elements can comprise one or more heat pipes and/or vapor chambers which can transport heat very efficiently.

The fully self contained subsystem can be attached to a dedicated subsystem area of the printed circuit board, wherein the subsystem area is located upstream of a processor area with respect to a flow of a cooling fluid. This allows for an effective cooling of the fully self contained subsystem. This is particularly useful if the fully self contained subsystem is a fully self contained memory subsystem with an the energy consumption which surmounts the processor subsystem energy consumption. This can happen with increasing memory size.

According to a further aspect of the invention a subsystem board for a computer system is proposed which comprises a first board portion which provides one or more connectors for attaching one or more subsystem modules to the first board portion; a second board portion which provides an interface for the one or more subsystem modules and for a primary printed circuit board to the subsystem board which can be attached to; and a third flexible board portion arranged between the first and second board portions for connecting the first and second board portions of the subsystem board. Favorably the subsystem board can be made of low loss high speed material. The fully self contained sabsystem can particularly be a memory subsystem. Preferably, the invention is useful for subsystems which otherwise would be equipped with small form factor cards, such as VLP DIMMs and/or other small form factor cards like processors or active components like DSP's.

The flexible joint provided by the third board portion between the first and the second board portions allows for a compact arrangement of the subsystem board. Instead of requiring a large base area, a large useable area for attaching subsystem modules can be established by tilting the first board portion with respect to the second board portion and making use of the space above the second board portion. The third board portion provides electrical and mechanical connection between the first and second board portions. The third board portion preferably is formed of layers, particularly of inner layers, of the printed circuit board which forms the subsystem board.

According to a preferred embodiment, standard DINN connectors can be arranged on the first board portion for receiving standard DilviN modules. By arranging the first board portion particularly rectangular to the second board portion low cost standard DI devices can be used which can be oriented with their main faces parallel to the primary printed circuit board.

Favorably, use can be made of the fact that a stack of two DI modules has a lower height than the DIMM module in its upright position. Therefore, instead using VLP DIMMs, standard DINNs can be used irrespective of their larger height.

Preferably a first dedicated board area can be provided for electrical wiring mainly consisting of signal-integrity-sensitive electrical wiring electrically connecting the one or more connectors and a second dedicated board area is provided for subsystem, particularly memory support electronics and a potential standardized subsystem-to-motherboard--connector. The electrical wiring in the first board portion and depending on the complexity of the buffer solution on the second board portion mainly consist of said signal-integrity-sensitive electrical wiring electrically connecting the one or more connectors. This eases a standardized design of the subsystem board which then can easily adapted to various computer processor boards.

Favorably, the second board area provides a dedicated standardized interface comprising real and/or virtual connectors for connecting the one or more subsystem modules on the first board portion to interface electronics on the second board portion and the interface electronics to a connector at the second board portion for connecting the subsystem board to a primary printed circuit board. The arrangement is useful for a standardized design of the subsystem board. The design of the subsystem board particularly in the first dedicated board area is reusable for different subsystem requirements in computer system without changing design of this area, wherein in the second dedicated board area particular implementations can be provided. By defining the standardized interface with said real and/or virtual connectors an adaptation of the signal-integrity-sensitive electrical wiring to particular implementations is facilitated.

A compact arrangement can be provided if one or more connectors for memory modules on the first board portion can be arranged with their main extensions in parallel.

According to still another aspect of the invention a subsystem block comprising at least one subsystem board, exhibiting at least one feature as described, above is proposed wherein a first board portion of the at least one subsystem board is inclined with respect to a second board portion of the at least one subsystem board and the first and second board portions are connected via a third flexible board portion. A compact subsystem arrangement is provided which according to a preferred embodiment featuring a memory subsystem allows to employing cheap standard DINM modules. The subsystem block can be a memory subsystem of a computer system or a part of a memory subsystem.

Advantageously, a memory subsystem consists of a multitude of memory blocks according to the invention.

Favorably two subsystem boards can be arranged symmetrically on both sides of a center plane in the center of the subsystem block yielding a subsystem block with a high functional density, e.g. memory density or processor density, by employing cheap standard memory or processor modules.

A compact arrangement is achievable if the second board portions of the two subsystem boards can be juxtaposed to each other at the center of the subsystem block with the first board portions forming outer walls of the subsystem block. Alternatively, the first board portions of the two subsystem boards can be juxtaposed to each other at the center of the subsystem block parallel to the center plane.

One or more connectors can be arranged on the first board portion with their main extensions parallel to each other. This -10 -allows stacking of a multitude of subsystem modules, e.g. DI modules, parallel to the connector which is designated for electrical contact to a processor board. A high density of subsystem modules can be achieved within the subsystem module.

Preferably two or more subsystem modules, each plugged into one connector of the first board portion, can be stacked one over another in a stack direction parallel to the center plane.

According to a favorable embodiment, one or more thermal link elements of a thermal link system can be provided which extract heat from the one or more subsystem modules towards at least one thermal interface juxtaposed to the second board portion.

Favorably, a first thermal link element arranged proximate to at least one subsystem module particularly arranged on a PCB can be oriented parallel to the main face of the subsystem module, thus providing a large-area thermal contact between the subsystem module and the thermal link element.

The first thermal link element can preferably be attached to a second thermal link element which is oriented perpendicular to the main face of the second board portion. The second thermal link element preferable has a large diameter and can remove a large amount of heat off the first thermal link element and thus from the memory module.

The first and second thermal link elements can advantageously be formed of high thermal conductive material. Particularly one or both can be embodied as a heat pipe.

According to an advantage embodiment a third thermal link element can be arranged between the second board portion of the at least one subsystem board and the subsystem modules proximate to the second board portion and/or a thermal link element can be -11 -juxtaposed to a connector which is provided on the second board portion for electrically connecting the at least one subsystem board to a primary printed circuit board.

Favorably, the thermal link system can comprise one or more heat pipes and/or vapor chambers for an effective heat removal.

According to a further aspect of the invention, a fully self contained subsystem of a computer system is provided comprising at least one memory block exhibiting at least one of the features described above. Preferably, the fully self contained subsystem can be a memory subsystem of a computer system and can comprise at least one memory block exhibiting at least one of the features described above.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention together with the above-mentioned and other objects and advantages may best be understood from the following detailed description of the embodiment, but not restricted to the embodiment, wherein is shown in: Fig. 1 a prior art example of a server board comprising a memory subsystem; Fig. 2a-c a top view of a primary printed circuit board indicating a location of a preferred subsystem board which is shown in an elongated state (Fig. 2a and 2b), a detail of a preferred interface module providing interfaces to the primary printed circuit board and to the subsystem board (Fig. 2a) and a possible CIDD arrangement in an elongated state (Fig. 2c) Fig. 3 a preferred subsystem board with a flexible joint; -12 -Fig. 4 a first preferred computer system with a lu height comprising a memory subsystem consisting of three memory blocks; Fig. 5 a second preferred computer system with a 2u height comprising a memory subsystem consisting of three memory blocks of different heights; Fig. 6 an example of an arrangement in a computer system according to a thermal load of a memory subsystem and a processor subsystem; Fig. 7 a first preferred memory block; Fig. 8 a second preferred memory block; Fig. 9 a third preferred memory block; Fig. 10 a preferred memory block indicating main flow directions of thermal flow.

The drawings are merely schematic representations, not intended to portray specific parameters of the invention. Moreover, the drawings are intended to depict only a typical embodiment of the invention and therefore should not be considered as limiting the scope of the invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENT

Fig. 2a-2c depict in a schematic way details of a preferred embodiment of a computer system 50 such as a Blade, Rackrnount system or a motherboard with a multi-core CPU chip which can be used for so called appliances. Computer appliances are enclosed system solutions that provide a narrow range of functions that are generally run on a hardware platform of their own (e.g. computer system 50).

By way of example the computer system 50 comprises a primary printed circuit board 100 which carries one or more processor -13 -Units (not shown) and a fully self contained subsystem 180 (in the following referred to as memory subsystem 180) connected to a subsystem controller 102 (in the following referred to as memory controller 102) arranged on the primary printed Circuit board 100 (Fig. 2a). In this and the other embodiments, the fully self contained subsystem according to the invention is described for a preferred memory subsystem 180 comprising one or more memory modules 220 in one or more memory blocks 200.

According to the invention the memory subsystem 180 comprises at least one pref erred memory block with at least one preferred subsystem board 210. The memory subsystem 180 is schematically illustrated by a single subsystem board 210 which is drawn in Fig. 2a in an elongated state for display reasons. Fig. 2b shows a side view of the subsystem board 210 in an elongated state.. As will be discussed later in detail, the subsystem board 210 is mounted with the first board portion 212 arranged in an angle, particularly perpendicular, to the second board portion 214.

The subsystem board 210 consists of a first board portion 212 and a second board portion 214 which are connected by a flexible third board portion 216 arranged between the first and second board portions 212, 214. The subsystem board is preferably made of a low loss, high speed material, preferably with a dielectric constant much better than standard FR4 (FR4=Flanie Retardant 4) (such as PTFE based materials) In the mounted Position, the first board portion 212 would be tilted perpendicular both to the second board portion 214 and the primary printed circuit board 100 wherein the third board portion 216 forms the joint between the first and the second board portions 212, 214.

The subsystem board 210 is coupled to the memory controller 102 via a connector 250 which provides connections between the -14 -subsystem board 210 to memory module ports, particularly DINN ports, Service processor interface, voltage supply, RAS control and the like on the primary printed circuit board 100.

A first dedicated board area 222 is provided on the subsystem board 210 for electrical wiring mainly consisting of signal-integrity-seijv electrical wiring electrically connecting the one or more connectors 218 which are arranged on the first board portion 212. The dedicated board area 222 occupies the majority of the first board portion 212. Memory modules 220, preferably standard DIMM modules, are plugged into the connectors 218; preferably, the memory modules 220, particularly DI?flvI modules, are plugged into DI sockets with JEDEC (JEDEC Solid State Technology Association; formerly known as Joint Electron Device Engineering Council) standard employed as connectors 218.

A second dedicated board area 230 is provided for memory support electronics and interface electronics 232. The second board area 230 provides a dedicated standardized interface comprising real and/or virtual connectors 224, 226, 228 for connecting the one or more memory modules 220 on the first board portion 212 to interface electronics 232 on the second board portion 214 and the interface electronics 232 to a connector 250 at the second board portion 214 for connecting the subsystem board 210 to a primary printed circuit board 100. The second dedicated board area 230 also carries units such as server processor interface electronics 234, a voltage generator 236 providing a voltage VR for each pair of memory modules 220, and memory-module RAS electronics 238. Slave units 240 are arranged at the first board portion 212. The memory signals are terminated at the end of the wires with the terminator T. For optimized efficiency the terminators T are provided a specific terminator voltage supplied by the common voltage generators.

-15 -The interface electronics 232, particularly comprising a memory buffer, Preferably provides first connectors 224, which are consistent virtual connectors on design level, at dedicated locations of its first interface side assigned to the memory modules 220, particularly a standard DINM interface side for DINN modules. The interface electronics 232 preferably provides second virtual cormectors 226, which are consistent virtual connectors on design level, at dedicated locations of its second interface side assigned to the memory controller 102 and the connector 250, respectively. The second board area 230 comprising the electronics area 232 can be easily adapted to particular implementations by running concrete protocols on the virtual connectors 224, 226. The first board area 222 with the high wiring density is particularly reusable on detail design level.

Preferably, the interface electronics 232 can be embodied as an interface chip module. Fig. 2c depicts a preferred embodiment of the interface electronics 232 (CIDD module = Common Interface DI Drive module). By way of example the virtual connector 226 is connected to a first and a second memory channel Mem_ChnO, Mem_Chnl, wherein the first and the second memory channel split into two channels for two virtual connectors 224 each.

As illustrated in Fig. 3, a preferred embodiment of the subsystem board 210 implemented into the preferred computer system 50 in Fig. 2, exhibits a first board portion 212 which provides one or more connectors 218 for one or more memory modules 220. The connectors 218 are preferably standard DI connectors for standard DI modules as memory modules 220. The second board portion 214 provides electrical and mechanical connections to the primary printed circuit board 100, e.g. support electronics for the one or more memory modules 220 and a connector 250. The connector 250 is particularly a connector of very low height.

-16 -As already is described in Fig. 2a the electrical wiring in the first board portion 212 mainly consists of signal-integrjty_ sensitive electrical wiring (not shown) electrically connecting the connectors 218 and the one or more memory modules 220 (Fig. 2b) among to the interface electronics 232. The signal-integrity_sen5jj electrical wiring is arranged in the dedicated area 222 (Fig. 2a) in the first board portion 212 where a high number of layers within the subsystem board 210 can be provided to allow for length matching of the timing critical signals. By removing such sensible wiring from the primary printed circuit board 100 (motherboard) and applying it on the dedicated area 222 of the subsystem board 210, the expensive requirements of low damping in the board material and the high number of layers in the board are shifted from the large-area primary printed circuit board 100 to the much smaller subsystem board 210.

The amount of required layers of the second board portion 214 is mainly depending on the complexity of the CIDD electronics. Both boar portions can differ but most typically the amount of layers is equal to the first board portion 212 and particularly can be fabricated of high quality material which allows for very high signal propagation speed and low damping. Preferably, only those components which require high propagation speed are placed on this second board portion 214, whereas such wiring responsible for signal matching between the memory modules 220 can be placed on the first board portion (212) and the third board portion (216) . The connectors 218 are preferably standard DINN connectors with their main extension perpendicular to the paper plane of the Fig. 3 which can receive standard DI modules. Two arrows indicate the direction in which the DIMM modules are plugged into the Connectors 218.

-17 -The flexible third board portion consists of one or more signal layers, particularly inner layers of the subsystem board 210, which itself is a printed circuit board. As the first board portion 212 has to fulfill the requirements of the signal-integrity-sefl5i electrical wiring, particularly a high number of layers in the board, a primary printed circuit board can be designed with less metallized board layers than required for the memory subsystem.

Figs. 4 and 5 display by way of example a first and a second pref erred embodiment of a computer system 50 according to the invention as a side view cut through the computer system 50 displaying the arrangement of a memory subsystem 180 placed on a primary printed circuit board 100 or motherboard, which board contains one or more processors (not shown).

In the examples shown the memory subsystem 180 consists of three memory blocks 200 which each is composed of two subsystem boards 210 as described in Fig. 3. As will be described later in detail, the memory blocks 200 also comprise a thermal link system 300 (Figs. 7 through 10) for effectively cooling the memory modules 220 (Fig. 2a).

Only a few components of the system 50 are denoted with reference numerals for clarityreasons. The components will be described in more details in Fig. 7 through 10.

As can be easily seen in the drawing, the memory modules 220 are oriented with their main faces parallel to the main face of the primary printed circuit board 100 and stacked one over another perpendicular to the main face of the primary printed circuit board 100.

-18 -The primary printed circuit board 100 is coupled to a housing 150, Particularly a metal case, via a thermal link element 320 which provides an intense thermal contact between the primary printed circuit board 100 and the housing 50 as well as damping to protect the primary printed circuit board 100 and the memory subsystem 180 against mechanical shocks.

Fig. 4 presents an example embodiment of a single wide Blade computer system 50 in a single wide housing 150 with only two memory modules 220 per subsystem board 210. One memory block 200 carries four memory modules 220 which yields in this example twelve memory modules 220 in a single wide housing 150.

Preferably standard DINN modules can be used as memory modules 220.

The height of the stacked memory modules 220 is lower than the clearance of the memory modules 220 including the connectors 218 measured from the foot of the connector 218 to the free end of the memory module 220 plugged into the connector 218. By way of example, by using standard DDR3 D1MMs providing 8 GB per DI the memory subsystem 180 provides 96 GB per primary printed circuit board 100 in a single wide Blade housing 150.

Fig. 5 depicts an example embodiment of a dual wide Blade computer system 50 with a memory subsystem 180 comprising memory blocks 200 of different memory capacities, i.e. block heights.

Two memory blocks 200 are equipped with two subsystem boards 210, each containing two stacked memory modules 220 each and one memory block 200 on the left hand side inside the housing 150 contains two subsystem boards 210 carrying each five memory modules 220 stacked one over another. By way of example the memory subsystem 180 provides eighteen memory modules 220 resulting in 144 GB per primary printed Circuit board 100 in a dual wide housing 150 when employing DDR3 DIMMs with 8 GB per DIMIvI.

-19 -In this example embodiment a free space 160 is left over the two lower memory blocks 200 at the right hand side inside the housing 150. The free space 160 can be used e.g. for a front side access Particularly for hot-pluggable features such as cards, disk drives and the like.

What can be easily recognized in the embodiments featured in Figs. 4 and 5, an identical design of the primary printed circuit board 100 (motherboard) can be used for single wide and dual wide as well as for even wider systems. In conventional Blade systems, for example, two primary printed circuit boards would be necessary for holding and supplying such a number of DThiMs as memory modules 220.

As can be seen in Figs. 4 and 5, the memory blocks 200 are easily permeable for a coolant such as an air flow for cooling components on the primary printed circuit board 100 in the housing 150 arranged on the primary printed circuit board 100 behind the memory subsystem 180.

This favorable property can be used for a preferred cooling arrangement of the memory subsystem 180 on the primary printed circuit board 100, which is illustrated in Fig. 6 as a top view on a pref erred arrangement.

The memory subsystem 180 of a computer system is connected to a memory area 110 of a primary printed circuit board 100. The memory subsystem comprises one or more memory blocks 200 comprising memory modules 220 attached to subsystem boards 210.

The primary printed circuit board 100 is divided into three areas 110, 120, 130.

The memory area 110 is located towards the front side 106 of the primary printed circuit board 100. Figs. 4 and 5 show a typical -20 -view presented by the memory blocks 200 arranged on the front side 106.

Juxtaposed to the memory area 110 is a processor area 120 with e.g. two processor chips arranged on the primary printed circuit board 100. Juxtaposed to this processor area 120 is an auxiliary electronics area 130 for typical support electronics of the primary printed circuit board 100 such as I/O electronics, drive units, card units etc. Shown by Fig. 6, a coolant flow 330 of a cooling medium, e.g. air cooling, impinges on the front side 106 and cools the memory subsystem io prior to flowing around the processor area 120 taking account of the higher cooling requirements of the high memory density of the memory subsystem 108.

According to the invention, the memory blocks 200 are effectively cooled by an integrated thermal link system which removes heat off the memory blocks 200 without excessively heating the coolant and which directs the heat flow away from the processor area 120. Although the processor area 120 is arranged downstream of the memory subsystem 180 the thermal load added to the coolant flow 330 by the memory subsystem 180 is only marginal, thus avoiding to deteriorate the cooling of the processor area 120.

Referring now to Figs. 7 to Fig. 10 several preferred embodiments of a memory block 200 are illustrated. The memory block 200 is mounted on a primary printed circuit board 100 comprising an integrated thermal link system 300, wherein Fig. depicts the heat flow in detail. The thermal link system 300 provides thermal interfaces 304 between the memory block 200 and the primary printed circuit board 100 and the housing 150.

-21 -The thermal link system 300 consists of a multitude of thermal link elements 310 to 324. The thermal link system 300 is discussed in detail now.

A memory block 200 preferably Consists of one or two subsystem boards 210 comprising a first board portion 212 connected to a second board portion 214 connected by a third board portion 216, wherein the first board portion 212 is tilted, particularly perpendicular to the second board portion 214. The first board portion's main face is perpendicular to a main face of the primary printed circuit board 100 and the main face of the second board portion 214 is parallel to the main face of the primary printed circuit board 100.

The first board portion 212 carries connectors 218 in which a memory module 220 such as a DIMN is mounted. Each memory module 220 is contacted at its main faces by a first thermal link element 310, particularly a high thermal conductive material (e.g. copper plate or heat pipe and/or vapor chambers). The main faces of the memory modules 220 as well as of the first thermal link elements 310 are oriented parallel to the primary printed circuit board 100. The first thermal link elements 310 are connected, via a very low thermal resistance (e.g. soldering or welding) to a second thermal link element 312, which is perpendicular to the main face of the primary printed circuit board 100. The free ends of the first thermal link elements 310 opposite of the second thermal link element 312 are fixed with clamps 302 to the memory modules 220 so that one memory module 220 is arranged between two first thermal link elements 310.

The second thermal link element 312 has a rod-like body and can be a massive metal slab, a heat pipe and/or vapor chamber with a liquid core or a chamber like liquid cooler. it can be mounted in the center of the memory block 200 as in Figs. 7, 8, 9, 10 or be a part of the outermost face of the memory block 200 as shown -22 -in Fig. 8. The second thermal link element 312 can be screwed to the primary printed circuit board 100. The second board portion 214 is attached to the primary printed circuit board 100 via a stiffener element 260 around the interface electronics 232, which is particularly a interface module or buffer, wherein the stiffener element 260 can be screwed to the primary printed circuit board 100. The stiffener element 260 provides a high mechanical force to avoid deformations of the second board portion 214 when attached to the primary printed circuit board 100. Required forces for this are typical in the range of 8 to g/pin which can add up to 50 kg for the multi-pin LGA-(Land Grid Array) connector 250 which electrically connects the second board portion to the primary printed circuit board 100.

Between the lowest memory modules 220 above the second board portion 214 and the interface electronics 232 mounted on the second board portion 214 a third thermal link element 314 can be arranged. The third thermal link element 314 is preferably a so called heat pillow made of an elastic material with a high thermal conductivity. The thermal link element 314 is preferred when using a high power memory buffer as interface electronics 232. on the side opposite to the side of the second board portion 214 carrying the interface electronics 232 the connector 250 can be surrounded by a thermal link element 318.

The interface region between the second thermal link element 312 and the primary printed circuit board 100 can be furnished with a thermal link element 316 which fills up the space between the second thermal link element 313 and the interface electronics 232, the stiffener element 260, the second board portion 214 and the connector 250 and the thermal link element 318 surrounding the connector 250 as shown in Figs. 7 and 10. Between the primary printed circuit board 100 and the housing 150 a thermal link element 320 can be provided which connects the primary printed circuit board 100 to the metal housing 150.

-23 -Preferably, the thermal link elements 314, 316, 318 and 320 are elastic and particularly a gap fill material e.g. silicone material with a high thermal conductivIty.

The perpendicular channels indicated in the second board portion as well as the primary printed circuit board 100 below the connectors 250 symbolize the thermal flow from the memory block to the primary printed circuit board 100 and the housing 150. Dedicated inner layers 104 inside the primary printed circuit board 100 are also provided to conduct heat inside the primary printed circuit board 100 and remove the thermal load out of the region of the memory blocks 200.

Whereas in Fig. 7 the two subsystem boards 210 of the memory block 200 are connected with their second board portions 214 in the center of the memory block 200 with the first board portions 212 forming outer walls of the memory block 200 and with the second thermal link element 312 forming a central slab, Fig. 8 shows an embodiment in which the first board portions 212 form center walls of the memory block 200 and the first board portions 212 are connected with their main faces at a center plane 202 of the memory block 200. In this embodiment the second thermal link elements 312 form outer walls of the memory block 200.

Fig. 9 shows a connection of the central second thermal link element 312 embodied as a larnella element 322 wherein elements mounted on the primary printed circuit board 100 mesh with elements mounted on the second thermal link element 312 make an interdigital contact.

Referring now to Fig. 10 the heat flow in the memory block 200 and the primary printed circuit board 100 as well the housing is depicted in detail.

-24 -Heat developed in one of the memory modules 220 is transported into the first thermal link elements 310 contacting both main faces of the memory modules 200 and is extracted through the second thermal link element 312 towards the primary printed circuit board 100. Heat developed in the interface electronics 232 is partly transported by the third thermal link element 314 into the first thermal link element 310 arranged at the undermost memory module 220. This part is also extracted by the second thermal link element 312. Another part of the heat is transported through the second board portion 214 and the connector 250 into the primary printed circuit board 100 where it is guided away through dedicated inner layers 104 of the primary printed circuit board 100 together with the heat transported by the second thermal link element 312 towards the primary printed circuit board 100. By this thermal link system it is possible to let a remarkable amount of heat, e.g. about 30%, by-pass the processor area 120 arranged downstream of the memory blocks 200 (Fig. 6) thus diminishing the heat load of the coolant flow 330 (Fig. 6) flowing from the memory area 110 to the processor area 120.

The amount of heat removed from the memory blocks 200 can be increased and the heat load of the coolant flow 330 can be diminished further if a part of this heat amount is guided to the housing 150 by the thermal link element 320 arranged between the primary printed circuit board 100 and the housing 150.

Favorably, the invention allows for a compact memory packaging density and a memory subsystem field replaceable unit (FRU) with a high number of memory modules, particularly DThINs per physical space. A high performance memory subsystem FRU can be achieved by "decoupling" the high speed memory subsystem 180, e.g. 1.6 GHz from system motherboard, i.e. the primary printed circuit board 100. By employing JEDEC (JEDEC Solid State Technology -25 -Association; formerly known as Joint Electron Device Engineering Council) specified standard DIMMs off-the-shelf cost-effective and earliest available advanced DIMMs can be utilized. A fully self-contained memory subsystem FRU can be provided with x4 to x16 DIs per memory block 200 including a power subsystem, memory support and RAS electronics (active memory blocks 200 including memory buffer (interface electronics 232).

The high speed subsystem board 210 enables to use a high performance hybrid planar material with a low loss factor and superior signal integrity. Universal mechanical design allows to covering diversity of server form factors. The cooling concept employing integrated thermal link elements facilitates cooling of the system. The cooling concept scales with the memory capacity and is scalable to diverging server requirements provides a cost effective and reliable solution.

Claims

-26 -CLAIMS1. A computer system (50) comprising a primary printed circuit board (100) and at least one subsystem (180), such as a memory subsystem (180), which is electrically coupled to the primary printed circuit board (100), wherein the subsystem (180) comprises at least one subsystem module (220) plugged into a connector (218), characterized in that the subsystem (180) is fully self contained and is arranged on at least one separate subsystem board (210) electrically connected to the primary printed circuit board (100).
2. The computer system according to claim 2, characterized in that the fully self contained subsystem (180) comprises at least one subsystem block (200) consisting of one or more of the separate subsystem boards (210).
3. The computer system according to claim 2 or 2, characterized in that the fully self contained subsystem (180) is connected to a subsystem area (110) of the primary printed circuit board (100).
4. The computer system according to one of the preceding claims, characterized in that a thermal link system (300) is provided which directs heat from the subsystem (180) into one or more dedicated inner layers (104) inside the primary printed circuit board (100) and/or into a housing (150) encapsulating the primary printed circuit board (100) and the fully self contained subsystem (180).
5. The computer system according to claim 4, characterized in that a thermal link element (320) is arranged between the primary printed circuit board (100) and the housing (150).

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6. The computer system according to claim 4 or 5, characterized in that the thermal link system (300) by-passes a flow (330) of a cooling fluid cooling a processor area (120) of the primary printed circuit board (100).
7. The computer system according to one of the preceding claims, characterized in that the fully self contained subsystem (180) is attached to a memory area (110) of the primary printed circuit board (100), which is located upstream of a processor area (120) with respect to a flow (330) of a cooling fluid.
8. The computer system according to one of the preceding claims, characterized in that the fully self contained subsystem (180) is a memory subsystem (180)
9. A subsystem board (210) for a computer system (50), comprising -a first board portion (212) which provides one or more connectors (218) for one or more memory modules (220), -a second board portion (214) which provides an interface (230) for the one or more subsystem modules (220) and for a subsystem controller (102) mounted on a primary printed circuit board (100) to which the subsystem board (210) can be attached to; -a third flexible board portion (216) arranged between the first and second board portions (212, 214) for connecting the first and second board portions (212, 214) of the subsystem board (210).
10. The subsystem board according to claim 9, characterized in that the first board portion (212) is arranged perpendicular to the second board portion (214) in its mounted state on a primary circuit board (100).A-28 -
11. The subsystem board according to claim 9 or 10, characterized in that a first dedicated board area (222) is provided for electrical wiring mainly consisting of signal-integrity-sensjtjve electrical wiring electrically connecting the one or more connectors (218) and a second dedicated board area (230) is provided for memory support electronics.
12. The subsystem board according to claim 11, characterized in that the second board area (230) provides a dedicated standardized interface comprising real and/or virtual connectors (224, 226, 228) for connecting the one or more subsystem modules (220) on the first board portion (212) to interface electronics (232) on the second board portion (214) and the interface electronics (232) to a connector (250) at the second board portion (214) for connecting the subsystem board (210) to a primary printed circuit board (100)
13. The subsystem board according to one of the claims 9 to 12, characterized in that the one or more connectors (218) arranged on the first board portion (212) are arranged with their main extensions (221) in parallel.
14. A subsystem block (200) comprising at least one subsystem board (210) according to one of the claims 9 to 13, characterized in that a first board portion (212) of the at least one subsystem board (210) is inclined with respect to a second board portion (214) of the at least one subsystem board (210) and the first and second board portions (212, 214) are connected via a third flexible board portion (216)
15. The subsystem block according to claim 14, characterized by two subsystem boards (210) arranged syrnxrietrically on both -29 -sides of a center plane (202) in the center of the memory block (200)
16. The subsystem block according to claim 15, characterized in that the second board portions (214) of the two subsystem boards (210) are juxtaposed to each other at the center of the memory block (200) with the first board portions (212) forming outer walls of the subsystem block (200).
17. The subsystem block according to claim 15, characterized in that the first board portions (212) of the two subsystem boards (210) are juxtaposed to each other at the center of the subsystem block (200) parallel to the center plane (202)
18. The subsystem block according to claim 14 to 17, characterized in that one or more connectors (218) are arranged on the first board portion (212) with their main extension (221) parallel to each other and parallel to a transverse edge (206) of the subsystem board (210).
19. The subsystem block according to claim 14 to 18, characterized in that two or more subsystem modules (220) each plugged into one connector (218) are stacked one over another in a stack direction perpendicular to the main face (215) of the second portion (214)
20. The subsystem block according to one of the claims 14 to 19, characterized in that one or more thermal link elements (310, 312, 314, 316, 318) of a thermal link system (300) are provided which extract heat from the one or more subsystem modules (220) towards at least one thermal interface (304) juxtaposed to the second board portion (214) . -30 -
21. The subsystem block according to claim 20, characterized in that a first thermal link element (310) proximate to at least one subsystem module (220) is oriented in parallel to the main face of the subsystem module (220).
22. The subsystem block according to claim 21, characterized in that the first thermal link element (310) is attached to a second thermal link element (312) which is oriented perpendicular to the main face (215) of the second board portion (214)
23. The subsystem block according to one of the claims 20 to 22, characterized in that a third thermal link element (314) is arranged between the second portion (214) of the at least one subsystem board (210) and the subsystem modules (220) proximate to the second board portion (212) and/or that a thermal link element (318) is juxtaposed to a connector (250) which is provided for electrically connecting the at least one subsystem board (210) to a primary printed circuit board (100).
24. The subsystem block according to one of the claims 20 to 23, characterized in that the thermal link system (300) comprises one or more heat pipes and/or vapor chambers.
25. A fully self contained subsystem (180) for a computer system (50) comprising at least one subsystem block (200) according to one of the claims 14 to 24.