GB2457872A - Thin-film transistor using nano-crystalline thin-film as active layer, and method for fabricating the same - Google Patents

Thin-film transistor using nano-crystalline thin-film as active layer, and method for fabricating the same Download PDF

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GB2457872A
GB2457872A GB0802637A GB0802637A GB2457872A GB 2457872 A GB2457872 A GB 2457872A GB 0802637 A GB0802637 A GB 0802637A GB 0802637 A GB0802637 A GB 0802637A GB 2457872 A GB2457872 A GB 2457872A
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nano
layer
crystalline
thin
substrate
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Sangsig Kim
Kyoungah Cho
Dong-Won Kim
Jaewon Jang
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Industry Academy Collaboration Foundation of Korea University
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Industry Academy Collaboration Foundation of Korea University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

A top-gate thin-film transistor includes a substrate 10 made of glass, silicon, or plastic; a hydrophilic buffer layer 15 deposited on the substrate to facilitate the formation of a nano- crystalline thin-film thereon; a thermally treated nano-crystalline thin-film layer 20 as an active layer; source and drain electrodes 31, 32; a gate insulating layer 40 formed on the nano-crystalline thin-film layer by use of a high dielectric constant insulator and a top-gate electrode 50 formed on the gate insulating layer. With this configuration, the top-gate thin-film transistor and a logic circuit using the same can be operated at low voltages and be fabricated at low-temperatures.

Description

THIN-FILM TRANSISTOR AND LOGIC CIRCUIT USING NANO-
CRYSTALLINE THIN-FILM AS ACTIVE LAYER, AND METHOD FOR
FABRICATING THE SAME
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a thin-film transistor and a logic circuit using a nano-crystalline thin-film as an active layer, and a method for fabricating the same. More particularly, the present invention relates to a top-gate thin-film transistor and a logic circuit using nano-crystals, comprising: a flexible substrate made of glass, plastic, or silicon; a hydrophilic buffer layer deposited on the substrate to facilitate the formation of a nano-crystalline thin-film thereon; a thermally treated nano-crystalline thin-film layer as an active layer; a gate insulating layer formed on the nano-crystalline thin-film layer by use of a high dielectric constant insulator; and a top-gate electrode formed on the gate insulating layer, thereby enabling low-voltage operation and low-temperature fabrication of the transistor, and a method for fabricating the same.
Description of the Related Art
In the fabrication of thin-film field-effect
transistors currently used in flat panel displays including a liquid crystal display (LCD), it is general that an active layer is made of amorphous silicon (aSi:H) or polycrystalline silicon, and that silicon oxide or nitride is used as a gate insulator.
Recently, as an effort to realize low-temperature processes for thin-film transistors and to reduce production costs thereof, studies for the fabrication of thin-film transistors using organic materials, such as pentacene, hexathiophene, etc., have been actively ongoing. However, the resulting organic thin-film transistors have a radical limit in mobility, physical and chemical stability, etc., and also, are difficult, with the current degree of skill, to be directly applied to conventional processes for inorganic semiconductors.
To solve the above described problems, as one example, B. A. Ridley, B. Nivi, and J. M. Jacobson in Massachusetts Institute of Technology (MIT) (USA) had reported a study for the fabrication of a thin-film transistor using CdSe nano-crystals (See the journal Science, Vol. 286, p. 746, 1999).
The above study proposed the possibility of a thin-film transistor using nano-crystals via the fabrication of a transistor having a field-effect mobility in the degree of lcm2/Vsec and a on/off current ratio of more than l0.
As another example, D. V. Talapin and C. B. Murray in the 1MB (USA) reported a study for the fabrication of a thin-film transistor using PbSe nano-crystals (See the journal Science, Vol. 310, p. 86, 2005).
In the above study by D. V. Talapin and C. B. Murray, a nano-crystalline film was chemically processed with hydrazine to improve the conductivity of the film, and subsequently, was subjected to a thermal treatment to fabricate n-channel/p-channel transistors. As could be understood from the above studies, the use of inorganic semiconductor nano-crystals is effective to solve inherent problems of organic materials while achieving advantages of solution processes as represented by organic thin-film transistors.
However, in the case of conventional inorganic transistors using inorganic semiconductor nano-crystals developed up to now and most organic thin-film transistors, they take the form of back-gate transistors, in which a gate insulating layer is made of silicon dioxide (Si02) obtained by oxidization of a silicon substrate. Such back-gate transistors have a need for an enormous gate voltage of more than several decade voltages.
Moreover, most nano-crystalline thin-film transistors have been fabricated by use of a silicon substrate. Due to a difficulty in the deposition of a nano-crystalline film on a plastic substrate, and other problems such as the risk of deformation and possible damage to the plastic substrate caused during fabrication processes, currently, characteristics of thin-film transistors using a plastic substrate have not been confirmed. Also, no logic circuit, which is essential to flexible electronic products, has been realized by use of an inorganic nano-crystalline thin-film.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a top-gate thin-film transistor and a logic circuit using nano-crystals, comprising: a substrate made of silicon, glass, or plastic; a hydrophilic buffer layer deposited on the substrate to facilitate the deposition of a nano- crystalline thin-film thereon; a thermally treated nano-crystalline thin-film layer as an active layer; a gate insulating layer formed on the nano-crystalline thin-film layer by use of a high dielectric constant insulator; and a top-gate electrode formed on the gate insulating layer, thereby enabling low-voltage operation and low-temperature fabrication of the transistor, and a method for fabricating the same.
It is another object of the present invention to provide a logic device and a unit thin-film transistor constituting the logic device, and a method for fabricating the same, wherein an active layer of the thin-film transistor is selectively formed to achieve the integration of the logic device while minimizing interference caused upon integration of the device.
In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a method for fabricating a thin-film transistor using a nano-crystalline thin-film as an active layer, comprising: forming a buffer layer, made of a hydrophilic material, on a substrate; selectively forming a nano-crystalline film layer on the buffer layer or the substrate and performing a thermal treatment on the nano-crystalline film layer; forming source and drain electrodes on the nano-crystalline film layer; forming a gate insulating layer on the nano-crystalline film layer having the source and drain electrodes; and forming a top-gate electrode on the gate insulating layer.
The substrate may be any one selected from a silicon substrate, a glass substrate, and a plastic substrate.
The substrate may be made of any one selected from polyethylene terephthalate (PET), polyethylenenaphthalate (PEN), polycarbonate (PC), and polyethylenesulfone (PES).
The buffer layer may be made of a hydrophilic inorganic or organic material.
The hydrophilic inorganic material may be any one selected from A1203, Hf02, Ta205, La203, and Si02.
The hydrophilic inorganic material may be subjected to an atomic layer deposition (ALD) method or a sputtering method, to form the buffer layer.
The hydrophilic organic material may be any one selected from AIDCN, polyaniline, Cd-AA, PVP, PVA, and PEDOT.
The hydrophilic organic material may be subjected to an ultraviolet (UV) process using 03 as a reactive gas or a plasma process using 02 as a reactive gas, to form a hydrophilic surface.
The hydrophilic organic material may be subjected to any one selected from a spin-coating method, a spraying method, and a printing method, to form the buffer layer.
The buffer layer may have a thickness within a range of 2 nm to 20 nm.
The buffer layer may be deposited on the substrate at a temperature of 100-150 degrees centigrade.
The selective formation and thermal treatment of the nano-crystalline film layer may comprise: forming a selective active layer on the buffer layer by selectively exposing a partial region of the buffer layer to ultraviolet rays by use of a metal mask or a photoresist for a photolithography process; exposing the exposed region of the buffer layer to 03, to provide the buffer layer with hydrophilicity; forming a nano-crystalline film over the selective active layer and the buffer layer; patterning the nano-crystalline film by removing the masking layer (photoresist) via a lift-off process, to form the nano-crystalline film layer; and performing the thermal treatment on the nano-crystalline film layer.
The formation of the nano-crystalline film may comprise: preparing a nano-crystalline solution by distributing nano-crystals into a solvent; mixing the nano-crystalline solution with a precipitant; and coating the nano-crystalline solution containing the precipitant over the substrate.
The nano-crystals may be any one selected from the group consisting of HgTe, HgSe, HgS, CdTe, CdSe, CdS, ZnTe, ZnSe, ZnS, PbTe, PbSe, PbS, and ZnO.
The coating of the nano-crystalline solution containing the precipitant over the substrate may be performed by use of any one selected from a spin-coating method, a deep-coating method, a stamping method, a spraying method, and a printing method.
The thermal treatment may be performed at a temperature of 100-185 degrees centigrade for 10-200 minutes.
The formation of the gate insulating layer may be performed by forming a high dielectric constant insulator on the nano-crystalline film layer, and the insulator is an inorganic material selected from A1203, Hf02, Ta205, La203, and Si02 or an organic material selected from AIDCN, polyaniline, Cd-AA, PVP, PVA, and PEDOT.
The insulator may be deposited on the nano-crystalline film layer at a substrate temperature within a range of 100-185 degrees centigrade, and a thickness of the gate insulating layer is within a range of 10 nm to 500 nm.
In accordance with another aspect of the present invention, there is provided a method for fabricating a logic circuit, made by intergrating the thin-film transitor manufactured by the method according to any one claims 1 to 18 In accordance with another aspect of the present invention, there is provided a thin-film transistor using a nano-crystalline thin-film as an active layer comprising: a substrate; a buffer layer formed on the substrate by use of a hydrophilic material; a thermally treated nano-crystalline film layer formed on the buffer layer; source and drain electrodes formed on the nano-crystalline film layer; a gate insulating layer formed on the nano-crystalline film layer having the source and drain electrodes; and a top-gate electrode formed on the gate insulating layer.
The top-gate thin-film transistor may be fabricated according to any one of the said method.
In accordance with another aspect of the present invention, there is provided a logic circuit, wherein includes the thin-film transistors intergrated and manufactured according to any one of the said method.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIGS. 1A to 1E are sectional views illustrating the sequential fabrication processes of a top-gate thin-film transistor using nano-crystals according to the present invention; FIG. 2 is a graph illustrating the magnitude of a current measured after performing a thermal treatment on a HgTe nano-crystalline thin-film layer at 150 degrees centigrade for 180 minutes; FIG. 3 is an optical microscopic image illustrating a top surface of the top-gate thin-film transistor fabricated via the processes shown in FIGS. lA to lE; FIG. 4A is a graph illustrating the dependency of a drain current D on a voltage VDS applied to drain/source electrodes when a discontinuous voltage VG is applied to a gate electrode; FIG. 4B is a graph illustrating a drain current depending on a gate voltage; FIG. 5 is a photograph illustrating a top-gate transistor fabricated by use of a glass substrate according to an embodiment of the present invention; FIG. 6A is a graph illustrating the dependency of a drain current D on a voltage V applied to drain/source electrodes when a discontinuous voltage VG is applied to a gate electrode; FIG. 6B is a graph illustrating a drain current depending on a gate voltage; FIG. 7 is a photograph illustrating a top-gate transistor fabricated by use of a transparent plastic substrate according to another embodiment of the present invention; FIG. 8 is a photograph illustrating the spherical bending property of the top-gate transistor fabricated by use of the transparent plastic substrate as shown in FIG. 7; FIGS. 9A and 9B are graphs illustrating properties of the top-gate transistor fabricated by use of the transparent plastic substrate; FIG. 10 is a photograph illustrating an inverter logic circuit using, as an unit element, the top-gate transistor fabricated by use of the transparent plastic substrate; and FIG. 11 is a graph illustrating the properties of the inverter logic circuit according to an active resistor value of the logic circuit using the top-gate transistor fabricated by use of the transparent plastic substrate.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Now, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIGS. 1A to 1E are sectional views illustrating the sequential fabrication processes of a thin-film transistor and a logic circuit using a nano-crystalline thin-film as an active layer according to the present invention.
First, as shown in FIG. 1A, a buffer layer 15 is formed on a glass, silicon or plastic substrate 10 by use of a hydrophilic material. It is noted that the substrate can be selected from a variety of substrates so long as they have a flexibility. For example, a flexible plastic substrate may be used.
Since the thin-film transistor and the logic circuit according to the present invention can be fabricated via low-temperature processes, the use of the plastic substrate can be allowed. When the flexible plastic substrate is used, specifically, the plastic substrate may be made of any one of polyethylene terephthalate (PET), polyethylenenaphthalate (PEN), polycarbonate (PC), polyethylenesulfone (PES), and the like.
The buffer layer 15, to be formed on the glass, silicon, or plastic substrate 10, is made of a hydrophilic inorganic or hydrophilic organic material. That is, the buffer layer 15 can be made of an organic or inorganic material, and preferably, be made of a hydrophilic material.
When the buffer layer 15 is made of a hydrophilic inorganic material, it can be made of any one of A1203, Hf02, Ta205, La203, Si02, and the like. The hydrophilic inorganic material, more particularly, A1203 can be deposited by various methods. In the present invention, any one of hyctrophilic inorganic materials including, for example, A1203, Hf02, Ta205, La203, and S102 is deposited on the glass or plastic substrate 10 by use of an atomic layer deposition (ALD) method or sputtering method, to form the buffer layer 15.
On the other hand, when the buffer layer 15 is made of a hydrophilic organic material, it can be made of any one of AIDCN, polyaniline, Cd-AA, PVP, PVA, PEDOT, and the like. It is noted that these organic materials must be processed to have hydrophilicity. For this, the above mentioned organic materials must be subjected to an ultraviolet (UV) process using 03 as a reactive gas or a plasma process using 02 as a reactive gas, to provide the buffer layer 15 with a hydrophilic surface.
The hydrophilic organic materials can be deposited by use of various methods. In the present invention, the hydrophilic organic materials can be deposited by use of any one of a spin-coating method, a spraying method, and a printing method.
The above described buffer layer 15 may be configured to have various thicknesses. In the present invention, the buffer layer 15 is preferably deposited to have a thickness within a range of 2-20 nm. When the buffer layer 15 has the above described range of thickness, the buffer layer 15 can be deposited on the substrate 10 at a relatively low temperature within a range of 100-150 degrees centigrade. The formation of the buffer layer 15 on the glass or plastic substrate 10 has the following effects.
In consideration of the fact that a nano-crystalline solution, which will be described hereinafter, has hydrophilicity, the use of the hydrophilic buffer layer 15 is effective to facilitate the deposition of a nano-crystalline film on the glass, silicon or plastic substrate 10. For this reason, it is advantageous to form the buffer layer 15 on the glass, silicon or plastic substrate 10.
Now, a process for forming a nano-crystalline film on the buffer layer 15 will be described in detail.
As shown in FIG. 1B, a masking layer 17 is formed on the buffer layer 15, to form a selective active layer.
The masking layer 17 may be a metal mask or a photoresist for a photolithography process.
When the buffer layer 15 is made of any one of organic materials including, for example, AIDCN, polyaniline, Cd-AA, PVP, PVA, and PEDOT, only an exposed region of the buffer layer 15 not covered by the masking layer 17 is processed to form a hydrophilic surface by the following UV process.
Then, to form a nano-crystalline film, a nano-crystalline solution is first prepared by distributing desired nano-crystals into a solvent. In this case, the density of nano-crystals distributed in the solvent is preferably within a range of 0.01 mg/pi to 1 mgI.ii. After preparing the nano-crystalline solution, the nano-crystalline solution is mixed with a precipitant such as 2-propanol. In this case, the volume ratio of the mixture is 1:100 to 1:1. Then, the resulting nano-crystalline solution containing the precipitant is coated over the buffer layer 15 and the masking layer 17, to form a nano-crystalline film over the buffer layer 15 and the masking layer 17.
It is noted that although various nano-crystals can be used in the above described process, the present invention uses any one selected from semiconductor nano-crystals including HgTe, HgSe, HgS, CdTer CdSe, CdS, ZnTe, ZnSe, ZnS, PbTe, PbSe, PbS, ZnO, and the like.
Here, the nano-crystalline solution containing the precipitant can be coated over the buffer layer 15 and the masking layer 17 by use of any one of a spin-coating method, a deep-coating method, a stamping method, a spraying method, a printing method, and other solution processing techniques, to form the nano-crystalline film over the buffer layer 15 and the masking layer 17.
Thereafter, the masking layer 17 is removed by a lift-off method, and simultaneously, nano-crystals on the top of the masking layer 17 are removed. Thereby, a nano-crystalline film layer 20 is patterned on only a region of the buffer layer 15 except for the masking layer 17.
After forming the nano-crystalline film layer 20 on the buffer layer 15 by the above described process, the nano-crystalline film layer 20 is subjected to a thermal treatment at a desired temperature. The thermal treatment is performed, depending on the kind of nano-crystals, at 100-185 degrees centigrade for 10-20 minutes. It is noted that the thermal treatment can be performed at the above described low temperature range because currently-used glass or plastic substrates (more particularly, a PES substrate) have a fusion point of 185 degrees centigrade.
The thermal treatment has the roles of improving the crystallinity and mobility of the nano-crystalline film and improving the adhesive force of the nano-crystalline film to prevent the nano-crystalline film from being separated from the substrate due to a deterioration in the adhesive force between the nano-crystalline film and the substrate during a photolithography process.
FIG. 2 is a graph illustrating the magnitude of a current measured after performing a thermal treatment on a HgTe nano-crystalline film layer at 150 degrees centigrade for 180 minutes. As can be understood from FIG. 2 comparing a curve (designated by reference character "a") when no thermal treatment is performed with a curve (designated by reference character "b") when a thermal treatment is performed, the magnitude of a current when a thermal treatment is performed increases more than iO times. The nano-crystalline film layer 20, having passed through the thermal treatment, can operate as an active layer.
After performing the thermal treatment on the nano-crystalline film layer 20 as described above, as shown in FIG. 1D, source electrodes 31 and drain electrodes 32 are formed on the nano-crystalline film layer 20 by an electronic beam or photolithography method or by use of a metal mask.
After completing the formation of the source electrodes 31 and the drain electrodes 32, as shown in FIG. 1E, a gate insulating layer 40 is formed on the nano-crystalline film layer 20 having the source and drain electrode 31 and 32, The gate insulating layer 40 is formed by depositing a high dielectric constant insulator on the nano-crystalline film layer 20. Thereafter, gate electrodes 50 are formed on the gate insulating layer 40 by an electronic beam or photolithography method or by use of a metal mask.
When the gate insulating layer 40 is formed by depositing the high dielectric constant insulator as described above, the insulator is preferably any one selected from inorganic materials including, for example, A1203, Hf02, Ta205, La203, and Si02, or any one selected from organic materials including, for example, AIDCN, polyaniline, Cd-AA, PVP, PVA, and PEDOT.
When the above described insulator is deposited on the nano-crystalline film layer, the temperature of the substrate is preferably more than a normal temperature (more than 100 degrees centigrade) and less than 185 degrees centigrade. Also, a thickness of the gate insulating layer is preferably within a range of 10 nm to 500 nm.
FIG. 3 is an optical microscopic image illustrating a top surface of the top-gate thin-film transistor fabricated via the above described processes. FIG. 4A illustrates the dependency of a drain current I on a voltage VDS applied to drain and source electrodes when a discontinuous voltage VG is applied to a gate electrode.
From the fact that the smaller the gate voltage, the greater the drain current, it can be appreciated that the illustrated transistor is a p-channel transistor.
FIG. 4B illustrates a drain current depending on a gate voltage. When the voltage V applied to the drain and source electrode is fixed at a value of 1OV, the field-effect mobility calculated by use of a gradient of a curve represented by the relationship of / II1 to VG is 2.38 cm2/Vs.
FIG. 5 is a photograph illustrating a top-gate transistor fabricated by use of a glass substrate according to an embodiment of the present invention. FIG. 6A is a graph illustrating the dependency of a drain current I on a voltage V9 applied to drain and source electrodes when a discontinuous voltage VG is applied to a gate electrode.
FIG. 6B illustrates a drain current depending on a gate voltage. When the voltage VDS applied to the drain and source electrode is fixed at a value of 1OV, the field-effect mobility measured by use of a gradient of a curve represented by the relationship of -I lID1 to VG is 1. 06 cm2/V5. FIG. 7 is a photograph illustrating a top-gate transistor fabricated by use of a transparent plastic substrate according to another embodiment of the present invention. FIG. 8 is a photograph illustrating the spherical bending property of the top-gate transistor fabricated by use of the transparent plastic substrate as shown in FIG. 7.
FIGS. 9A and 9B illustrate the properties of the top-gate transistor fabricated by use of the plastic substrate according to the present invention. Here, in the fabrication of the top-gate transistor, a HgTe nano-crystalline film was used to form an active layer, and a A1203 gate insulating layer was deposited to have a thickness of 60 nm by an ALD method. In this case, a distance between source and drain electrodes, i.e. a channel length was 10 tm, and a channel width was 1,000 tm.
FIG. 10 is a photograph illustrating an inverter logic circuit using, as a unit element, the thin-film transistor fabricated by use of the transparent plastic substrate and the nano-crystalline thin-film as an active layer according to the embodiment of the present invention. FIG. 11 illustrates the properties of the inverter logic circuit when an active resistor value of the logic circuit using the top-gate thin-film transistor fabricated by use of the plastic substrate according to the present invention is within a range of -15V to +15V.
It is noted that no transistor fabricated by performing a nano-crystal solution process on a plastic substrate has not been reported yet and the present invention is the first attempt.
As apparent from the above description, a thin-film transistor and a logic circuit using a nano-crystalline thin-film as an active layer and a method for fabricating the same according to the present invention provide the following several effects.
Firstly, as a result of depositing a hydrophilic buffer layer on a glass or plastic substrate, the present invention can assure easy formation of a nano-crystalline film on the substrate. Further, by adopting the nano-crystalline film, which is formed on the glass or plastic substrate and serves as an active layer, and a top-gate insulating layer, a top-gate thin-film transistor capable of being operated at low gate voltages can be accomplished.
Secondly, according to the present invention, fabrication processes of the thin-film transistor can be performed at low temperatures. Such low-temperature fabrication enables the use of glass or plastic substrates as well as a silicon substrate, and the implementation of solution processes, resulting in a reduction in the overall fabrication costs of the thin-film transistor.
Thirdly, when using the glass and plastic substrates, a transparent flexible thin-film transistor can be fabricated. In particular, since the use of glass and plastic substrates allow the fabrication of a large-area transistor and the deposition of a nano-crystalline layer, it is unnecessary to use very expensive high-vacuum deposition equipment. Accordingly, the present invention can reduce the overall fabrication costs and
achieve outstanding industrial applicability.
Fourthly, by fabricating the thin-film transistor and the logic circuit by use of an inorganic semiconductor nano-crystalline thin-film as an active layer, the present invention can achieve advantages of a high charge mobility, chemical stability, thermal durability, and resistance to high voltages.
Fifthly, differently from conventional semiconductor thin-film transistors formed on silicon, glass, and plastic substrates and using crystalloid or polycrystalline channels, according to a characteristic advantage of the present invention, semiconductor thin-film transistor channels, which are formed on the plastic substrate by use of semiconductor nano-crystals, are made of substantially mono-crystal materials, and have a high charge mobility.
Sixthly, with the separation of the active layer, the present invention can achieve an outstanding effect of forming a field-effect device and an inverter logic device on a single flexible substrate by use of various kinds of materials and various kinds of semiconductor nano-crystals.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims (22)

  1. WHAT IS CLAIMED IS: 1. A method for fabricating a thin-film transistor using a nano-crystalline thin-film as an active layer, comprising: forming a buffer layer, made of a hydrophilic material, on a substrate; selectively forming a nano-crystalline film layer on the buffer layer or the substrate and performing a thermal treatment on the nano-crystalline film layer; forming source and drain electrodes on the nano-crystalline film layer; forming a gate insulating layer on the nano-crystalline film layer having the source and drain electrodes; and forming a top-gate electrode on the gate insulating layer.
  2. 2. The method according to claim 1, wherein the substrate is any one selected from a silicon substrate, a glass substrate, and a plastic substrate.
  3. 3. The method according to claim 2, wherein the substrate is made of any one selected from polyethylene terephthalate (PET), polyethylenenaphthalate (PEN), polycarbonate (PC), and polyethylenesulfone (PES).
  4. 4. The method according to claim 1, wherein the buffer layer is made of a hydrophilic inorganic or organic material.
  5. 5. The method according to claim 4, wherein the hydrophilic inorganic material is any one selected from Al7O, Hf02, Ta205, La2O, and Si02.
  6. 6. The method according to claim 5, wherein the hydrophilic inorganic material is subjected to an atomic layer deposition (ALD) method or a sputtering method, to form the buffer layer.
  7. 7. The method according to claim 4, wherein the hydrophilic organic material is any one selected from AIDCN, polyanhline, Cd-AA, PVP, PVA, and PEDOT.
  8. 8. The method according to claim 7, wherein the hydrophilic organic material is subjected to an ultraviolet (UV) process using 03 as a reactive gas or a plasma process using 02 as a reactive gas, to form a hydrophilic surface.
  9. 9. The method according to claim 8, wherein the hydrophilic organic material is subjected to any one selected from a spin-coating method, a spraying method, and a printing method, to form the buffer layer.
  10. 10. The method according to claim 1, wherein the buffer layer has a thickness within a range of 2 nm to 20 nm.
  11. 11. The method according to claim 1, wherein the buffer layer is deposited on the substrate at a temperature of 100-150 degrees centigrade.
  12. 12. The method according to claim 1, wherein the selective formation and thermal treatment of the nano-crystalline film layer comprises: forming a selective active layer on the buffer layer by selectively exposing a partial region of the buffer layer to ultraviolet rays by use of a metal mask or a photoresist for a photolithography process; exposing the exposed region of the buffer layer to 03, to provide the buffer layer with hydrophilicity; forming a nano-crystalline film over the selective active layer and the buffer layer; patterning the nano-crystalline film by removing the selective active layer (photoresist) via a lift-off process, to form the nano-crystalline film layer; and performing the thermal treatment on the nano-crystalline film layer.
  13. 13. The method according to claim 12, wherein the formation of the nano-crystalline film comprises: preparing a nano-crystalline solution by distributing nano-crystals into a solvent; mixing the nano-crystalline solution with a precipitant; and coating the nano-crystalline solution containing the precipitant over the substrate.
  14. 14. The method according to claim 13, wherein the nano-crystals are any one selected from the group consisting of HgTe, HgSe, HgS, CdTe, CdSe, CdS, ZnTe, ZnSe, ZnS, PbTe, PbSe, PbS, and ZnO.
  15. 15. The method according to claim 13, wherein the coating of the nano-crystalline solution containing the precipitant over the substrate is performed by use of any one selected from a spin-coating method, a deep-coating method, a stamping method, a spraying method, and a printing method.
  16. 16. The method according to claim 1, wherein the thermal treatment is performed at a temperature of 100-185 degrees centigrade for 10-200 minutes.
  17. 17. The method according to claim 1, wherein the formation of the gate insulating layer is performed by forming a high dielectric constant insulator on the nano-crystalline film layer, and the insulator is an inorganic material selected from A1203, Hf02, Ta405, La203, and Si02 or an organic material selected from AIDCN, polyaniline, Cd-A.A, PVP, PVA, and PEDOT.
  18. 18. The method according to claim 17, wherein the insulator is deposited on the nano-crystalline film layer at a substrate temperature within a range of lOOl85 degrees centigrade, and a thickness of the gate insulating layer is within a range of 10 nm to 500 nm.
  19. 19. A method for fabricating a logic circuit, is made by intergrating the thin-film transitor manufactured by the method according to any one claims 1 to 18.
  20. 20. A thin-film transistor using a nano-crystalline thin-film as an active layer comprising: a substrate; a buffer layer formed on the substrate by use of a hydrophilic material; a thermally treated nano-crystalline film layer formed on the buffer layer; source and drain electrodes formed on the nano-crystalline film layer; a gate insulating layer formed on the nano-crystalline film layer having the source and drain electrodes; and a top-gate electrode formed on the gate insulating layer.
  21. 21. The thin-film transistor according to claim 19, wherein the top-gate thin-film transistor are fabricated by the method according to any one of claims 1 to 18.
  22. 22. The logic circuit, wherein includes the thin-film transistor according to claim 20 or 21.
GB0802637A 2008-02-13 2008-02-13 Thin-film transistor using nano-crystalline thin-film as active layer, and method for fabricating the same Withdrawn GB2457872A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001046987A2 (en) * 1999-12-21 2001-06-28 Plastic Logic Limited Inkjet-fabricated integrated circuits
WO2007058231A1 (en) * 2005-11-18 2007-05-24 Idemitsu Kosan Co., Ltd. Semiconductor thin film, method for producing same, thin film transistor and active-matrix-driven display panel
US20070160747A1 (en) * 2006-01-12 2007-07-12 International Business Machines Corporation Method for fabricating an inorganic nanocomposite
US20070228376A1 (en) * 2006-03-30 2007-10-04 Korea University Industrial & Academic Collaboration Foundation Top-gate thin-film transistors using nanoparticles and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001046987A2 (en) * 1999-12-21 2001-06-28 Plastic Logic Limited Inkjet-fabricated integrated circuits
WO2007058231A1 (en) * 2005-11-18 2007-05-24 Idemitsu Kosan Co., Ltd. Semiconductor thin film, method for producing same, thin film transistor and active-matrix-driven display panel
US20070160747A1 (en) * 2006-01-12 2007-07-12 International Business Machines Corporation Method for fabricating an inorganic nanocomposite
US20070228376A1 (en) * 2006-03-30 2007-10-04 Korea University Industrial & Academic Collaboration Foundation Top-gate thin-film transistors using nanoparticles and method of manufacturing the same

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