GB2456924B - Method, apparatus, computer program product and data processing program of controlling cache usage in a computer system - Google Patents

Method, apparatus, computer program product and data processing program of controlling cache usage in a computer system

Info

Publication number
GB2456924B
GB2456924B GB0904430.6A GB0904430A GB2456924B GB 2456924 B GB2456924 B GB 2456924B GB 0904430 A GB0904430 A GB 0904430A GB 2456924 B GB2456924 B GB 2456924B
Authority
GB
United Kingdom
Prior art keywords
data processing
computer system
computer
cache usage
program product
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0904430.6A
Other versions
GB2456924A (en
GB0904430D0 (en
Inventor
Elmar Zipp
Eberhard Pasch
Markus Nosse
Achim Haessler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB0904430D0 publication Critical patent/GB0904430D0/en
Publication of GB2456924A publication Critical patent/GB2456924A/en
Application granted granted Critical
Publication of GB2456924B publication Critical patent/GB2456924B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
GB0904430.6A 2008-04-28 2009-03-16 Method, apparatus, computer program product and data processing program of controlling cache usage in a computer system Active GB2456924B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP08155292 2008-04-28

Publications (3)

Publication Number Publication Date
GB0904430D0 GB0904430D0 (en) 2009-04-29
GB2456924A GB2456924A (en) 2009-08-05
GB2456924B true GB2456924B (en) 2012-03-07

Family

ID=40637362

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0904430.6A Active GB2456924B (en) 2008-04-28 2009-03-16 Method, apparatus, computer program product and data processing program of controlling cache usage in a computer system

Country Status (1)

Country Link
GB (1) GB2456924B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6000014A (en) * 1997-04-14 1999-12-07 International Business Machines Corporation Software-managed programmable congruence class caching mechanism
US6016529A (en) * 1997-11-26 2000-01-18 Digital Equipment Corporation Memory allocation technique for maintaining an even distribution of cache page addresses within a data structure
US20040064651A1 (en) * 2002-09-30 2004-04-01 Patrick Conway Method and apparatus for reducing overhead in a data processing system with a cache
US20050091466A1 (en) * 2003-10-27 2005-04-28 Larson Douglas V. Method and program product for avoiding cache congestion by offsetting addresses while allocating memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6000014A (en) * 1997-04-14 1999-12-07 International Business Machines Corporation Software-managed programmable congruence class caching mechanism
US6016529A (en) * 1997-11-26 2000-01-18 Digital Equipment Corporation Memory allocation technique for maintaining an even distribution of cache page addresses within a data structure
US20040064651A1 (en) * 2002-09-30 2004-04-01 Patrick Conway Method and apparatus for reducing overhead in a data processing system with a cache
US20050091466A1 (en) * 2003-10-27 2005-04-28 Larson Douglas V. Method and program product for avoiding cache congestion by offsetting addresses while allocating memory

Also Published As

Publication number Publication date
GB2456924A (en) 2009-08-05
GB0904430D0 (en) 2009-04-29

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Legal Events

Date Code Title Description
746 Register noted 'licences of right' (sect. 46/1977)

Effective date: 20130402