GB2456891B - Method to update corrupted local working registers in a multi-staged pipelined execution unit - Google Patents
Method to update corrupted local working registers in a multi-staged pipelined execution unitInfo
- Publication number
- GB2456891B GB2456891B GB0823186.2A GB0823186A GB2456891B GB 2456891 B GB2456891 B GB 2456891B GB 0823186 A GB0823186 A GB 0823186A GB 2456891 B GB2456891 B GB 2456891B
- Authority
- GB
- United Kingdom
- Prior art keywords
- update
- execution unit
- working registers
- local working
- pipelined execution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08150812 | 2008-01-30 |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0823186D0 GB0823186D0 (en) | 2009-01-28 |
GB2456891A GB2456891A (en) | 2009-08-05 |
GB2456891B true GB2456891B (en) | 2012-02-01 |
Family
ID=40343893
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0823186.2A Active GB2456891B (en) | 2008-01-30 | 2008-12-19 | Method to update corrupted local working registers in a multi-staged pipelined execution unit |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2456891B (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070043934A1 (en) * | 2005-08-22 | 2007-02-22 | Intel Corporation | Early misprediction recovery through periodic checkpoints |
US7200742B2 (en) * | 2005-02-10 | 2007-04-03 | International Business Machines Corporation | System and method for creating precise exceptions |
US20080016325A1 (en) * | 2006-07-12 | 2008-01-17 | Laudon James P | Using windowed register file to checkpoint register state |
US7475230B2 (en) * | 2003-05-16 | 2009-01-06 | Sun Microsystems, Inc. | Method and apparatus for performing register file checkpointing to support speculative execution within a processor |
-
2008
- 2008-12-19 GB GB0823186.2A patent/GB2456891B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7475230B2 (en) * | 2003-05-16 | 2009-01-06 | Sun Microsystems, Inc. | Method and apparatus for performing register file checkpointing to support speculative execution within a processor |
US7200742B2 (en) * | 2005-02-10 | 2007-04-03 | International Business Machines Corporation | System and method for creating precise exceptions |
US20070043934A1 (en) * | 2005-08-22 | 2007-02-22 | Intel Corporation | Early misprediction recovery through periodic checkpoints |
US20080016325A1 (en) * | 2006-07-12 | 2008-01-17 | Laudon James P | Using windowed register file to checkpoint register state |
Also Published As
Publication number | Publication date |
---|---|
GB2456891A (en) | 2009-08-05 |
GB0823186D0 (en) | 2009-01-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
746 | Register noted 'licences of right' (sect. 46/1977) |
Effective date: 20130107 |