GB2456640B - Memory device - Google Patents

Memory device

Info

Publication number
GB2456640B
GB2456640B GB0724420A GB0724420A GB2456640B GB 2456640 B GB2456640 B GB 2456640B GB 0724420 A GB0724420 A GB 0724420A GB 0724420 A GB0724420 A GB 0724420A GB 2456640 B GB2456640 B GB 2456640B
Authority
GB
United Kingdom
Prior art keywords
memory device
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0724420A
Other versions
GB0724420D0 (en
GB2456640A (en
Inventor
Stephen Felix
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Icera LLC
Original Assignee
Icera LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icera LLC filed Critical Icera LLC
Priority to GB0724420A priority Critical patent/GB2456640B/en
Publication of GB0724420D0 publication Critical patent/GB0724420D0/en
Publication of GB2456640A publication Critical patent/GB2456640A/en
Application granted granted Critical
Publication of GB2456640B publication Critical patent/GB2456640B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
GB0724420A 2007-12-14 2007-12-14 Memory device Active GB2456640B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0724420A GB2456640B (en) 2007-12-14 2007-12-14 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0724420A GB2456640B (en) 2007-12-14 2007-12-14 Memory device

Publications (3)

Publication Number Publication Date
GB0724420D0 GB0724420D0 (en) 2008-01-30
GB2456640A GB2456640A (en) 2009-07-29
GB2456640B true GB2456640B (en) 2011-09-21

Family

ID=39048109

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0724420A Active GB2456640B (en) 2007-12-14 2007-12-14 Memory device

Country Status (1)

Country Link
GB (1) GB2456640B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9245595B2 (en) 2013-12-20 2016-01-26 Nvidia Corporation System and method for performing SRAM access assists using VSS boost

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060262628A1 (en) * 2005-05-23 2006-11-23 Renesas Technology Corp. Semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060262628A1 (en) * 2005-05-23 2006-11-23 Renesas Technology Corp. Semiconductor memory device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique" M Yamaoka et al, IEEE J Solid State Circuits, Vol 41, No 3, Mar 2006, pages 705-711 *

Also Published As

Publication number Publication date
GB0724420D0 (en) 2008-01-30
GB2456640A (en) 2009-07-29

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20120913 AND 20120919

732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20130516 AND 20130522