GB2456202A

GB2456202A - Clock gating system for macro circuits on a semiconductor chip

Info

Publication number: GB2456202A
Application number: GB0821970A
Authority: GB
Inventors: Guenter Gerwig; Frank Lehnert; Ulrich Mayer
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2008-01-09
Filing date: 2008-12-02
Publication date: 2009-07-08
Anticipated expiration: 2028-12-02
Also published as: GB0821970D0; GB2456202B

Abstract

A digital circuit on a semiconductor chip comprises a plurality of macro circuits (10, 12, 14) and a clock gating system (50, 52, 54) for disabling the clock signal for at least one single macro circuit (12) to reduce power consumption. The circuit comprises a hierarchical structure with at least two clock gating levels, and each macro circuit (10, 12, 14) is associated with one of the levels. A macro control circuit (10) is provided on a top clock gating level and controls the clock gating of at least one other macro circuit (12) on one or more lower clock gating levels, wherein all external signals used to control the clock gating are connected to the control circuit (10). The method distinguishes between two clock gating granularities. A coarse-grain gating operates on the boundaries of the macro circuits, and a fine-grain gating operates mainly on dataflow storage elements within the macro circuits.

Description

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DESCRIPTION

A digital circuit on a semiconductor chip with a plurality of macro circuits and a clock gating system

Background of the invention

I. Field of the invention

The present invention relates to a digital circuit on a semiconductor chip with a plurality of macro circuits and a clock gating system. Further, the present invention relates to a method for controlling the clock gating system of the digital circuit on the semiconductor chip.

2. Description of the related art

Hierarchical designs of complex semiconductor chips often include clock gating mechanisms in order to reduce the power consumption. The clock gating mechanism requires a control concept for managing the clock gating within the hierarchical structure of the chip design. The clock gating disables the clock of a single circuit within the chip design, when said single circuit is actually not used.

The article "Low Power Design of 90-mm SuperH Processor Core" by Tetsuya Yamada et al. (Proceeding of the 2005 International Conference on Computer Design) describes in detail the principle of the clock gating mechanism.

In the hierarchical design of the semiconductor chip the scope of the clock gating is limited to macro circuits. Thus, the complete macro Circuit is either clocked or not clocked. The control logic circuit that manages the clock gating resides normally in the macro circuit itself. Functional interactions between different macro circuits can often not be detected. In r other cases the detection requires a complex interface structure between Lhe different macro circuits.

This means that many times a macro circuit is clocked although where is no functional need for doing this due to missing information located in other macro circuits. If signals used to control the clock gating are coming from outside they often must he buffered at first. This means that at least a couple of storage elements must be clocked in every cycle in order to capture the incoming signals and in order to control the clock gating. Thus, the clock gating cannot be applied to all storage elements of the macro.

Object of the invention It is an object of the present invention to provide a digital circuit on a semiconductor chip with a plurality of macro circuits and a clock gating system, which allows reduced power consumption.

Summary of the invention

The above object is achieved by a method as laid out in the independent claims. Further advantageous embodiments of the present invention are described in the dependent claims and are

taught in the description below.

The core idea of the invention is to provide a clock gating control mechanism within a hierarchical design of a digital circuit on a semiconductor chip. The digital circuit is subdivided into a plurality of macro circuits. The scheme of said hierarchical design includes at least two clock gating levels. Each macro circuit is associated with one of the clock gating levels. The main control of the clock gating is located in a single macro control circuit on a top clock gating level.

The macro control circuit is provided to control the clock gating of at least one other macro circuit on one oi more lower clock gating levels. Further, the macro circuit on a second or lower clock gating level may he provided to control other macro circuits on one or more lower clock gating levels or on the same clock gating level. All external signals used to control the clock gating are connected to the macro control circuit.

The clock gatirig implementation according to the present invention distinguishes between two clock gating granularities.

A coarse grain clock gating mechanism is working on the boundaries of the macro circuits. A fine grain clock gating mechanism is working mainly on datafiow storage elements within the macro circuit.

The macro control circuit itself is not clock gated in order to capture all asynchronous events used for managing and controlling the clock gating scheme. The macro control circuit controls only the coarse grain clock gating granularity, meaning that the clock is either enabled or disabled for macros but it does not control dataflow registers within a macro. Furthermore the chosen structure enables a macro that is itself controlled by the macro control circuit to control the coarse grain clock gating of another macro. In this case the detailed information when clock gating for specific macros should be applied are not available in the main clock gating control macro itself. Thus these macros are controlled by the appropriate macros containing the necessary information in order to make clock gating more efficient.

Depending on the logic structure of the digital circuit it is generally possible to define a number of clock gating levels in the hierarchy structure. The overall clock gating is controlled by a dedicated macro circuit which has all information necessary to control the main clock domain of the macro circuits on the

I

first clock gating level. In general by using such a structure the main clock domain of a macro circuit on the clock gating level n is controlled by a macro circuit on the clock gating level n-i. A macro circuit on the clock gating level n=l is always controlled by the global clock gating control macro circuit.

The haerarchical clock gating structure of the present invention allows saving power. The key to improve the power saving efficiency is the selection of a structure where clock gating is controlled by one instance having all the necessary information available to effectively manage clock gating on a given scope.

This principle is reflected in the chosen clock gating hierarchy. The overall control is concentrated at one place and not spread out over the different macro circuits.

Further, by using this structure it is possible to disable clock gating for a whole macro circuit, if it is functionally not needed. This is also true for the next hierarchy clock gating level where the internal clock gating of the macro circuit is efficiently managed by the macro circuit itself, since al]. the necessary information are available at this scope. This structure allows a more precise clock gating. Thus, the macro circuits are clocked only then, if they are functional used.

Brief description of the drawings

The above as well as additional objectives, features and advantages of the present invention will be apparent in the

following detailed written description.

The novel and inventive features believed characteristics of the invention are set forth in the appended claims. The invention itself, their preferred embodiments and advantages thereof will be best understood by reference to the following detailed description of preferred embodiments in conjunction with the accompanied drawings, wherein: Fig. 1 illustrates a schematic diagram of a clock gating implementation within a plurality of macro circuits according to an embodiment of the present invention, Fig. 2 illustrates a schematic diagram of an external coarse grain clock gating according to a further embodiment of the present invention, Fig. 3 illustrates a schematic diagram of a clock gating control with a feedback path according to a further embodiment of the present invention, Fig. 4 illustrates a schematic diagram of an internal fine grain clock gating according to a further embodiment of the present invention, Fig. 5 illustrates a schematic diagram of an external fine grain clock gating according to a further embodiment of the present invention, and Fig. 6 illustrates a schematic diagram of a clock gating within a hierarchical structure according to a further embodiment of the present invention.

Detailed description of the invention

Fig. 1 illustrates a schematic diagram of a clock gating implementation within a structure of a plurality of macro circuits according to the preferred embodiment of the present invention. : .

An ISR (input status register) circuit 10 is the centre macro circuit within said structure. The ISR circuit 10 is connected to an RIQ (read interlock queue) circuit 12 via an RIQ power line 32 and an RIQ active line 34. The ISR circuit 10 is connected to an OPX (output muxing) circuit 14 via an OPX power line 36. The ISP. circuit 10 is connected to a WQC (write queue control) circuit 20 via a WQC power line 38 and a WQC active line 40.

The ISP. circuit 10 is connected to a CSH (checkpoint status register high part) circuit 22 via a CSH power line 42. The ISR circuit 10 is connected to a CSL (checkpoint status register low part) circuit 24 via a CSL power line 44. The TSR circuit 10 is connected to an IXR (FXU input register) circuit 26 via an IXR power line 46. At last, the ISR circuit 10 is connected to an IPR (BFU input register) circuit 28 via an IPR power line 48. In this example the ISR circuit 10 acts as a macro control circuit.

The main control of the clock gating is located in the ISR circuit 10. The ISR circuit 10 controls the other macro circuits. All external signals used to control the clock gating are connected to the ISP. circuit 10.

The present invention is not restricted on such kind of macro circuits as described above. The digital circuit according to the present invention may by be applied to arbitrary digital macro circuits.

The clock gating implementation according to the present invention distinguishes between two clock gating granularities.

A coarse grain clock gating mechanism is working on boundaries of the macro circuits. A fine grain clock gating mechanism is working mainly on dataf low storage elements within the macro circuit. In order to control the clock gating a hierarchical : design approach has been used. The scheme of the hierarchical design consists of at least two hierarchy clock gating levels.

In order to capture all asynchronous events used for managing the clock gating scheme, the ISR circuit 10 itself is not clock gated. The ISR circuit 10 controls only the coarse grain clock gating granularity, meaning that the clock signal is either enabled or disabled for the macro circuits, but it does not control the dataflow registers within the macro circuit.

Further, the chosen structure enables the macro circuits 12 to 28. The macro circuits 12 to 28 itself are controlled by the ISR circuit 10 in order to control the coarse grain clock gating of another macro circuit. In this case the detailed information are not available in the main clock gating control macro circuit itself, when clock gating for specific macro circuits should be applied. Thus, these macro circuits are controlled by appropriate macro circuits containing the necessary information in order to make clock gating more efficient.

Fig. 2 illustrates a schematic diagram of an external coarse grain clock gating according to a further embodiment of the present invention. This example relates to the ISR circuit 10, the WQC circuiL 20 and a CKX circuit 58. The ISR circuit 10 comprises a clock gating manager 50. The WQC circuit 20 comprises a LCB (logical clock block) circuit 52, a plurality of storage elements 56, a busy detector circuit 54 and a clock gating manager 50.

The clock gating manager 50 of the ISR circuit 10 is connected to the LCB circuit 52 of the WQC circuit 20 via a WQC clock gate line 60. The busy detector circuit 54 is connected to the clock gating manager 50 of the ISP. circuit 10 via the WQC active line 40. The clock gating manager 50 of the WQC circuit 20 is connected to the LCB circuit 52 within the CKX circuit 58 via a "I CKX clock gate line 62. The LCB circuit 52 within the CKX circuit 58 is connected to a plurality of storage elements 56.

In order to be able to disable the clock gatirig for specific macro circuits when these macro circuits are not functionally used two different mechanisms are provided. A first mechanism includes a pipeline oriented structure in order to determine active state without any feedback path. A second mechanism includes a macro circuit active indication with a feedback path.

According to the first mechanism without feedback path, the active state of a certain macro circuit can be clearly derived from an execution pipeline. In this case the clock gating can really be controlled without having any feedback path. This means that the controlling macro circuit needs a kind of execution pipeline copy to detect the phases where the macro circuit is used and thus, the clock gating has to be turned on.

The second mechanism uses the feedback path. If it is not possible to detect the phase where a certain macro circuit is active on the bases of the execution pipeline, then a feedback path is necessary. Sometimes the functions of the macro circuit are kind of asynchronous to the execution pipeline and thus, a special feedback signal indicating the active phase of the macro circuit is necessary. The point in time where the clock gating has to be turned on is detected by the controlling macro circuit itself, but not the duration how long it takes to process a specific task. This information is delivered by the executing macro circuit itself, since this macro has all necessary information. As long as the feedback loop is active clock gating for this specific macro is turned on. Such an example with a feedback path is shown is Fig. 3.

Fig. 3 illustrates a schematic diagram of a clock gating control with a feedback path according to a further embodiment of the *: present invention. This example relates to the ISR circuit 10 and the RIQ circuit 12. The RIQ circuit 12 includes also a LCB circuit 52, a plurality ot storage elements 56 and a busy detector circuit 54. The clock gating manager 50 is connected to the LCB circuit 52 of the RIQ circuit 12 via a RIQ clock gate line 64. The busy detector circuit 54 is connected to the clock gating manager 50 via an RIQ active line 34. The RIQ active line 34 acts as the feedback path.

The fine grain clock gating may be controlled either by the macro circuit itself or by another macro circuit. The clock gating control by the macro circuit itself is described by the examp]e of Fig. 4 and the clock gating control by another macro circuit by the example of Fig. 5 below.

Fig. 4 illustrates a schematic diagram of an internal fine grain clock gating according to a further embodiment of the present invention. This example relates to the ISR circuit 10 and the IPR circuit 28. The IPR circuit 28 includes also a LOB circuit 52, a plurality of storage elements 56, a number of clock gati.ng managers 50 and a number of LJCB Circuits 52. The clock gating managers 50 and three of the LOB circuits 52 are interconnected between the storage elements 56, wherein said three LCB circuits 52 are provided for the fine grain clock gating mechanism.

Further, the three LCB circuits 52 are serially connected to three clock gating managers 50. The single LCB circuit 52 is controlled by the clock gating manager 50 of the TSR circuit 10 via an IPR clock gate line 66. Said single LOB circuit 52 is provided for the coarse grain clock gating mechanism.

In this case the fine grain clock gating is controlled by the macro circuit itself. When the macro circuit is in a functional mode, then all storage elements 56 in the main domain of the macro circuit are clocked. Based on the internal state of the macro circuit the clock for specific dataflow storage elements h, * -10 - 56 is turned on and off depending on the time when they are used. The internal state of the macro circuit can be directly derived from the storage elements 56 contained in the main clock domain.

Fig. 5 illustrates a schematic diagram of an external fine grain clock gating according to a further embodiment of the present invention. This example relates to the ISR circuit 10, the RIQ circuit 12 and the OPX circuit 14. The RIQ circuit 12 includes the LCB circuit 52, the plurality of storage elements 56 and the busy detector circuit 54, as shown in Fig. 3. Additionally, the RIQ circuit 12 comprises also a clock gating manager 50. The OPX circuit 14 includes a number of LCB circuits 52 and a plurality of storage elements 56.

The clock gating manager 50 of the ISR circuit 10 is connected to the LOB circuit 52 of the RTQ circuit 12 via the RIQ clock gate line 64. The busy detector circuit 54 is connected to the clock gating manager 50 of the ISR circuit 10 via the RIQ active line 34. The clock gating manager 50 of the ISR circuit 10 is connected to one LCB circuits 52 of the OPx circuit 14 via a clock gate line 68. The clock gating manager 50 of the RIQ circuit 12 is connected to the other LCB circuits 52 of the OPX circuit 14 via clock gate lines 70.

In the case according to Fig. 5 the fine grain clock gating is controlled by another macro circuit. In this case the information is not available in the macro circuits containing the dataf low itself, when the clock gating to specific dataf low storage elements should be applied. Thus, these macro circuits are controlled by the appropriate macro circuit containing the necessary information.

Depending on the logic structure of the semiconductor chip it is possible to have a number of hierarchy clock gating levels.

-11 -Fig. 6 illustrates a schematic diagram of a clock gating within a hierarchical structure according to a further embodiment of the present invention. The structure comprises a clock gate control circuit 74, a first function macro circuit 76 on a first clock gating level, a second function macro circuit 78 on a second clock gating level and an n-th function macro circuit 80 on an n-th clock gating level. The clock gate control circuit 74 includes the clock gating manager 50. The first 76 and second 78 function macro circuit includes the LCB circuit 52, the plurality of storage elements 56 and also the clock gating manager 50. The n-th function macro circuit 80 comprises the LCB circuit 52 and the plurality of storage elements 56.

The clock gating manager 50 of the clock gate control circuit 74 is connected to the LCB circuit 52 of the first function macro circuit 76 via a clock gate line 72. In the same way, the clock gating manager 50 of one clock gate control circuit 76 or 78 is connected to the LCB circuit 52 of the next function macro circuit 78 or 80, respectively, via the clock gate line 72.

Additional function macro circuits may be interconnected between the second function macro circuit 78 and the ri-th function macro circuit 80.

The structure in Fig. 6 is a generic hierarchy structure where the overall clock gating is controlled by a dedicated macro circuit. Said dedicated macro circuit has all information necessary to control the main clock domain of the macro circuits in the first clock gating level. In order to have a good power save granularity and thus saving power the macro circuit on the second clock gating level is again controlled by the macro circuit in the first clock gating level. In general by using such a structure the main clock domain of the n-th function macro circuit 80 on the clock gating level n is controlled by a function macro circuit on a clock gating level n-i. The function t I -12 -macro circuit 76 on clock gating level n=l is always controlled by the global clock gate control circuit 74.

The clock gating within the hierarchical structure according to the present invention allows a more efficient power saving. By selecting the structure where clock gating is controlled by an instance that has all the necessary information available to effectively manage the clock gating on a given scope is the key to improve the power sav-ing efficiency. This principle is reflected in the chosen clock gating hierarchy. This means that the global power of the macro circuit is managed by an instance containing all the necessary information. By doing this the overall control is concentrated at one place and not spread out over the different macros.

Further, by using this structure it is possible to disable the clock gating for a whole macro circuit, if it is functionally not needed. This is also true for the next hierarchy clock gating level where an internal clock gating within the macro circuit is efficiently managed by the macro circuit itself since all the necessary information is available at this scope. This structure allows performing the clock gating more precisely.

This means that macro circuits are clocked only then, if they are functionally used. These states, at which macro circuits and storage elements are clocked although they are not used, are minimized since this hierarchically approach makes the active detection more effective.

The present invention can also be embedded in a computer program product which comprises all the features enabling the implementation of the methods described herein. Further, when loaded in computer system, said computer program product is able to carry out these methods.

-13 -Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims. *1,(

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LIST OF REFERENCE NUMERALS

ISR (input status register) circuit 12 RIQ (read interlock queue) circuit 14 OPX (output muxing) circuit WQC (write queue control) circuit 22 CSH (checkpoint status register high part) circuit 24 CSL (checkpoint status register low part) circuit 26 IXR (FXU input register) circuit 28 IPR (BFU input register) circuit 32 RIQ power line 34 RIQ active line 36 OPX power line 38 WQC power line WQC active line 42 CSH power line 44 CSL power line 46 1XR power line 48 IPR power line clock gatirig manager 52 LCB (logical clock block) circuit 54 busy detector circuit 56 storage elements 58 CKX (checkpoint muxing) circuit WQC clock gate line 62 CKX clock gate line 64 RIQ clock gate line 66 IPR clock gate line 68 clock gate line clock gate line 72 clock gate line 74 clock gate control circuit 76 first function macro circuit 78 second function macro circuit n-th function macro circuit

Claims

-. 15 - CLAIMS

1. A digital circuit on a semiconductor chip with a plurality of macro circuits (10, 12,..., 28) and a clock gating system (50, 52, 54) for disabling the clock signal for at least one single macro circuit (10, 12, ..., 28), wherein -the digital circuit is designed as a hierarchical structure with at least two clock gating levels, -each macro circuit (10, 12, ..., 28) is associated with one of the clock gating levels, -a macro control circuit (10) is provided on a top clock gating level in order to control the clock gating of at least one other macro circuit (12, 14, ..., 28) on one or more lower clock gating levels, and -all external signals (30, 32, ..., 40) used to control the clock gating are connected to the macro control circuit (10)

2. The digital circuit according to claim 1, wherein at least one macro circuit (12, 14, ..., 28) on a second or lower clock gating level is provided to control the clock gating of at least one other macro circuit (12, 14, ..., 28) on one or more lower clock gating levels or on the same clock gating level.

3. The digital circuit according to claim 1 or 2, wherein the clock gating mechanism is working on the boundaries of the macro circuits (12, 14, ..., 28).

4. The digital circuit according to any one of the preceding claims, wherein the clock gating mechanism is working substantially on dataf low storage elements within the macro circuit (12, 14, ..., 28)

5. The digital circuit according to any one of the preceding claims, wherein the macro control circuit (10, 50) is provided -16 to detect the phases where the macro circuits (12, 14, ..., 28) is used.

6. The digital circuit according to any one of the preceding claims, wherein the clock gating system includes a pipeline oriented structure in order to determine active states.

7. The digital circuit according to any one of the preceding claims, wherein the clock gating system includes macro circuit active indication means (54) for indicating the active phase of the macro circuit (12, 14, ..., 28) with a feedback path.

8. The digital circuit according to any one of the preceding claims, wherein the digital circuit is realized in hardware or a combination of hardware and software.

9. A method for controlling a clock gating system (50, 52, 54) of a digital circuit designed as a hierarchical structure with at least two clock gating levels on a semiconductor chip, wherein the digital circuit is subdivided into a plurality of macro circuits (10, 12, ..., 28) associated with one of the clock gating levels and the clock gating system (50, 52, 54) is provided for disabling the clock signal for at least one single macro circuit (10, 12, ..., 28) , and wherein said method comprises the steps of: -a macro control circuit (10) controls the clock gating of at least one other macro circuit (12, 14, ..., 28) on one or more lower clock gating levels, and -all external signals (30, 32, ..., 40) used to control the clock gating are applied to the macro control circuit (10).

10. The method according to claim 9 or 10, wherein at least one macro circuit (12, 14, ..., 28) on a second or lower clock gating level controls the clock gating of at least one other macro -17 -circuit (12, 14, ..., 28) on one or more lower clock gating levels or on the same clock gating level.

11. The method according to claim 9 or 10, wherein the clock gating works on the boundaries of the macro circuits (12, 14 28)

12. The method according to any one of the claims 9 to 11, wherein the clock gating works substantially on dataf low storage elements within the macro circuit (12, 14, ..., 28)

13. The method according to any one of the claims 9 to 12, wherein the macro control circuit MO, 50) detects the phases where the macro circuits (12, 14, ..., 28) is used.

14. The method according to any one of the claims 9 to 13, wherein the active states are determined by a pipeline oriented structure.

15. The method according to any one of the claims 9 to 14, wherein the active phase (54) of the macro circuit (12, 14, 28) is indicated by a feedback path.

16. The method according to any one of the claims 9 to 15, wherein the method is realized in hardware, software or a combination of hardware and software.

17. A computer program product stored on a computer usable medium, comprising computer readable program means for causing a computer to perform a method according to anyone of the preceding claims 9 to 16.