GB2456004A - Frequency synthesiser with output frequency higher than VCO frequency - Google Patents

Frequency synthesiser with output frequency higher than VCO frequency Download PDF

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Publication number
GB2456004A
GB2456004A GB0725342A GB0725342A GB2456004A GB 2456004 A GB2456004 A GB 2456004A GB 0725342 A GB0725342 A GB 0725342A GB 0725342 A GB0725342 A GB 0725342A GB 2456004 A GB2456004 A GB 2456004A
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United Kingdom
Prior art keywords
signal
frequency
detector
oscillator
output
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GB0725342A
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GB0725342D0 (en
Inventor
John Paul Lesso
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Cirrus Logic International UK Ltd
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Wolfson Microelectronics PLC
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Application filed by Wolfson Microelectronics PLC filed Critical Wolfson Microelectronics PLC
Priority to GB0725342A priority Critical patent/GB2456004A/en
Publication of GB0725342D0 publication Critical patent/GB0725342D0/en
Priority to PCT/GB2008/004269 priority patent/WO2009083713A1/en
Publication of GB2456004A publication Critical patent/GB2456004A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

A frequency synthesiser comprises an oscillator 43, for example a numerically controller oscillator, for generating a first signal. An edge combiner 45 is provided for generating a second signal derived from the first signal, for example using two or more tap signals from the oscillator, the second signal having a frequency that is greater than that of the first signal. A detector 33 receives an input reference signal Fin and a feedback signal 35, and generates an output signal 37 that is used to provide an input to the oscillator, such that the oscillator operates in a locked loop mode of operation. The feedback signal to the detector is taken from the output of the edge combiner 45 rather than directly from the output of the oscillator, thus compensating for errors introduced by the edge combiner 45. The feedback signal may also pass through a divider 36. The frequency synthesiser may also include a sigma-delta modulator (47, fig.4) which is clocked by either the first signal or the second signal depending on power requirements. Keywords: synthesizer, synthesizer, edge combiner, frequency multiple.

Description

FREQUENCY SYNTHESISER APPARATUS AND METHOD
Technical Field
The present invention relates to a frequency synthesiser apparatus and method, and more particularly to the use of edge combiners in a frequency locked loop (FLL) or a phase locked loop (PLL).
Background
Figure 1 shows a conventional frequency synthesiser configured as a frequency-locked loop (FLL). A signal having a frequency FIN is input to a frequency detector 3, which determines the frequency difference between FIN and the frequency of a feedback signal 5. The output of the frequency detector 3, i.e. a frequency difference signal 7, is input to a block 9. The block 9 may be an integrating block having an integrating function, a filter, or a combined integrator and filter. As such, the block 9 may comprise, for example, a loop filter having an integrating function. The signal 11 output from the block 9 is passed to a numerically controlled oscillator (NCO) 13. The NCO 13 is designed to output a signal 5 with a high frequency if the signal 11 is relatively high, or a low frequency if the signal 11 is relatively low. For example, the NCO 13 may comprise a digital-to-analogue converter (DAC) followed by a voltage-controlled oscillator (VCO).
In order to output a signal having a frequency that is higher than that of the NCO 13, an edge combiner (EC) 15 is used to tap into the NCO 13 and generate an output signal with a frequency FOUT that is a fixed multiple of the frequency of the NCO 13. Figure 1 shows the EC 15 having three tap signals from the NCO 13, which results in the EC 15 producing a signal F0 having a frequency which is three times the frequency of the signal 5 generated by the NCO 13. Thus, to produce an output signal FOUT having a frequency which is N times the frequency of the signal 5 generated by the NCO 13 would require N tap signals from the NCO 13.
Figure 2a shows an example of an oscillator having three oscillating stages 21, 22, 23, with three taps o, and 02. The oscillating stages 21, 22, 23 are shown as inverters, but it will be appreciated that other circuit components may also be used. A digital signal input to the loop will oscillate between 0 and 1 as it passes through each of the three inverters. It will be appreciated that Figure 2a shows three stages in the NCO 13 of Figure 1 * with the tap signals 4), , and D2 relating to the tap signals that would be taken to the EC 15.
Figure 2b shows how the tap signals, and 02 may vary with time. For ease of reference, the inverse of tap cD is shown, i.e. ,. By carefully designing the delays inherent in each of the oscillating stages 21, 22, 23, the signal can effectively be delayed by a fixed amount. The EC 15 acts to output a pulse whenever a positive edge is encountered by any of the tap signals 0, 4) and 02, thereby generating a signal having a frequency that is three times the frequency of the oscillator.
It will be appreciated that edge combiner circuits are disadvantageously difficult to design, and the circuitry used must be carefully planned in order to ensure that the output frequency F0 is accurate and stable. This is partly because any differences in the stages 21, 22, 23 (for example different time delays) would be reflected in the output frequency Foijr.
It is therefore an aim of the invention to provide a frequency synthesiser apparatus and method that does not suffer from the disadvantage mentioned above.
Summary of the invention
According to a first aspect of the invention, there is provided a frequency synthesiser comprising:an oscillator for generating a first signal having a first frequency; an edge combiner for generating a second signal derived from the first signal, the second signal having a frequency that is greater than the first signal; a detector for providing an input signal to the oscillator, the detector configured to receive an input reference signal and a feedback signal; wherein the second signal generated by the edge combiner forms the feedback signal for the detector.
According to another aspect of the invention, there is provided a method of synthesising a frequency signal, the method comprising the steps of: generating a first signal having a first frequency using an oscillator; generating a second signal derived from the first signal, the second signal having a frequency that is greater than the first signal; and using the second signal as a feedback signal in a detector that provides an input signal to the oscillator, the detector configured to receive an input reference signal and the feedback signal.
Brief descriDtion of the drawinQs For a better understanding of the invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example only, to the following drawings in which: Figure 1 shows a typical frequency synthesiser; Figure 2a shows an example of oscillating stages in the frequency synthesiser of Figure 1; Figure 2b shows the waveforms from taps In the oscillating stages of Figure 2a; Figure 3 shows a frequency synthesiser according to a first embodiment of the present invention; and Figure 4 shows a frequency synthesiser according to a second embodiment of the present invention.
DescriDtion of the �referred embodiments The embodiments described below will be made in relation to a frequency synthesiser configured in the form of a frequency locked loop. However, it will be appreciated that the invention is equally applicable to other forms of frequency synthesisers, such as phase locked loops.
Figure 3 shows a FLL 30 according to an embodiment of the present invention. A frequency FIN is input to a frequency detector 33. The frequency detector outputs a frequency difference signal 37 to a block 39, the block 39 having, for example, an integrating and/or filtering function. A signal 41 output from the block 39 is passed to an oscillator 43, for example a numerically controlled oscillator (NCO) 43. The NCO 43 would normally produce a first signal 49 having a first frequency. In order to output a signal with a higher frequency than that of the NCO 43, i.e. higher than the first signal 49, an edge combiner 45 is used as described above to tap into the NCO 43 and generate a second signal (i.e. the output signal of the frequency synthesiser) having a frequency F0,-that is a multiple of the frequency of the first signal 49 from the NCO 43.
As such, the EC 45 produces a second signal (i.e. For) that is derived from the first signal (i.e. 49). In the example of Figure 3 the EC 45 is shown as having five tap signals coming from the NCO 43, thus generating an output signal having a frequency F that is five times the frequency of the signal 49 generated by the NCO 43.
According to the invention, the output of the EC 45 is fed back to the frequency detector 33, such that the frequency detector 33 determines the difference between the input frequency FIN and the output signal F0. This means that any distortion or errors in the output signal, for example introduced by the edge combiner 45 because of unmatched delays in the oscillator stages of the NCO 43, will be automatically corrected for by the feedback loop 35. This has the advantage of relaxing the constraints on the designer of the frequency synthesiser. In other words, the designer constraints are relaxed because the oscillator stages 21, 22, 23 of Figure 2a do not need to be as accurate, since any fluctuations in the output signal F0 will be compensated for by the output signal F01 being fed back to the frequency detector 33.
It Is noted that the feedback path 35 may optionally comprise a divide-by-N block 36, N being, for example, the number of tap signals from the NCO 43 to the EC 45. The divide-by-N block may be used to lower the frequency of the signal in the feedback path 35, i.e. in view of the fact that the feedback signal is now being taken from the higher frequency output signal F0 from the EC 45 rather than directly from the output 49 of the NCO 43.
Figure 4 shows a further embodiment of the invention, with examples of the possible frequencies involved. As with Figure 3, a frequency FIN is input to a frequency detector 33. The frequency detector outputs a signal 37 to a block 39, for example having an integrating and/or filtering function. However, rather than connecting the signal 41 directly to the NCO 43, the output from the block 39 is instead passed via a sigma-delta word length reduction block, i.e. sigma-delta modulator, 47. The sigma-delta modulator 47 enables the complexity of the oscillator (i.e. NCO 43) to be reduced further, as described in greater detail in co-pending application number GBO7I 4890.1 by the present applicant, (applicant's reference P1002GBOO WLR F8). The sigma-delta modulator (SDM) 47 receives a signal 41 having a relatively high number of bits, and outputs a signal 51 having a relatively lower number of bits. However, the output signal averages very accurately to the input signal. To output a sufficiently accurate signal, the SDM 47 must be clocked at a relatively high rate. However, this consumes a significant amount of power, and therefore a compromise must be reached.
Thus, according to a further aspect of the invention, this compromise is achieved by clocking the SDM with the output signal 49 from the NCO 43 rather than the relatively higher frequency signal F0 from the output of the EC 45, but feeding back the output of the EC 45 to the frequency detector 33 as described in Figure 3. In a non-restrictive example, the SDM 47 may therefore be clocked at 20 MHz, which is sufficiently fast for the system to operate correctly. However, the greater 100 MHz signal output from the EC 45 is fed back to the frequency detector 33, so any errors introduced by the EC 45 and/or NCO 43 are corrected for. It will be appreciated that the output signal of the EC 45 has a frequency of 100 MHz in the example provided, in view of the fact that the EC receives five taps from the NCO 43 which, in the illustrative example, has an output frequency 49 of 20MHz.
Thus, as with the embodiment of Figure 3, the output of the EC 45 in Figure 4 is fed back to the frequency detector 33, such that the frequency detector 33 determines the difference between the input frequency FIN and the output signal F0.
It is noted that, as with Figure 3, the feedback path 35 may optionally comprise a divide-by-N block 36, N being, for example, the number of tap signals from the NCO 43 to the EC 45. The divide-by-N block may be used to lower the frequency of the signal in the feedback path 35, i.e. in view of the fact that the feedback signal is now being taken from the higher frequency output signal F from the EC 45 rather than directly from the output of the NCO 43.
It will be appreciated that the sigma-delta modulator 47 could be clocked by the higher frequency signal from the output of the EC 45, for example when power consumption is not an issue. Alternatively, the frequency synthesiser could be arranged such that the sigma-delta modulator 47 is selectively or dynamically switchable between being clocked by the output of the NCO 43 and the output of the EC 45. For example, when low power consumption is important, such as when the frequency synthesiser is being used in battery powered equipment, the frequency synthesiser can be configured such that the sigma-delta modulator 47 is clocked by the output signal 49 from the NCO 43.
However, the sigma-delta modulator 47 could be switched to be clocked by the output signal F0 from the EC 45 when the battery powered equipment is temporarily connected to a mains power supply, for example when connected to a charger or docking station.
The frequency synthesiser described above has the advantage of operating in a locked loop configuration, wherein any errors introduced by the edge combiner are compensated for.
The frequency synthesiser described above may be used in numerous applications.
These include, but are not limited to, applications in the fields of: portable audio players (MP3 Players); mobile phones; PDAs; HI-Fl; DVD; CD; TV (inc Flat Screen); Sat Nay; Camera (still & video); In-Car/Train/Plane entertainment systems.
It is noted that, although the embodiments above are described in relation to the frequency synthesiser having a numerically controlled oscillator, the invention is also applicable to frequency synthesisers having other types of oscillator.
The skilled person will recognise that some of the above-described apparatus and methods may be embodied as processor control code, for example on a carrier medium such as a disk, CD-or DVD-ROM, programmed memory such as read only memory (firmware), or on a data carrier such as an optical or electrical signal carrier.
For many applications, embodiments of the invention will be implemented on a DSP (digital signal processor), ASIC (application specific integrated circuit) or FPGA (field programmable gate array). Thus the code may comprise conventional program code or microcode or, for example code for setting up or controlling an ASIC or FPGA. The code may also comprise code for dynamically configuring re-configurable apparatus such as re-programmable logic gate arrays. Similarly the code may comprise code for a hardware description language such as Verilog TM or VHDL (very high speed integrated circuit hardware description language). As the skilled person will appreciate, the code may be distributed between a plurality of coupled components in communication with one another. Where appropriate, the embodiments may also be implemented using code running on a field-(re-)programmable analogue array or similar device in order to configure analogue/digital hardware.
It should also be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims or drawings. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single element or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims (29)

1. A frequency synthesiser comprising: an oscillator for generating a first signal having a first frequency; an edge combiner for generating a second signal derived from the first signal, the second signal having a frequency that is greater than the first signal; a detector for providing an input signal to the oscillator, the detector configured to receive an input reference signal and a feedback signal; wherein the second signal generated by the edge combiner forms the feedback signal for the detector.
2. A frequency synthesiser as claimed in claim 1, further comprising a sigma-delta modulator circuit connected between the detector and the oscillator.
3. A frequency synthesiser as claimed in claim 2, wherein the sigma-delta modulator is clocked by the first signal.
4. A frequency synthesiser as claimed in claim 2, wherein the sigma-delta modulator is clocked by the second signal.
5. A frequency synthesiser as claimed in claim 2, wherein the sigma-delta modulator is selectively clocked by either the first signal or the second signal.
6. A frequency synthesiser as claimed in any preceding claim, further comprising an integrating and/or filtering circuit connected between the output of the detector and the input of the oscillator.
7. A frequency synthesiser as claimed in claim 6 when dependent on any one of claims 2 to 5, wherein the integrating and/or filtering circuit is connected between the output of the detector and the input of the sigma-delta modulator.
6. A frequency synthesiser as claimed in any one of the preceding claims, wherein the frequency synthesiser is configured as a frequency locked loop, and wherein the second signal from the edge combiner to the detector forms the loop of the frequency locked loop.
9. A frequency synthesiser as claimed in any one of claims 1 to 7, wherein the frequency synthesiser is configured as a phase locked loop, and wherein the second signal from the edge combiner to the detector forms the loop of the phase locked loop.
10. A frequency synthesiser as claimed in any one of the preceding claims, wherein the second signal is derived from the first signal using two or more tap signals taken from the oscillator.
11. A method of synthesising a frequency signal, the method comprising the steps of: generating a first signal having a first frequency using an oscillator; generating a second signal derived from the first signal, the second signal having a frequency that is greater than the first signal; and using the second signal as a feedback signal in a detector that provides an input signal to the oscillator, the detector configured to receive an input reference signal and the feedback signal.
12. A method as claimed in claim 11, further comprising the step of providing a sigma-delta modulator between the detector and the oscillator.
13. A method as claimed in claim 12, further comprising the step of clocking the sigma-delta modulator using the first signal.
14. A method as claimed in claim 12, further comprising the step of clocking the sigma-delta modulator using the second signal.
15. A method as claimed in claim 12, further comprising the step of selectively clocking the sigma-delta modulator using either the first signal or the second signal.
16. A method as claimed in any one of claims 11 to 15, further comprising the step of providing an integrating and/or filtering circuit between the output of the detector and the input of the oscillator.
17. A method as claimed in claim 16 when dependent on any one of claims 12 to 14, further comprising the step of providing the integrating and/or filtering circuit between the output of the detector and the input of the sigma-delta modulator.
18. A method as claimed in any one of claims 11 to 17, wherein the frequency synthesiser is configured as a frequency locked loop, and wherein the second signal from the edge combiner to the detector forms the loop of the frequency locked loop.
19. A method as claimed in any one of claims 11 to 17, wherein the frequency synthesiser is configured as a phase locked loop, and wherein the second signal from the edge combiner to the detector forms the loop of the phase locked loop.
20. A method as claimed in any one of claims 11 to 19, wherein the second signal is derived from the first signal using two or more tap signals taken from the oscillator.
21. An integrated circuit, comprising a frequency synthesiser as claimed in any of claims ito 10.
22. An audio system, comprising an integrated circuit as claimed in claim 21.
23. An audio system as claimed in claim 22, wherein the audio system is a portable device.
24. An audio system as claimed in claim 22, wherein the audio system is a mains-powered device.
25. An audio system as claimed in claim 22, wherein the audio system is an in-car, in-train, or in-plane entertainment system.
26. A video system, comprising an integrated circuit as claimed in claim 21.
27. A video system as claimed in claim 26, wherein the video system is a portable device.
28. A video system as claimed in claim 26, wherein the video system is a mains-powered device.
29. A video system as claimed in claim 26, wherein the video system is an in-car, in-train, or in-plane entertainment system.
29. A video system as claimed in claim 26, wherein the video system is an in-car, in-train, or in-plane entertainment system.
Amendments to the claims have been filed as follows Ii
1. A frequency synthesiser for receiving an input reference signal and generating an output signal, the frequency synthesiser comprising: an oscillator for generating a first signal having a first frequency; an edge combiner for generating the output signal derived from the first signal, the output signal having a frequency that is greater than the first signal; a detector for providing an input signal to the oscillator, the detector configured to receive the input reference signal and a feedback signal; wherein the output signal generated by the edge combiner further forms the feedback signal for the detector.
2. A frequency synthesiser as claimed in claim 1, further comprising a sigma-delta modulator circuit connected between the detector and the oscillator.
3. A frequency synthesiser as claimed in claim 2, wherein the sigma-delta modulator is clocked by the first signal.
4. A frequency synthesiser as claimed in claim 2, wherein the sigma-delta modulator is clocked by the output signal.
5. A frequency synthesiser as claimed in claim 2, wherein the sigma-delta modulator is selectively clocked by either the first signal or the output signal.
6. A frequency synthesiser as claimed in any preceding claim, further comprising an integrating and/or filtering circuit connected between the output of the detector and the input of the oscillator.
7. A frequency synthesiser as claimed in claim 6 when dependent on any one of claims 2 to 5, wherein the integrating and/or filtering circuit is connected between the output of the detector and the input of the sigma-delta modulator.
8. A frequency synthesiser as claimed in any one of the preceding claims, wherein the frequency synthesiser is configured as a frequency locked loop, and wherein the output signal from the edge combiner to the detector forms the loop of the frequency locked loop.
9. A frequency synthesiser as claimed in any one of claims 1 to 7, wherein the frequency syrithesiser is configured as a phase locked loop, and wherein the output signal from the edge combiner to the detector forms the loop of the phase locked loop.
10. A frequency synthesiser as claimed in any one of the preceding claims, wherein the output signal is derived from the first signal using two or more tap signals taken from the oscillator.
11. A method of synthesising an output signal from an input reference signal, the method comprising the steps of: generating a first signal having a first frequency using an oscillator; generating the output signal derived from the first signal, the output signal having a frequency that is greater than the first signal; and using the output signal as a feedback signal in a detector that provides an input signal to the oscillator, the detector configured to receive an input reference signal and the feedback signal.
12. A method as claimed in claim 11, further comprising the step of providing a sigma-delta modulator between the detector and the oscillator.
13. A method as claimed in claim 12, further comprising the step of clocking the sigma-delta modulator using the first signal.
14. A method as claimed in claim 12, further comprising the step of clocking the sigma-delta modulator using the output signal.
15. A method as claimed in claim 12, further comprising the step of selectively clocking the sigma-delta modulator using either the first signal or the output signal.
16. A method as claimed in any one of claims 11 to 15, further comprising the step of providing an integrating and/or filtering circuit between the output of the detector and the input of the oscillator.
17. A method as claimed in claim 16 when dependent on any one of claims 12 to 14, further comprising the step of providing the integrating and/or filtering circuit between the output of the detector and the input of the sigma-delta modulator.
18. A method as claimed in any one of claims 11 to 17, wherein the frequency synthesiser is configured as a frequency locked loop, and wherein the output signal from the edge combiner to the detector forms the loop of the frequency locked loop.
19. A method as claimed in any one of claims 11 to 17, wherein the frequency synthesiser is configured as a phase locked loop, and wherein the output signal from the edge combiner to the detector forms the loop of the phase locked loop.
20. A method as claimed in any one of claims 11 to 19, wherein the output signal is derived from the first signal using two or more tap signals taken from the oscillator.
21. An integrated circuit, comprising a frequency synthesiser as claimed in any of claims Ito 10.
22. An audio system, comprising an integrated circuit as claimed in claim 21.
23. An audio system as claimed in claim 22, wherein the audio system is a portable device.
24. An audio system as claimed in claim 22, wherein the audio system is a mains-powered device.
25. An audio system as claimed in claim 22, wherein the audio system is an in-car, in-train, or in-plane entertainment system.
26. A video system, comprising an integrated circuit as claimed in claim 21.
27. A video system as claimed in claim 26, wherein the video system is a portable device.
28. A video system as claimed in claim 26, wherein the video system is a mains-powered device.
GB0725342A 2007-12-28 2007-12-28 Frequency synthesiser with output frequency higher than VCO frequency Withdrawn GB2456004A (en)

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GB0725342A GB2456004A (en) 2007-12-28 2007-12-28 Frequency synthesiser with output frequency higher than VCO frequency
PCT/GB2008/004269 WO2009083713A1 (en) 2007-12-28 2008-12-23 Frequency synthesiser apparatus and method

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WO2007130750A2 (en) * 2006-03-21 2007-11-15 Leadis Technology, Inc. Phase-slipping phase-locked loop

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US6943599B2 (en) * 2003-12-10 2005-09-13 International Business Machines Corporation Methods and arrangements for a low power phase-locked loop
US7330060B2 (en) * 2005-09-07 2008-02-12 Agere Systems Inc. Method and apparatus for sigma-delta delay control in a delay-locked-loop

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Publication number Priority date Publication date Assignee Title
US5945881A (en) * 1998-01-12 1999-08-31 Lucent Technologies Inc. PLL frequency synthesizer with K multiplication in addition to division for subtraction of phase noise
US20060261903A1 (en) * 2003-11-28 2006-11-23 Advantest Corporation Oscillator, frequency multiplier, and test apparatus
WO2007130750A2 (en) * 2006-03-21 2007-11-15 Leadis Technology, Inc. Phase-slipping phase-locked loop

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WO2009083713A1 (en) 2009-07-09

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