GB2452790A

GB2452790A - Power supply controller circuitry

Info

Publication number: GB2452790A
Application number: GB0724689A
Authority: GB
Inventors: Mikkel Hoyerby
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 2007-09-14
Filing date: 2007-12-19
Publication date: 2009-03-18
Anticipated expiration: 2027-12-19
Also published as: GB2452790B; GB0724689D0; GB0717958D0

Abstract

A switched-mode power supply controller circuit 300 comprises oscillation circuitry 310, compensation circuitry 320 arranged to provide a compensated control signal to the oscillation circuitry 310, and power converter circuitry 330 operably coupled to an output of the oscillation circuitry 310. The power supply controller circuit 300 further comprises switching frequency controller logic 340 operably coupled to the compensation circuitry 320 and arranged to control a switching frequency of the power supply controller circuit 300 based on at least a switching frequency feedback signal from an output of the oscillation circuitry 310. Varying output ripple voltage is substantially alleviated whilst providing increased control loop bandwidth.

Description

POWER SUPPLY CONTROLLER C[RCUTTRY

TECHNICAL FIELD

The technical field relates generally to power supply controller circuitry, and more particularly to power supply controller circuitry for ultra-fast tracking power supplies.

BACKGROUND

In the field of digital radio systems, for example the TErrestrial Trunked Radio (TETRA) system, developed by the European Telecommunications Standards Institute (ETSI), and defined by a plurality of ETSI Standards, including the ETS 300-39x technical specification series, and the more recent TETRA 2 system, defined in the draft for release 2 of the TETRA specifications, it is desirable to control the voltage or cusrent supply to the transmitter power amplifier (PA). In this manner, by use of a controller to dynamically set the applied voltage or current to the PA, the output power level of the PA may be adjusted to correspond more closely to the required instantaneous output power level in order to maximize the PA efficiency.

To this end, an Ultra-Fast Tracking Power Supply (UFTPS) is typically required for generating a rapidly varying PA supply voltage, whilst not wasting power itself. The requirements for such a UFTPS include: (i) UFTPS power losses should be low enough for an overall system power saving to be realized, and as such must use switch-mode technology; (ii) the output voltage must respond quickly to reference changes (ideally at a rate equivalent to the transmitted radio frequency (RF) signal bandwidth, for example 25-150kHz according to TETRA 2

specifications);

(iii) the output ripple voltage, which is a feature of switch-mode power converters, must be low enough to avoid RF pollution when it inter-modulates with the transmitted RF signal (for example in a range of 5 -. SOmVpp); (iv) electromagnetic fields emitted from the UFTPS should be configured to not interfere with the PA output spectrum; and (v) the output impedance of the UFTPS must be sufficiently low, from DC to the RF bandwidth, in order to produce a relatively stiff' supply voltage for the PA (for example in a region of 10 -I 00m for high power wireless transmission units).

In effect, the UFTPS is required to act as a low-dissipation, low-electromagnetic interference (EMI) controllable voltage source, from DC to the RF bandwidth, and as such must achieve an acceptable compromise between output impedance and ripple voltage.

FIG. 1 illustrates an example of a known LIFTPS circuit using a standard clocked pulse width modulator and a proportional-integral-derivative compensator (PWM/PID) voltage-mode control scheme. Such known solutions are based on having a signal that is external to the control loop (V rrlei) generating the high-frequency dynamics necessary to make the control loop switch output voltage levels.

For these types of solution, it is necessary to limit the control loop bandwidth, or more precisely the crossover frequency, in order to avoid instabilities caused when the slope of ripple on the PWM input exceeds the slope of the carrier. Typically, a loop crossover frequency of less than a quarter of the switching frequency is necessary to avoid this form of instability.

Typically the control loop bandwidth is required to be limited to between three to ten times less than the switching frequency. Since the control ioop is instrumental in reducing the output impedance of the UFTPS, as well as providing a fast response, this limitation of control loop bandwidth results in increased output impedance and/or response speed of the power supply. This is particularly the case when the switching frequency is outside of the control loop bandwidth.

FIG. 2 illustrates a different class of known control system, in which the UFTPS uses a hysteretic self-oscillating PID voltage-mode control scheme. In this solution, no external signal is required to produce the switching. It is noteworthy that Vcarrier now refers to the output of the compensation circuitry, reflecting the common notion that a hysteretic controller generates its own carrier signal'. Instead, a purposefully introduced instability in the control loop is used. This fundamentally (according to the well-established Barkhausen criteria for oscillation) leads to a control loop bandwidth (crossover frequency) that is equal to the switching frequency.

In the hysteretic self-oscillating controller, the instability is caused by the presence of hysteresis, as also exploited in common triangle-wave oscillator circuits. In this manner, the loop gain can be increased by a factor of between three to ten times over traditional solutions, such as that illustrated in FIG. 1.

A problem with the type of solution illustrated in FIG. 2 is that the switching (oscillation) frequency will vary with the duty ratio of the generated PWM signal, resulting in a variable ripple voltage at the output of the UFTPS. Since the UFTPS will generally be required to maintain a maximum output ripple voltage, the variation in the switching frequency is undesirable, and is particularly problematic when the VFTPS is fitted with a higher-order output filter. This problem is primarily due to the attenuation of a higher-order filter changing dramatically with frequency (compared to a second-order filter). As an example, a UFTPS with a 4' order filter would have its ripple increase by 24dB (a factor of around 16') if the switching frequency were halved. This would commonly happen for a normal hysteretic controller in the UFTPS application, where the output voltage range is large.

Thus, there exists a need for power supply controller circuitry, an integrated circuit and a communication unit, which addresses at least some of the shortcomings of past and present power supply controller circuits.

BRIEF DESCRIPTION OF TIlE FIGURES

The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views, which together with the detailed description below are incorporated in and form part of the specification and serve to further illustrate various embodiments of concepts that include the claimed invention, and to explain various principles and advantages of those embodiments.

FIG. I illustrates an example of a known UFTPS control system.

FIG. 2 illustrates an alternative example of a known UFTPS control system.

FIG. 3 illustrates a power supply controller circuit according to some embodiments.

FIG. 4 illustrates an example of a power supply controller circuit in accordance with the embodiment of FIG. 3.

FIG. 5 illustrates feed-forward block according to an embodiment.

FIG. 6 illustrates feed-forward block according to an alternative embodiment.

FIG. 7 illustrates feed-forward block according to a further alternative embodiment.

FIG. 8 illustrates feed-forward block according to a still further alternative embodiment.

FIG. 9 illustrates a power supply controller circuit according to an alternative embodiment.

FIG. 10 illustrates an example of a power supply controller circuit in accordance with the embodiment of FIG. 9.

FIG. 11 illustrates a power supply controller circuit according to an alternative embodiment.

FIG. 12 illustrates an example of a power supply controller circuit in accordance with the embodiment of FIG. 11.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments. In addition, the description and drawings do not necessarily require the order illustrated. Apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the various embodiments so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Thus, it will be appreciated that for simplicity and clarity of illustration, common and well-understood elements that are useful or necessary in a commercially feasible embodiment may not be depicted in order to facilitate a less obstructed view of these various embodiments.

DETAILED DESCRIPTION

Generally speaking, pursuant to the various embodiments, there is provided a power supply controller circuit comprising oscillation circuitry, compensation circuitry arranged to provide a compensated control signal to the oscillation circuitry, and power converter circuitry operably coupled to an output of the oscillation circuitry. The power supply controller circuitry further comprises switching frequency controller logic, arranged to control the switching frequency of the power supply controller circuitry based on at least switching frequency feedback from the output of the oscillation circuitry.

In this manner, a known problem of a varying output ripple voltage, caused by the switching frequency varying with a duty ratio of an output of the oscillation circuitry, may be substantially alleviated, whilst providing increased control loop bandwidth afforded by a self-oscillating switch-mode power supply controller.

Those skilled in the art will realise that the above recognised advantages and other advantages described herein are merely illustrative and arc not meant to be a complete rendering of all of the advantages of the various embodiments.

Referring now to the drawings, and in particular FIG. 3, power supply controller circuitry in accordance with some embodiments is shown and indicated generally at 300. The power supply controller circuitry 300 comprises oscillation circuitry 310, compensation circuitry 320 arranged to provide a compensated control signal to the oscillation circuitry 310, and power converter circuitry 330 operably coupled to an output of the oscillation circuitry 310. For the illustrated embodiment, the oscillation circuitry 310 comprises a hysteretic self-oscillating comparator.

Those skilled in the art, however, will recognise and appreciate that the specifics of this example are merely illustrative of some embodiments and that the teachings set forth herein are applicable in a variety of alternative settings. For example, since the teachings described do not depend on a hysteretic self-oscillating control scheme, they can be applied to any type of oscillating control scheme, although a hysteretic self-oscillating control scheme is shown in this embodiment. As such, other alternative implementations using different types of oscillation circuitry are contemplated and are considered to be within the scope of the various teachings described. For example, in a phase-shift self-oscillating controller, the phase shift network may be made variable, similarly providing control over the switching frequency. This is because the phase-shift self-oscillating control loop will oscillate at the point where the total phase lag through the entire loop is -360°.

For the embodiment illustrated in FIG. 3, the compensation circuitry 320 comprises controllable gain compensation circuitry, and receives as an input a required output envelope voltage signal (V11), and control loop feedback from the output of the power converter circuitry 330, via control ioop feedback circuitry 350.

The required output envelope voltage signal (V1) and the control loop feedback may be added together, or otherwise processed, to produce an error signal.

The compensation circuitry 320 is operably coupled to the output of the oscillation circuitry 310 via switching frequency controller logic 340. The switching frequency controller logic 340 generates a switching frequency control signal (V t), based on the output of the oscillation circuitry 310 and, for the illustrated embodiment, a reference signal (ReO. This switching frequency control signal (V lrq) is provided to the compensation circuitry 320. For clarity, the switching frequency refers to the oscillating frequency of the output signal from the oscillation circuitry 310.

The compensation circuitry 320 generates the compensated control signal based on the error signal, from the required output envelope voltage signal and the control loop feedback, and the switching frequency control signal (V tq). In particular, the compensated control signal is generated to compensate for any discrepancy between the required output and the actual output from the power converter circuitry, whilst also compensating for variation of switching frequency, such that the switching (oscillating) frequency of the output signal from the oscillation circuitry 310 remains substantially constant, or at least within a predetermined range.

As will be appreciated by a skilled artisan, the oscillation circuitry 310 provides a switching signal to the power converter circuitry 330, based on the compensated control signal from the compensation circuitry 320 and the switching signal driving the power converter circuitry 330. Accordingly, by compensating for a variation of switching frequency in the aforementioned manner, and thereby maintaining a substantially constant switching signal, or at least a switching signal with a frequency within a predetermined range, output voltage ripple from the power converter circuit 330 remains substantially constant, or at least within a predetermined range. In this manner, the output voltage ripple of the power supply controller circuit 300 may be maintained below a maximum level, as defined by, for example, design considerations of a load to which power is to be supplied by the power supply controller circuit 300.

Referring now to FIG. 4, there is illusirated an example of a power supply controller circuit 400 in accordance with the embodiment of FIG. 3. The power supply controller circuit 400 comprises oscillation circuitry, in a form of hysteretic comparator 410, compensation circuitry 420 arranged to provide a compensated control signal to comparator 410, and power converter circuitry 330 operably coupled to an output of hysteretic self-oscillating comparator 410.

For the embodiment illustrated in FIG. 4, the compensation circuitry 420 comprises Proportional-Integral-Dez-jvative (PID) controller circuitry 425 and feed-forward block 460. The P11) controller circuitry 425 receives, as an input, a required output envelope voltage signal (Ve\), and control loop feedback from the output of the power converter circuitry 430, via control loop feedback circuitry 450. The PID controller circuitry 425 produces an error signal from the required output envelope voltage signal (Vl\) and the control loop feedback, which is provided to the feed-forward block 460.

The compensation circuitry 420, and more particularly for the illustrated embodiment the feed-forward block 460, is operably coupled to the output of the hysteretic self-oscillating comparator 410, via switching frequency controller logic 440. The switching frequency controller logic 440 comprises frequency-to-voltage conversion logic 445, which receives the output signal from the comparator 410, and converts the switching (oscillating) frequency of the received signal into a voltage value representing the switching frequency. The voltage value is then provided to switching frequency compensation circuitry 447, along with a switching frequency reference signal (Vri't). In response thereto, the switching frequency compensation circuitry 447 generates a switching frequency control signal hq), which is provided to the compensation circuitry 420, and more particularly for the illustrated embodiment the feed-forward block 460.

The feed-forward block 460 generates the compensated control signal based on the error signal from the PID controller circuitry 425 and the switching frequency control signal (V t.q). The compensated control signal is provided to the hysteretic self-oscillating comparator 410. The hysteretic self-oscillating comparator 410 provides a switching signal to the power converter circuitry 430, based on the compensated control signal from the compensation circuitry 420, the switching signal driving the power converter circuitry 430.

For the embodiment illustrated in FIG. 4, the power converter circuitry 430 comprises a switched mode power converter, such as a buck converter power stage 435, which generates a Pulse Width Modulated (PWM) signal (Vp1). The power converter circuitry further comprises an output LC filter, and in one embodiment a or higher order LC filter, for example a low-pass 4th order LC filter, which filters the PWM signal to produce an output signal (V(,LJI) for the power supply controller circuitry 400.

Referring now to FIG. 5, there is illustrated feed-forward block 500 according to an embodiment. The feed-forward block 500 comprises a transistor, such as a junction gale field effect transistor (JFET) 510, which functions as a voltage-controlled resistor. The JFET 510 is operably coupled in series between a resistor 520 and ground, and as such forms a part of a voltage divider circuit with the resistor 520.

Feed-forward block 500 further comprises a capacitor 530, operably coupled in parallel with the JFET 510. As will be appreciated by a skilled artisan, varying V produces a variable voltage division ratio across the resistor 520 arid JFET 510, as well as a variable pole location, since the circuit time constant is set by the parallel value of the resistances of the JFET 510 and resistor 520 and the value of capacitor 530.

Referring now to FIG. 6, there is illustrated feed-forward block 600 according to an alternative embodiment. As will be appreciated by a skilled artisan, the feed-forward block 600 of FIG. 6 is a simplified version of the feed-forward block of FIG. 5, comprising a JFET 610 operably coupled in series between a resistor 620 and ground.

Referring now to FIG. 7, there is illustrated feed-forward block 700 according to a further alternative embodiment. The feed-forward block 700 comprises a PID compensator 710. A JFET 720, functioning as a voltage-controlled resistor, is provided in series with a capacitor 730 to produce a zero at a variable frequency.

Functionally, this means that the high-frequency gain of the block can be controlled via the JFET gate. This, in turn (in a hysteretic self-oscillating controller), provides control over the carrier signal slope and, thus, the switching frequency of the loop.

Referring now to FIG. 8, there is illustrated feed-forward block 800 according to a still further alternative embodiment. The feed-forward block 800 comprises a PID compensator 810. A JFET 820, functioning as a voltage-controlled resistor, is provided as an input resistor for the PID compensator 810, thereby producing a variable gain for the PID compensator 810.

Referring now to FIG. 9, there is illustrated a power supply controller circuit 900 according to an alternative embodiment. The power supply controller circuit 900 comprises oscillation circuitry 910, in a form of a hysteretic self-oscillating comparator. The power supply controller circuit 900 further comprises compensation circuitry 920, and power converter circuitry 930 operably coupled to an output of the hysteretic self-oscillating circuitry 910.

The compensation circuitry 920 comprises gain compensation circuitry, and receives as an input a required output envelope voltage signal (V1), and control loop feedback from an output of the power converter circuitry 930, via control ioop feedback circuitry 950. The required output envelope voltage signal (Ve,) and the control loop feedback may be added together, or otherwise processed, to produce an error signal.

The power supply controller circuit 900 further comprises switching frequency controller logic 940, arranged to control the switching frequency of the power supply controller circuitry 900 based on switching frequency feedback from the output of the hysteretic self-oscillating circuitry 910. In particular, the switching frequency compensation circuitry 940 generates a switching frequency control signal (sw_frq), based on an output of the hysteretic self-oscillating circuitry 910 and a reference signal (Ret). For the embodiment illustrated in FIG. 9, the switching frequency controller logic 940 provides the switching frequency control signal (sw_frq) to the hysteretic self-oscillating circuitry 910.

In this manner, the hysteretic self-oscillating circuitry 910 provides a switching signal to the power converter circuitry 930, based on the compensated control signal from the compensation circuitry 920, and having a switching (oscillating) frequency based on the switching frequency control signal (sw_frq) from the switching frequency controller logic 940.

Referring now to FIG. 10, there is illustrated an example of power supply controller circuit 1000 in accordance with the embodiment of FIG. 9. The power supply controller circuit 1000 comprises oscillation circuitry, again in a form of hysteretic self-oscillating comparator 1010, compensation circuitry 1020 arranged to provide a compensated control signal to hysteretic self-oscillating comparator 1010, and power converter circuitry 1030 operably coupled to an output of hysteretic self-oscillating comparator 1010.

For the embodiment illustrated in FIG. 10, the compensation circuitry 1020 comprises PID controller circuitry 1025. The PID controller circuitry 1025 receives as an input a required output envelope voltage signal and control loop feedback from the output of the power converter circuitry 1030, via control loop feedback circuit 1050. The PID controller circuitry 1025 produces an error signal from the required output envelope voltage signal (V1) and the control loop feedback, which is provided to the hysteretic self-oscillating comparator 1010.

The power supply controller circuit 1000 further comprises switching frequency controller logic 1040, operably coupled to the output of the hysteretic self-oscillating comparator 1010. The switching frequency controller logic 1040 comprises a Monostable Multi-Vibrator (MMV) 1042, which receives, as an input, the output signal from the hysteretic self-oscillating comparator 1010. The MMV 1042 generates a square or rectangular wave signal representative of the switching frequency of the output of the hysteretic self-oscillating comparator 1010. The square or rectangular wave signal generated by the MMV 1042 is provided to an integrator 1045, along with a switching frequency reference signal (Vri). The integrator 1045 generates a hysteretic and switching frequency control signal, which for the illustrated embodiment is provided to a first hysteretic input (-V,) of comparator 1010. The hysteretic and switching frequency control signal is also inverted, by inverter 1047, and provided to a second hysteretic input (+V11,,t).

Functionally, this circuit ensures a hysteresis window where the positive and negative hysteresis thresholds change symmetrically (substantially avoiding errors being forced into the carrier signal DC operating point). The integrator ensures that the under steady-state conditions are substantially no different between the switching frequency reference signal (Vrct) and the average of the MMV output. Since the average MMV output is proportional to the actual switching frequency, this means that the converter switching frequency is determined by V1 Referring now to FIG. 11, there is illustrated a power supply controller circuit 1100 according to an alternative embodiment. The power supply controller circuitry 1100 comprises oscillation circuit 1110, compensation circuitry 1120 arranged to provide a compensated control signal to the oscillation circuitry 1110, and power converter circuitry 1130 operably coupled to an output of the oscillation circuitry 1110. For the embodiment illustrated in FIG. 11, the oscillation circuilry 1110 comprises a comparator.

The compensation circuitry 1120 comprises controllable phase-shift compensation circuitry, and receives, as an input, a required output envelope voltage signal and control loop feedback from the output of the power converter circuitry 1130, via control ioop feedback circuitry 1150. The required output envelope voltage signal (V,) and the control loop feedback may be added together, or otherwise processed, to produce an error signal.

The compensation circuitry 1120 is operably coupled to an output of the phase-shift-type self-oscillating circuitry 1110 via switching frequency controller logic 1140. The switching frequency controller logic 1140 generates a switching frequency control signal (V hq), based on the output of the phase-shift-type self-oscillating circuitry 1110 and, for the illustrated embodiment, a reference signal (Ref).

This switching frequency control signal) is provided to the compensation circuitry 1120.

The compensation circuitry 1120 generates the compensated control signal based on the error signal, from the required output envelope voltage signal and the control loop feedback, and the switching frequency control signal (V h(i). In particular, the compensated control signal is generated to compensate for any discrepancy between the required output and the actual output from the power converter circuitry, whilst also compensating for a variation of switching frequency, such that the switching (oscillating) frequency of the output signal from the phase-shift-type self-oscillating circuitry 1110 remains substantially constant, or at least within a predetermined range.

Referring now to FIG. 12, there is illustrated an example of power supply controller circuit 1200 in accordance with the embodiment of FiG. 11. The power supply controller circuit 1200 comprises oscillation circuitiy, in a form of a comparator 1210, compensation circuitry 1220 arranged to provide a compensated control signal to the comparator 1210, and power converter circuitry 1230 operably coupled to an output of the comparator 1210.

For the embodiment illustrated in FIG. 12, the compensation circuitry 1220 comprises PID controller circuitry 1225 and feed-forward block 1260. The PID controller circuitry 1225 receives, as an input, a required output envelope voltage signal (V(Sl\), and control loop feedback from an output of the power converter circuitry 1230, via control loop feedback circuitry 1250. The PID controller circuitry 1225 produces an error signal from the required output envelope voltage signal (V) and the control loop feedback, which is provided to the feed-forward block 1260.

The compensation circuitry 1220, and more particularly for the illustrated embodiment the feed-forward block 1260, is operably coupled to an output of the comparator 1210, via switching frequency controller logic 1240. The switching frequency controller logic 1240 comprises frequency-to-voltage conversion logic 1245, which receives the output signal from the comparator 1210, and converts the switching (oscillating) frequency of the received signal into a voltage value representing the switching frequency. The voltage value is then provided to the switching frequency compensation circuitry 1247, along with a switching frequency reference signal (Vrt). The switching frequency compensation circuitry 1247 generates a switching frequency control signal &q), which is provided to the compensation circuitry 1220, and more particularly for the illustrated embodiment the feed-forward block 1260.

The feed-forward block 1260 generates the compensated control signal based on the error signal from the PU) controller circuitry 1225 and the switching frequency control signal,). The compensated control signal is provided to the comparator 1210. The comparator 1210 provides a switching signal to the power converter circuitry 1230, based on the compensated control signal from the compensation circuitry 1220 and the switching signal driving t he power converter circuitry 1230.

The power supply controller circuits described herein, in accordance with various embodiments of the present invention, allow the switching frequency of self-oscillating power converters to be controlled, thereby substantially removing the inherent disadvantage of a variable switching frequency associated with known self-oscillating control solutions. Furthermore, the power supply controller circuits allow a simpler implementation of the hysteretic comparator, when compared to prior art solutions.

Referring now to FIG. 13, there is illustrated an example of a switching frequency reference signal (Vr&) source, for example a source suitable for the embodiment of FIG. 12. The V source comprises a Phase Locked Loop (PLL) based frequency control, which for the example illustrated in FIG. 13, consists of a Phase-Frequency Detector (PFD) 1310 and a PLL compensator 1320. As will be appreciated by a skilled artisan, a PFD is a device that compares the phase of two input signals, which for the illustrated embodiment is in a form of an output of the comparator 1210 and an external clock signal. An output of the PDF 1310 is provided to the PLL compensator 1320, which generates V(. The PLL compensator 1320 may comprise a P1 compensator.

Referring now to FIG. 14, there is illustrated an example of the power supply controller circuit 1200 of FIG. 12 comprising an alternative switching frequency controller logic 1440. For the embodiment illustrated in FIG. 14, the frequency controller logic 1440 comprises a Phase Locked Loop (PLL) based frequency control, which consists of a Phase-Frequency Detector (PFD) 1410 and a PLL compensator 1420. The inputs of the PFD 1410 comprise the output of the comparator 1210 and an external clock signal. An output of the PDF 1410 is provided to the PLL compensator 1320, which generates V. The PLL compensator 1320 may comprise a PT compensator.

For each of the embodiments of FIG's. 13 and 14, the PLL based frequency control synchronises the sensed switching frequency of the VFTPS (the output of the comparator 1210) with an externally provided reference clock. In particular, for the embodiment illustrated in FIG. 13, a nested frequency locked loop allows phase-accurate locking of the switching action of the self-oscillating converter to an external clock. As will be appreciated by a skilled artisan, the sensed switching frequency may be taken from other locations within the UFTPS, such as the PWM signal output of the power stage (Vpwm).

In the foregoing specification, specific embodiments have been described.

however, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the invention as set forth in the claims below.

By way of example, switching frequency controller logic may comprise a digital signal processor or a phase locked ioop circuit to phase-lock the PWM signal to an external clock. Furthermore, the power converter circuitry and compensation circuitry are not limited to those illustrated in the accompanying drawings or as described herein. For example, the power supply controller circuitry may comprise a power topology with a 4th order LC filter, and a more elaborate feedback network.

Accordingly, the specification and figures arc to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present teachings. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.

Moreover in this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms comprises,' comprising,' has', having,' includes', including,' contains', containing' or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, includes, contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by comprises. . .a', has. . .a', includes -. .a', contains. . . a' does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises, has, includes, contains the element. The terms a' and an' are defmed as one or more unless explicitly stated otherwise herein. The terms substantially', essentially', approximately', about' or any other version thereof, are defined as being close to as understood by one of ordinary skill in the art. The term coupled' as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is configured' in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim.

Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.

Claims

What is claimed is: I. A power supply controller circuit comprising oscillation circuitry, compensation circuitry arranged to provide a compensated control signal to the oscillation circuitry, and power converter circuitry operably coupled to an output of the oscillation circuitry; wherein the power supply controller circuit is characterised by switching frequency controller logic operably coupled to the compensation circuitry and arranged to control a switching frequency of the power supply controller circuit based on at least a switching frequency feedback signal from an output of the oscillation circuitry.
2. The power supply controller circuit of Claim 1 further characterised by the switching frequency controller logic being arranged to generate a switching frequency control signal, based on at least the output of the oscillation circuitry.
3. The power supply controller circuit of Claim 2 further characterised by the switching frequency controller logic being arranged to generate the switching frequency control signal based further on a reference signal.
4. The power supply controller circuit of Claim 3 further characterised by the switching frequency control signal being provided to the compensation circuitry, and the compensation circuitry generating the compensated control signal based at least on an error signal and the switching frequency control signal.
5. The power supply controller circuitry of Claim 4 further characterised by the compensation circuitry comprising feed-forward block arranged to generate the compensated control signal based on at least the switching frequency control signal.
6. The power supply controller circuit of Claim 5 further characterised in that the feed-forward block generates the compensated control signal based further on an error signal, the error signal being produced by the compensation circuitry from an output envelope voltage signal and control loop feedback.
7. The power supply controller circuit of Claim 5 or Claim 6 further characterised by the feed-forward block comprising a transistor arranged to function as a voltage-controlled resistor, and forming part of a voltage divider circuit.
8. The power supply controller circuit of Claim 5 or Claim 6 further characterised by the feed-forward block comprising a Proportional-Integral-Derivative compensator, and a transistor arranged to function as a voltage-controlled resistor, the transistor being provided in series with a capacitor to produce a zero at a variable frequency for the Proportional-Integral-Derivative compensator.
9. The power supply controller circuit of Claim 5 or Claim 6 further characterised by the feed-forward block comprising a Proportional-Integral-Derivative compensator, and a transistor arranged to function as a voltage-controlled resistor, the transistor being provided as an input resistor for the Proportional-Integral-Derivative compensator.
10. The power supply controller circuit of Claim 3 further characterised by the switching frequency control signal being provided to the oscillation circuitry, and the oscillation circuitry arranged to provide a switching signal to the power converter circuitry, based on the compensated control signal from the compensation circuitry.
11. The power supply controller circuit of any preceding claim further characterised by the switching frequency controller logic comprising frequency-to-voltage conversion logic and switching compensation circuitry.
12. The power supply controller circuit of Claim 11 wherein the frequency-to-voltage conversion logic receives the output signal from the oscillation circuitry and converts the switching frequency of the received signal into a voltage value representing the switching frequency.
13. The power supply controller circuit of Claim 12 wherein the voltage value is provided to the switching frequency compensation circuitry, together with a switching frequency reference signal, which together generate a switching frequency control signal.
14. The power supply controller circuit of any preceding claim further characterised by the switching frequency controller logic comprising a Monostable Multi-Vibrator and a comparator.
15. The power supply controller circuit of Claim 14 wherein the Monostable Multi-Vibrator receives as an input an output signal from the oscillation circuitry and generates in response thereto a signal representative of a switching frequency of an output of the oscillation circuitry.
16. The power supply controller circuit of Claim 15 wherein the signal is provided to the comparator, along with a switching frequency reference signal such that the comparator generates a switching frequency control signal.
17. The power supply controller circuit of any preceding claim further characterised by the switching frequency controller logic comprising a digital signal processor.
18. The power supply controller circuit of any preceding claim further characterised by the switching frequency controller logic comprising a phase locked loop circuit.
19. The power supply controller circuit of Claim 14, Claim 15 or 16 further characterised by the comparator being arranged to generate a hysteretic and switching frequency control signal.
20. The power supply controller circuit of any preceding claim further characterised by the oscillation circuitry comprising a hysteretic self-oscillating comparator.
21. The power supply controller circuit of any preceding claim further characterised by the compensation circuitry comprising gain compensation circuitry.
22. The power supply controller circuit of any preceding claim further characlerised by the compensation circuitry comprising Proportional-Integral-Derivative controller circuitry.
23. The power supply controller circuit of any preceding claim further characterised by the compensation circuitry comprising a comparator.
24. The power supply controller circuit of any preceding claim further characterised by the compensation circuitry comprising phase- shift compensation circuitry.
25. The power supply controller circuit of any preceding claim further characterised by the power converter circuitry comprising a switched mode power converter.
26. The power supply controller circuit of Claim 25 further characterised by the power converter circuitry comprising a buck converter power stage.
27. The power supply controller circuit of any preceding Claim further characterised by the power supply converter circuiti-y comprising an output LC filter 0f2h1d or higher order.
28. The power supply controller circuit of Claim 27 further characterised by the output LC filter comprising a low-pass 4111 order LC filter.
29. An integrated circuit comprising the power supply controller circuit of any preceding claim.
30. A wireless communication unit comprising the power supply controller circuit of any ofpreceding Claims I to 28.
31. The wireless communication unit of claim 30 wherein the wireless communication unit is arranged to support Terrestrial Trunked Radio (TETRA) Radio communication.