GB2448758A

GB2448758A - A switching power converter with reduced collector dv/dt

Info

Publication number: GB2448758A
Application number: GB0708198A
Authority: GB
Inventors: Vinod A Lalithambika; Russell Jacques; Paul Thomas Ryan; David Michael Garner
Original assignee: Cambridge Semiconductor Ltd
Current assignee: Cambridge Semiconductor Ltd
Priority date: 2007-04-27
Filing date: 2007-04-27
Publication date: 2008-10-29
Also published as: GB0708198D0; WO2008132512A1

Abstract

The rate of change of the collector voltage of the main power switch 208 in a switching converter is limited by a feedback circuit which reduces the base drive current. The slope of the collector voltage waveform is sensed by a capacitor 400 coupled to the small resistance of a switch 406 in a driver IC. Limiting dv/dt at turn-on reduces capacitive load charging transients which could be mistaken for overload currents. Limiting dv/dt at turn-off reduces RFI and decreases voltage transients which could cause damage. The switch 406 shorts out a second capacitor which divides the voltage sensed by capacitor 400 during operation of a feedback saturation control circuit (figure 4). Limiting dv/dt at turn-on reduces current flowing through the small switch 406 and the earth pin of the control IC. The rate of change of the collector voltage may alternatively be controlled indirectly by feedback regulation of the collector current (figure 33). The charge storage time of a BJT or IGBT may be measured and used to vary the base or gate drive in subsequent cycles (figures. 35 and 36).

Description

Power Converters

FIELD OF THE INVENTION

This invention relates to power converters, and more particularly to protection systems for such converters, including current limiting techniques.

BACKGROUND TO THE INVENTION

In a switching power converter broadly speaking a magnetic energy storage device, in many cases a transformer, is used to cyclically transfer energy from an input to an output of the converter by switching power through the device. The converter may be a forward converter, when power is transferred to the output when the switch is on, or a flyback converter when power is transfelTed when the switch is off. A range of power switching devices may be employed including, but not limited to, a bipolar junction resistor (BJT), an insulated gate bipolar transistor (IGBT) and a MOSFET.

Often the magnetic energy storage device (transformer) has significant self-capacitance, which can cause large capacitive currents to flow when the switch is turned on. This is particularly a problem in resonant converters, especially where a resonant capacitor is included in the power converter. Some of the sensing techniques we describe later also employ a coupling capacitor, and again this can result in relatively large currents when the power switch is turned on.

One problem that can arise from the flow of relatively large currents is that such a current may be mistaken for an overload current. Another problem that can arise, in particular where the power converter incorporates a power controller integrated circuit (IC), is that current flowing through a ground connection of the IC can result in "ground bounce" which can affect the operation of the IC. The IC, more particularly the die, should also be sufficiently large to handle these current flows.

Control of dV/dt can also be useful at the instant of turnoff of the switch. At turnoff there is typically a fast rise of switch voltage caused by current flow in circuit inductance and transformer leakage inductance. In some configurations this fast rise of voltage can be troublesome particularly where it causes a large rise of voltage. A fast rise of voltage can cause unwanted radio frequency interference and a large rise of voltage can be destructive to the switch or other components of the circuit.

SUMMARY OF THE INVENTION

According to the present invention there is therefore provided a switching power converter, said power converter having an input to receive an input power supply, an output to provide an output power supply, a magnetic device having at least one winding, said magnetic device being coupled between said input and said output, and a switching device coupled to switch power from said input on and off to said winding of said magnetic device to transfer power from said input to said output, and wherein said switching power converter further comprises a dv/dt limiting circuit to limit a rate of change of a voltage across said winding of said magnetic device when said switching device is turned on or off.

Broadly speaking by limiting the rate of change of voltage (with time) when the switching device is turned on the capacitive currents flowing in the power converter can be reduced, thus ameliorating the aforementioned problems. The limiting may be either hard limiting or soft limiting. Also, if the rate of rise of switch voltage is limited when the switching device is turned off then, in embodiments, the energy dissipated from the circuit and leakage inductance does not appear as a high switch voltage but is instead dissipated in the switch itself.

In some embodiments the dv/dt limiting circuit comprises a dv/dt sensing circuit to sense the rate of change of voltage across the winding of the magnetic device (which in embodiments comprises a transformer). In other embodiments, in particular those employing a bipolar switching device such as a BiT, a current in the primary circuit (from the input power supply) is sensed. When the voltage across the winding, in embodiments the collector voltage of the BJT, changes rapidly, current flows through the switching device as a consequence of capacitance associated with the winding (rather than because of the inductance of the winding). This capacitance may comprise, for example, the selfcapacitance of the winding and/or additional capacitance added across the winding, say, for resonance. In the case of a BiT this (collector) current may be related to a base drive current by the gain of the transistor. In embodiments the dv/dt limiting circuit also includes a control circuit to control a drive (voltage or current) to the switching device in response to the sensed rate of change of voltage.

In embodiments the rate of change of voltage is sensed by sensing a current passing through a capacitor coupled to the winding using a current sense circuit which may comprise, for example, a resistance connected in series with the capacitance to convert a current through the capacitor to a voltage. This resistance may comprise, for example, a MOSFET. The capacitor used for dv/dt sensing may also be employed to sense a voltage on the switching device for controlling a drive to the switching device, for example to control saturation of the device. Thus in embodiments this capacitor may serve two purposes.

in some preferred embodiments the control circuit has an offset such that the drive to the switching device is adjusted to slow the turn on or turn off of the switching device in response to the sensed rate of change of voltage exceeding a level set by the offset.

Thus, broadly, if the sensed rate of change of voltage is too high the drive is adjusted (reduced) to reduce this. The offset may, for example, comprise a bias voltage or maybe "built-in" for example using the threshold voltage of an FET.

In embodiments a circuit such as a current generator is employed to apply an initial, forcing drive to the switching device when the switching device is turned on. The control circuit may then be configured to control a level of this initial, forcing drive.

In embodiments where, as mentioned above, the dv/dt limiting circuit comprises a current sensing circuit, this may include a current sensing resistor employed to control an output current limit of the power converter. A signal (voltage) derived from the sensed current may be compared with a reference and the comparison (difference) used to control a drive to the switching device. Thus for example in embodiments where the switching device comprises a bipolar junction transistor a transconductance error amplifier may be employed to control the base drive to the BJT dependent on a difference between the sensed current and the reference.

In a related aspect the invention provides a method of limiting a current flow in a capacitance of a switching power converter, said power converter having an input to receive an input power supply, an output to provide an output power supply, a magnetic device having at least one winding, said magnetic device being coupled between said input and said output, and a switching device coupled to switch power from said input on and off to said winding of said magnetic device to transfer power from said input to said output, the method comprising limiting a rate of change of a voltage across said winding of said magnetic device when said switching device is turned on or off to limit said current flow through said capacitance.

The capacitance in which culTent flow is limited may comprise any capacitance the charge on which is changed by operation of the power switching device including, but not limited to, self-capacitance of the magnetic device, a resonant capacitance coupled in series or in parallel with the winding, and a voltage sensing capacitance.

The invention further provides a method of controlling current flow through a pin of a power converter controller integrated circuit (IC) employing a method as described above to limit a current flow through a capacitance coupled to the IC and/or charged or discharged by operation of the power switching device.

BRIEF DESCRiPTION OF THE DRAWiNGS

These and other aspects of the invention will now be further described, by way of example only, with reference to the accompanying figures in which: Figures Ia shows a typical high voltage NPN transistor and Figure lb shows a characteristic curve of the high voltage NPN transistor of Figure la; Figures 2a and 2b show, respectively, a circuit for a power converter and an example of a discontinuous resonant forward converter; Figure 3a and 3b show, respectively, a diode used as a sensing element and a resistive divider sensing element; Figure 4 shows a preferred capacitive divider based sensing element; Figure 5 shows waveforms for low/high on state currents for the circuit of Figure 4; Figure 6 shows a high bandwidth base drive circuit; Figure 7 shows a set of waveforms for the circuit of Figure 6; Figure 8 shows an embodiment of a low bandwidth base drive circuit; Figure 9 shows waveforms illustrating the operation of the circuit of Figure 8; Figure 10 shows a further example of a low bandwidth base driver circuit; Figure II shows waveforms for high/low on state current for the circuit; Figure 12 shows an embodiment of a leaky peak detector base drive circuit; Figure 13 shows waveforms illustrating the operation of the circuit of Figure 12; Figure 14 shows a further set of waveforms for the circuit of Figure 12; Figure 15 shows an example embodiment of a circuit to implement a leaky peak detector; Figure 16 shows a DC transfer function of the leaky peak detector of Figure 15; Figure 17 shows the approximately exponential decay of a sensed peak detected voltage over time; Figure 18 shows a graph of collector voltage against time; Figure 1 9a and I 9b show, respectively, show an example of pulse amplitude modulation and pulse amplitude modulation illustrating an example of undesired oscillation; Figure 20 shows a PWM base drive scheme; Figure 21 shows a variable slope modulation scheme; Figure 22 shows an example of PFM modulation; Figure 23 shows a preferred embodiment of a control system; Figure 24 shows the trailing edge of the force-on signal synchroniscd with the active clamp signal; Figure 25 shows an implementation of the Leaky Peak controller of Figure 23 Figure 26 shows an embodiment of the differential transconductance amplifier/with limiter (error amplifier); Figure 27 shows a base voltage clamping circuit; Figure 28 shows a timing diagram illustrating a negative magnetizing current at turn-on; Figure 29 shows an embodiment of a negative magnetising current detector; Figure 30 shows an example implementation of the detector of Figure 29; Figure 31 shows a preferred embodiment of a system to control the dv/dt of the collector during the force-on period; Figure 32 shows a circuit described below which can be used to limit the maximum turn on dv/dt by controlling the amount of base current flowing into the BJT; Figure 33 shows a circuit with collector current feedback which can be used to limit the maximum turn on dV/dt; Figure 34a and 34b show, respectively, typical effects of charge storage in BiT and IGBT power switches.

Figure 35 shows an embodiment of a saturation control system based on cyclic measurement of storage time; and Figure 36 shows timing and signals of a system as in Figure 35 for the two conditions a) where the drive is too low and the storage time is less than the target duration and b) where the drive is too high and the storage time is longer than the target duration

1)ETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Broadly speaking we will describe an apparatus and related method for controlling the level of base current to minimise the total losses in the primary switching transistor. In embodiments we control the base drive current to avoid excess stored charge at a desired instant of turn-off, in order to minimise turn-off time. This is done by measuring the collector voltage. Although preferred applications of the techniques we describe are in the field of power converters, the techniques may be used more generally where bipolar transistors are employed for cyclic switching, in particular where it is desired to achieve both a low on-state voltage (collector to emitter) and a fast turn-off.

Hwever such a combination is particularly desirable in power converters, to minimise power losses and to optimise control, for example to limit output current in overload conditions. Use of a bipolar switching resistor in a power converter can provide a significant cost saving as compared with, say, a power MOSFET, but with a bipolar transistor there is a need to manage carefully the on-state conditions.

When using bipolar transistors in switching applications, an important parameter is the quantity of charge in the transistor immediately prior to the intended instant of turn-off.

Excess charge should be cleared from the device before turn-off is completed and if there is a large amount of excess charge this can take a long time and cause additional stresses in the device and in the system. However, if the base current is reduced during the on-period, the onstate voltage increases, causing unwanted power dissipation in the transistor. Insulated-gate bipolar transistors (IGBT) are a variety of bipolar transistor which may be used for power switching applications and also exhibit charge storage.

The tecimiques we describe are applicable to these as well as NPN and PNP junction bipolar transistors. IGBTs may be controlled using a voltage applied to their gate terminal, as opposed to a current applied to the base terminal of a junction bipolar transistor. The following description refers to the use ofajunction bipolar transistor, but the same techniques are applicable to IGBTs; for base drive read gate drive and so forth.

A particular difficulty arises in switching when there is a range of current that has to be sustained by the transistor in the on-state (collector current). At high levels of on-state current it is desirable to provide sufficient base current to keep the on-state voltage low enough -particularly when the current gain of the transistor may be low. If this level of base current is maintained when the on-state current is low, there will be a large amount of excess charge in the transistor which will degrade the turn-off behaviour.

A solution to this problem is to vary the on-state base current in response to the on-state current and/or transistor gain so that the delivered base current is sufficient to support the on-state conditions at low on-state voltage but is not excessive. Figure 2 shows an outline block diagram of a control system with the ability to turn off the bipolar switch quickly at the required time. Charge storage in the transistor makes this difficult. If there is excessive charge in the base, then turn-off time can be veiy long (many microseconds), especially at low collector currents. To provide fast turn off we therefore aim to: * Minimise the excess charge in the transistor i.e. during the on-period apply base current sufficient only to just hold the collector voltage low enough.

* At turn-off, withdraw maximum current out of the base.

if the base drive is varied only according to the on-state collector current, sufficient current should be provided to give satisfactory operation (low on-state voltage) when the transistor has low gain. Variation of gain may result from manufacturing tolerance and/or temperature variation. in practice this is typically a wide range so there is likelihood that there will be significant excess charge at turn-off. Since it is difficult to detennine the gain of a transistor in such a circuit, a preferable method of controlling the base current is in response to the on-state voltage across the transistor (e.g. collector to emitter). if the transistor is provided with a high level of base current then the voltage will be low, conversely, low base current will give a higher on-state voltage. A more

detailed description is given later.

We will describe some preferred embodiments of the invention with particular reference to a common-emitter configuration but the skilled person will understand that corresponding principles can also be applied to common-base operation, by configuring the circuits with base bias, emitter switching and base current (or gate voltage) control.

Referring to Figure 2a, this shows a circuit for a power converter 200 according to an embodiment of the invention, the power converter having (in this instance) an AC input from a grid mains supply 202 which is rectified and smoothed to provide DC power on line 204 to the primary winding of a transformer 206, switched by bipolar transistor 208, QI. The secondary winding of transformer 206 is rectified and smoothed to provide a DC voltage output 210.

A sensing element 212 senses the collector voltage of transistor 208 (Qi) and provides a sensed voltage signal output (Col) on line 213 to a controller 214 which has, as a second input, a reference level, as illustrated a reference voltage VREF. The signal on the Col line has a value which is dependent on the sensed collector voltage and, in embodiments in which the system is implemented on an integrated circuit, may be brought out on a pin of the IC. The controller has an output 216 to a modulator 218 which provides a base drive signal 220 to the base (or gate) of transistor 208 modulated by switch 222, which may for example be implemented using a MOSFET. Switch 222 is controlled by a DRIVE signal from controller 224 which, in the illustrated example, has a sense input 226 also from the collector of transistor 208 but which, in other arrangements, may have a different sensing arrangement, for example sensing DC output 210.

As shown in Figure 2a the base current is controlled by monitoring the voltage at the collector of the BJT (bipolar junction transistor) during the on-time of the primary switch (BJT). The aim of the Proportional Base Driver (PBD) is to control the amount of base current so that the voltage at the collector pin is set equal to the threshold voltage (VREF) just before turn-off. It is possible to set the collector "set point" above or below the quasi-saturation limit (see later). If the transistor collector voltage is controlled to be within quasi-saturation then the on-state power dissipation is low but the charge storage can be significant. Conversely, if set above quasi-saturation, storage is low and turn-off is quick. Depending on the application, the threshold may be set to balance the acceptable on-state voltage against the excess stored charge, and, hence, turn-off characteristics.

In power converter applications the range within which it is desirable to maintain the base (or gate) drive depends on the transistor characteristics but is typically 0.3 to 2V for low voltage transistors (<I OOV) and increases with transistor voltage and capability to perhaps 8V in high voltage applications.

Since the proportional base driver (PBD) system comprises a feedback loop it can suffer from instability. There are several source of gain and phase shift that can contribute to this: transistor gain and 1; transistor base-collector capacitance; transistor collector load impedance; controller input impedance; and controller circuit's gain and phase.

Nominally the transistor is in an inverting configuration; however substantial phase shifts can occur at relatively low frequencies. Hence care is preferably taken in the design of this feedback loop (and some particularly preferred arrangements are described later).

Referring now to Figure 2b, this shows an example of a discontinuous resonant forward converter 250 in the context of which embodiments of the teclmiques we describe may be employed.

Referring to Figure 2b, the converter 250 has a dc input 252 coupled to the primary winding 254 of a transformer 256, connected in series with a power switch 262. A resonant capacitor 264 is connected across the primary winding of the transformer and the de input 252 is provided with a smoothing capacitor 266. On the output side of the forward converter a secondary winding 258 of the transformer provides power to a pair of dc output terminals 268 via a rectifier 275. A smoothing capacitor 272 is connected across the dc output terminals 268 and an output node at the junction of rectifier 275, smoothing capacitor 272 and a connection to one of the dc output terminals 268 is denoted "X". The current into node X, which flows to either or both of the smoothing capacitor 272 and output 268, is discontinuous.

In general the switch 262 may comprise a bipolar or MOS transistor such as a MOSFET, or IGBT, or some other device. However in the context of Figure 2a the switch is implemented using bipolar transistor 258 (Qi) in conjunction with turn-off switch 272 (which is preferably a MOS transistor, but may be a bipolar transistor).

The rectifier 275 may be implemented as a diode or by means of a MOS transistor. The resonant capacitor 264 may either comprise a discrete component, or may be entirely provided by parasitic capacitance, or may comprise a combination of the two.

The switch 262 is controlled by a controller 260 comprising a timing control module 260a and a switch control module 260b, the timing control module providing switch on and switch off signals 260c to the switch control module 260b. The timing control module may have one or more sense inputs, such as a voltage sense input and a culTent sense input as illustrated, or such sensing may be omitted and the timing control module 260a may operate substantially independently of any sensed condition of the forward converter circuit.

Where voltage sensing is employed the voltage on the primary winding of the transformer may be sensed, either directly or indirectly; for example, a sensing voltage may be derived from an auxiliary winding of the transformer (not shown). Where current sensing is employed this may be conveniently implemented by sensing the voltage across a current sense resistor.

In operation the circuit of Figure 2b converts the input dc voltage, typically relatively high, to an output dc voltage, typically in a range suitable for consumer electronic devices, for example between around 5V and 25V. In some preferred implementations, the dc output is isolated from the dc input as shown; in other implementations secondary side feedback may be employed, in which case an opto-isolator may be included to provide isolation between the primary and secondary sides of the forward converter.

In operation, afler an energy transfer cycle the transformer is reset (so that it is not magnetised or magnetisation is reversed), during the reset phase current flowing in the transformer primary winding in an opposite direction to that in which it flows when switch 262, generally a power transistor, is turned on. The resonant action of the inductance of the transformer primary and capacitor 264 is employed to perform this reset -once switch 262 is turned off there is a half cycle sine wave on the bottom plate of capacitor 264 (waveform 304). The voltage on this bottom plate is driven above the power supply voltage by the action of the inductor so that at the top of the sine wave the voltage across the transformer primary is in the opposite direction to that during forward energy transfer. (At this point there is a relatively high voltage across switch 262, significantly higher than the input voltage, and the switch should therefore be able to sustain such a voltage without breakdown). As the capacitor discharges and the voltage across the switch 262 faIls back to 0 the current flowing in the transformer primary is in the opposite direction to the direction of current flow during a forward energy transfer portion of the power supply cycle and thus the transformer is reset. If the switch is not switched on at this time the resonance continues with a gradually diminishing series of resonant peaks. Preferably the switch 262 is turned on when the voltage across the switch is substantially at a minimum, that is close to OV.

More details of suitable controllers are described in the applicant!s co-pending applications US 11/449,486, US 11/639,827, GB0706132.8, GB0706249.O, GB0706246.6 and GB0706256.5 [and corresponding US applications to these latter three UK applicationsJ, all hereby incorporated by reference in their entirety.

Referring again to Figure 2a, the sensing element measures the collector voltage. The sensing element may be (without limitation): 1. A diode (e.g. as used in a baker clamp) 2. A coupling capacitor and/or divider 3. A resistor and diode clamp The controller can be implemented as (without limitation): 1. Proportional controller (1-ugh bandwidth base driver circuit) 2. Tntegral controller (Low bandwidth base driver circuit with cycle to cycle memory) 3. Proportional integral controller 4. Leaky peak detector base driver circuit (preferred embodiment) Methods for modulating the base current include (without limitation): 1. Pulse Amplitude Modulation (PAM) 2. Pulse Width Modulation (PWM) 3. Variable Slope Modulation (VSM) 4. Pulse Frequency Modulation (PFM) 5. Combinations of the above.

Modified Baker Clamp-based sensor Figure 3a shows a diode used as a sensing element. The diode 300 will turn on when the collector voltage falls below a preset voltage (IREF*R > VREF). The base driver controls the base current to keep the collector voltage close to VREF.

In operation, when transistor 208 is on the voltage on line 213 follows the collector voltage but when the transistor is off the sensed voltage signal is limited to IR1FR.

However if the collector voltage is falling fast capacitive coupling through the diode can pull the voltage on line 213 down.

However this arrangement uses an expensive high voltage diode with a low reverse recovery time. Also the parasitic capacitance of the diode affects the operation at low duty cycles.

Resistor and diode-based sensor Figure 3b shows a resistive divider sensing element. The resistive sensing element comprises a resistor Ri and clamping diodes 304a, b. However a high value of Ri could result in a high RC time constant; the delay introduced could detrimentally affect the operation of control ioop. A low value of Ri could result in large power dissipation across it lowering the efficiency of the controller.

Coupling capacitor and/or divider-based sensor Figure 4 shows a preferred capacitive divider based sensing element. Initially during the drive period the voltage at either side of the capacitor (CcoI) is reset to a known value. Subsequently the voltage at the feedback pin (COL) will follow the collector voltage.

In the sensing circuit of Figure 4, capacitor 400 (Ccol) is used to sense the voltage on the collector of transistor 208 to provide a voltage sense signal on line 213 which is preferably limited to between the supply rails by diodes 402a, b. A capacitor 404 (Cp) coupled to line 213 (and to ground) provides a capacitive divider which can dump some current to ground (when, for example, a high current flows through capacitor 400 in a resonant converter), which can provide scaling, and which can reduce the effects of stray capacitance. Capacitor 404 is optional and may comprise parasitic capacitance.

Switch 406 (SI) can be used to briefly connect the plate of capacitor 400 coupled to voltage sense line 213 to ground (or a voltage source) to reset the voltage on capacitor 400; when switch 406 is open voltage variations on line 213 then follow the collector voltage. Optional switch 408 can be used to apply an initial relatively high base drive (current or voltage) to transistor 208 to turn the transistor on (preferably irrespective of the collector load) and to place the transistor in saturation or quasi-saturation; subsequent variations in the collector voltage of the transistor can then be measured and used to control the base drive to control the degree of saturation of the transistor.

Current source 410 provides an initial force-on current (1FON). Preferably switch 406 is closed before the forcing current is applied to provide a current path to ground. A hold-on switch 412 allows a base drive(current or voltage) to be selectively applied to the base or gate of transistor 208, for example by a drive signal. In embodiments a switch (not shown in Figure 4) may also be provided to isolate the controller from the sensing element 212 when the transistor is off, this is used when the controller 214 includes a memory element which would otherwise be affected when the transistor is off, for example a peak detector or integrator (described further later).

Figure 5 shows waveforms for low/high on state currents for the circuit of Figure 4. At the start of each drive period a high base current (IFON) is applied to the BJT during the force-on period. During this time the COL pin is clamped to ground using a switch (Si).

By the end of the force-on period the collector has fallen to a low voltage (0V) and hence both sides of the capacitors are reset to a low voltage. At the end of the force-on period the switch Si is opened and the COL pin is floating allowing it to follow the changes in collector voltage.

Subsequently, hold-on current is servo controlled to stabilise the collector at a higher voltage, set by the C01/C ratio and VREF. In this condition, base current is provided that is sufficient only just to hold the transistor collector at this voltage. C, is preferably included to allow adjustment of the preset collector voltage according to the requirements of particular transistors or applications.

Some particular advantages of this method include: low power loss, fast response to collector voltage changes; and the capacitor may also be used for resonance in resonant converter topologies.

Collector voltage is measured relative to the initial ("saturation") voltage present at the beginning of the on-period. Where the load is inductive (typical of power converters), it is possible to achieve saturation of the switch for a short period before switch current builds inductively, hence this gives an accurate measure of the achievable on-state voltage. Subsequently, the PBD responds according to the increase of the collector voltage. So, if the initial saturation voltage is higher for a particular transistor, this is taken into account when judging subsequently the degree of saturation. This is helpful when the initial saturation voltage may change as a result of transistor variation (type or individual device), temperature and the like. If the PBD did not take account of this initial saturation voltage, there is a risk that excess base drive may applied if the initial voltage was lower in some conditions. When there is a resistive component to the switch load current, the initial saturation voltage will be higher (see below). Controlling base drive from this reference can also be advantageous in a similar way.

Controllers We now describe various types of controllers that can be used along with their merits and disadvantages. If a controller includes a "history" or memory element, as is the case for example with a peak detector or integrator, then their inputs should be disabled during the off period; optionally they may be enabled for only a part of the on-period.

Proportional controller (high bandwidth base drive circuit) Figure 6 shows a high bandwidth based drive circuit 600 including a proportional controller 602 comprising an error amplifier 604 responsive to a difference between a sensed voltage signal on line 213 and a reference (voltage) 606 to provide a control output 608 for controlling a base (current or voltage) drive system 610. The base drive system 610 may comprise, for example, a pulse amplitude modulation (PAM), pulse width modulation (PWM) or variable shape modulation (VSM) system. In the illustrated embodiment a first switch 612 is provided to switch on a drive to the base or gate of transistor 208 and a second switch 222 is provided to switch off or discharge the drive on the base or gate of transistor 208.

The circuit of Figure 6 is responsive to the absolute collector voltage or to changes in the voltage since the transistor was first saturated or quasi-saturated; the circuit is relatively straightforward and responds quickly to changes in load culTent but can be difficult to make stable, in particular because of time delays in the transistor, sensing and control loop (and reducing the loop gain may be undesirable).

Referring now to Figure 7, this shows a set of waveforms for the circuit of Figure 6 for highllow on state current, in particular for a resonant converter.

The operating sequence of the circuit (see Figure 6) is: 1. Open discharge switch (222) 2. Close the drive switch (612) 3. Open drive switch (612 4. Close discharge switch (222) When the drive switch (612) is closed the collector falls to a low voltage. During the drive period the collector voltage is maintained close to VREF value by the error amplifier. It is difficult to assure stability of this feedback loop; even with a low gain.

For turn-off, it is desirable not only to remove the base current but also to withdraw maximum base culTent, via the turn-off switch.

Advantages of the circuit of Figure 6 include: an optimum base drive within the on-period, and an optimum base drive on cycle-by-cycle basis. Disadvantages include: that it is difficult to make stable (against oscillation), or has low gain, which equates to excessive collector voltage at high load. It is difficult to make fast enough to provide suflicient base drive is applied early enough in high-load conditions. When high on-state current establishes quickly it is important to apply base current as soon as possible.

Because of delays in the switching transistor it may be desirable to apply significant base current before the collector voltage rises significantly; otherwise the voltage may rise too far before the additional base current manifests as increased collector current.

Inte2ral controller (low bandwidth base drive circuit with cycle by cycle memory) Figure 8 shows an embodiment of a low bandwidth base drive circuit 800 with cycle-to-cycle memory. The circuit is similar to that of Figure 6 but uses an integral controller 802 to integrate a difference between a voltage sense signal on line 213 and a (voltage) reference in integrator 804 to provide an integrated error signal which is amplified by (optional) error amplifier 806 before being provided to the base drive system 610. A switch 808 is provided to isolate integrator 804 from the sensed voltage when the transistor is off Broadly the integrator 804 avoids major excursions in the base drive caused by small changes in the sensed voltage, thus facilitating more accurate control at the expense of speed. However by holding a value from a previous switching cycle (substantially isolated from changes in the collector voltage when the transistor is off) the effects of a slow start for the base drive and hence collector current, which is particularly important for inductive loads, can be mitigated.

Figure 9 shows waveforms illustrating the operation of the circuit of Figure 8 fbr highllow on state current. The operating sequence is: 1. Open discharge switch 2. Apply FON (force-on) current (optional) 3. Turn off FON 4. Close the hold-on switch 5. Open hold-on switch 6. Close discharge switch When 1FON (410) current is applied the collector falls to a low voltage. It will be understood that the force-on current is not essential but in embodiments it is preferable, to turn the transistor on quickly. Cycle to cycle memory is provided by the integrator and it determines the amount of base drive during the drive period. During the hold-on period the collector voltage is maintained close to VREF value. The integrator has a response that is slow relative to the speed of the switching transistor so the base-drive current may not track fast load and/or supply variations sufficiently well. For turn-off, it is still desirable not only to remove the base culTent but also to withdraw maximum base current, via the discharge switch.

Advantages are that it is easy to make the circuit stable against oscillation, and that it provides hold-on base drive immediately after force-on, so that high loads can be supported well. However disadvantages are: a slow response to supply or load variations (causing increased power dissipation, or impaired control of timing of power switching). A slow response to change in load during on-state, so may allow excessive on-state voltage if the load current varies during the on-period.

Proportional Integral controller Figure 10 shows a further example of a low bandwidth base driver circuit 1000 with cycle-to-cycle memory, in this example using a proportional and integral controller 1002. This can respond quickly to changes when transistor 208 is on and also has the advantage of being able to store a base or gate drive from a previous cycle. Figure 11 shows waveforms for highllow on state current for the circuit.

The operating sequence is: 1. Open discharge switch 2. Apply FON (force-on) current (optional) 3. Turn off FUN 4. Close the hold-on switch 5. Open hold-on switch 6. Close discharge switch When force-on (408) current is applied the collector falls to a low voltage. The skilled person will understand that the force-on culTent is not essential but in embodiments it is preferable, to turn the transistor on quickly. Cycle to cycle memory is provided by the integrator and it determines the amount of base drive during the drive period. During the drive period the collector voltage is maintained close to VREF value. Addition of the proportional element improves the response to changes in load or supply, both within an on-period and over a sequence of on-periods. For turn-off, it is still desirable not only to remove the base current hut also to withdraw maximum base current, via the discharge switch.

Advantages are an improved response to load or supply changes; the circuit also provides a hold-on base drive immediately after force-on, so that high loads can be supported well. Disadvantages are that it can be difficult to ensure stability against oscillation.

Leaky peak detector base driver circuit Figure 12 shows an embodiment of a leaky peak detector base drive circuit 1200 incorporating the preferred capacitive sensing embodiment of Figure 4 as the sensing element 212. The circuit includes a leaky peak detector 1202 followed by an error amplifier 1204 (which may have a gain of less than or greater than unity) responsive to a difference between a peak detect output from leaky peak detector 1202 and a reference; this represents a preferred embodiment of controller 214 of Figure 2 (the skilled person will understand that error amplifier 1204 may be positioned either before or after leaky peak detector 1202). The active clamp switch 406 provides the function of switch Si in Figure 4 and may comprise a MOSFET.

Details of an embodiment of leaky peak detector 1202 are given later but, broadly speaking, this system allows a component of the input signal to pass through but also functions as a peak detector. Either or both of these components may be employed to control the base or gate drive to transistor 208; the peak detector is leaky so that over time a detected peak value decays away. Broadly the peak detect function maintains a level of base drive so that in a subsequent cycle this base drive is applied soon enough in the on period to sustain heavy loads later. The circuit is particularly responsive to the peak load value, and thus particularly suitable for inductive loads (which tend to present a high load towards the end of the on period, which is where the greatest control is desirable for a rapid switch off of transistor 208. Preferably an element of proportional control is also employed to facilitate a rapid response to excursions in the load.

Although we will describe embodiments of the arrangement with reference to cyclic operation, this drive configuration may also be employed in circuit with an acyclic operation.

Figure 1 3 shows waveforms illustrating the operation of the circuit of Figure 12 for highllow on state current. The operating sequence is: I. Close ActiveClamp switch 2. Open discharge switch 3. Apply FON (force-on) current 4. turn-off ActiveClamp switch 5. Turn off IFON 6. Close hold-on switch 7. Open hold-on switch 8. Turn on ActiveClamp switch 9. Close discharge switch Note that the operation of the circuit of Figure 12 has been described using the preferred "coupling capacitor" sensing method, but could equally be accomplished using other sensing methods.

Continuing to refer to Figure 13, this shows an example (at point A) of a load excursion which results in the collector voltage increasing as the transistor 208 comes out of a quasi-saturated state. As this happens proportional control increases the base drive (current) to respond substantially immediately to the excursion in collector voltage, bringing the collector voltage down and the base drive down again, but to a higher level (because of an increase in the peak detected level); thus the peak detector is also set up in this way for a subsequent cycle. At point B switch 808 is opened to isolate the leaky peak detector 1202 from the sensed collector voltage signal on line 213.

Figure 14 shows a further set of waveforms for the circuit of Figure 12, again illustrating high/low on state current showing another example variation of collector voltage, without the load excursion shown in Figure 13, but with a more realistic illustration of the transition of transistor 208 into saturation.

The description below is in the context of using a capacitively-coupled sensing method.

Other embodiments are possible, for example using other coupling methods, and these may omit the Force-on feature.

When IFON current is applied the collector voltage falls to a low value. Subsequently, hold-on current is servo controlled to stabilise the collector at a higher voltage, set by the C/C ratio and VREF. ln this condition, base current is provided that is sufficient only to just hold the transistor collector at this voltage. Preferably C, is included to allow adjustment of the preset collector voltage according to the requirements of particular transistors or applications. For turn-off, it is still desirable not only to remove the base current but also to withdraw maximum base current, via the turn-off switch.

The hold-on current system is a feedback loop and thus may suffer from instability.

Therefore a technique adopted in a preferred embodiment is to implement a slow control, but with features to make this handle load and line changes more successfully: * Base drive setting is held from one cycle to the next so that the loop need only track cycle-to-cycle changes * If the collector voltage rises (during the hold-on period), the base drive is rapidly increased via peak-detect function * In the absence of rising collector voltage, the base drive is progressively reduced on a cycle-to-cycle basis Thus the "leaky peak detector" refers to the controller function between the sensing element and the modulator. Broadly, its operational principle is: * A storage element holds a value of base drive * The stored value is arranged to decay away to a level corresponding to zero base drive * This decay may be implemented in a variety of ways, as described in more detail below, including (but not limited to): o Constant linear rate against time o Constant exponential rate against time o Linear decay per converter cycle o Exponential decay per converter cycle During the on-period, if the sensed collector voltage rises above the reference, the storage element value is increased (peak detector function). VREF error amplifier provides an error signal to the peak detector and the stored value is increased in response to this error signal. The rate of increase can be controlled in a variety of ways, including (but not limited to): * Fast: the stored value is increased to match the error signal.

* Linear rise: increase the stored value at a predetermined rate * Proportional rate of rise: the stored value is increased at a rate proportional to the difference between the error signal and the present stored value.

Apart from the rise/fall characteristics of the storage element, a further consideration is the signal that is produced to control the immediate base drive. This signal may be produced by techniques which include (but are not limited to): * Use of the present stored value * Use of the stored value with an added contribution from the sensed collector voltage * Use of the stored value or the sensed collector voltage, whichever is the higher The alternative methods have different benefits and drawbacks: Decay niethods Item Benefits Drawbacks Constant linear rate against Simple Poor response when there is time Tracks small variations of a wide range of conditions switching conditions well (too fast at low levels or too slow at high levels of base drive) Response does not vary in accordance with off-period, e.g. may decay too fast if off-period is extended Constant exponential rate Simple Response does not vary in against time Tracks well variations of accordance with off-period, switching conditions over a e.g. may decay too fast if wider range off-period is extended Linear decay per converter Tracks small variations of Poor response when there is cycle switching conditions well a wide range of conditions Accommodates variation of (too fast at low levels or too switching rates, particularly slow at high levels of base where the off-period varies drive) over a wide range Exponential decay per Tracks well variations of converter cycle switching conditions over a wider range Accommodates variation of switching rates, particularly where the off-period varies over a wide range Easy to implement in an integrated circuit using switched-capacitor techniques I Peak detector methods Item Benefits Drawbacks Fast: Responds quickly to May increase the stored increases of the collector value too much (overshoot) voltage during each on-period Linear rise: Lower overshoot than May not respond quickly "fast" method enough to larger increases of collector voltage Proportional rate of rise: Lower overshoot than (preferred) "fast" method In comparison to "linear rise", responds better to larger increases of collector voltage Base drive control signal Item Benefits Drawbacks Present stored value Simple Responds slowly to increasing collector voltage Stored value with an added Responds quickly to If the error signal is below contribution from the increasing collector voltage the stored value, the base sensed collector voltage drive may be reduced which is undesirable in conditions where high on-state switch current establishes quickly Stored value or the sensed Responds quickly to collector voltage, whichever increasing collector voltage is the higher The preferred embodiment is to use an "Exponential decay per converter cycle" for decay and "Proportional rate of rise" for peak detector. Optionally, the error amplifier may precede and/or follow the peak detector and, further, it may be integrated with other functional elements. Those skilled in the art will understand that other combinations of gain and offset functions may also he employed.

The inventors have termed this a "leaky peak detector" technique: Figure 15 shows an example embodiment of a circuit to implement such a leaky peak detector 1202.

Referring to Figure 15 the leaky peak detector 1202 comprises a buffer 1500 followed by a rectifier 1502 coupled to an output 1504 of the leaky peak detector. A combination of a peak detect function and proportional control is provided by a resistor Rpeak 1506 coupled in series with a capacitor Cpcak 1508 to output line 1504. The signal on output line 1504 is the higher of either the sensed collector voltage (the output of diode 1502) or the peak detect function (the voltage on capacitor 1508). However if the sensed collector voltage, more particularly the voltage on line 1504, is greater than that on capacitor 1508 then the rate of rise of voltage on capacitor 1 508 is proportional to the difference between the voltage on this capacitor (the previously detected peak voltage) and the voltage on line 1504 (the sensed collector voltage), the constant of proportionality being determined by the value of resistor 1506. In this way the circuit provides in an elegant fashion a combination of peak detect and proportional control.

An exponential decay of the voltage on capacitor 1508 is provided by switches 1 51 Oa, b and leakage capacitor Cleak 1 512. In operation switches 151 Oa, b are operated to charge capacitor 1512 to a reference, for example VRip, (which may be ground) and then to coimect this capacitor across capacitor 1508 so that they share charge and hence so that the voltage on capacitor 1508, over time, decays to the reference voltage (VREF). The speed of the decay depends upon the relative values of capacitors 1508 and 1512 (preferably capacitor 1512 is much smaller than capacitor 1508), and the rate of operation of switches 151 Oa, b. Preferably the voltage on capacitor 1508 is decayed during the off period of the transistor so as not to affect control during the on period.

In embodiments VpEp may be chosen so that the drive decays exponentially to zero, although VREF could be set lower for a faster return to zero, and hence faster turn-off.

Preferably, however, VREF is chosen so that in the absence of a load the base drive decays to zero. Broadly VREF sets the collector voltage threshold which starts to produce a base drive. This is illustrated in Figure 16 which shows a DC transfer function of the leaky peak detector of Figure 15.

In the example of Figure 1 5 the error amplifier follows the peak detector, but in other embodiments a leaky peak detect may be performed on the error signal.

Thus base current is applied according to the voltage on the holding capacitor Cpeak, compared to VREF. In a leaky peaky (illustrated using a PAM system) the differential amplifier and PA.M are arranged to have a controlled gain and intercept as shown in Figure 16.

If the collector voltage rises above the holding capacitor voltage, the capacitor charges and increased base current is applied. SI and S2 operate in opposition every converter cycle, S 1 is closed during the off-period and S2 is closed during the on-period (but the inverse would also work). The effect of these is to drain charge away from Cpeak according to the voltage of Cpeak above VREF. Figure 17 shows the approximately exponential decay of the sensed peak detected voltage over time.

The decay approximates to an exponent, but with a rate that varies with the converter cycle rate. This is a significant advantage because it works consistently across a range of converter frequencies. In the case of resonant discontinuous converters this is a particular advantage because it caters for tolerance of resonant frequencies and when off-time is varied. Optionally, the reference voltage connected to S2 V(S2) may be different from V REF* For example, if V(S2) is lower than VRFF, the decay aims to ensure that base current is removed when the collector voltage is low. This is advantageous to minimise turn-off time when the system is to operate with very low on-state culTents.

It is important to limit the rate of rise of the peak detector voltage if the collector voltage rises. Typically, if the transistor has insufficient base current to support its increasing load current, the collector voltage rises in two stages as shown in Figure 18.

Figure 18 shows a graph of collector voltage against time (assuming an inductive load so that the collector current increases with time), or equivalently against collector load or current (Ia). In the direction indicated by the arrow the voltage across the internal collector resistance (Re) is increasing whilst the transistor is in the quasi-saturation region indicated (the "internal" transistor remains in saturation). At the knee in the curve the "internal" transistor can no longer sustain the collector current for the given base drive and thus begins to turn off, coming out of saturation (quasi-saturation).

It is possible to set the collector "set point" above or below the quasi-saturation limit, if the transistor collector voltage is controlled to be within quasi-saturation then the on-state power dissipation is low but the charge storage can be significant. Conversely, if set above quasi-saturation, storage is low and turn off is quick. In either case, however, the collector may rise up the steep part of the dc-saturation curve. If the peak detector tracks this, base current can be applied quickly but the transistor delay characteristics may be such that the collector voltage has already risen to a high value and the peak detector has risen correspondingly. Consequently it is possible for the peak detector voltage to rise too high, leading to excessive base current (and consequent charge storage) on subsequent cycle(s). By including a limit to the rate of rise (Rpeak), this effect can be reduced to acceptable levels.

High collector voltage excursions during the on-period, apart from pumping the holding capacitor voltage too high, can also cause problems with the collector coupling capacitor. In the case where the controller is implemented as a CMOS integrated circuit then if the excursion is large then the positive ESD protection diode of the controller input pin may come into conduction. Though this need not cause immediate problems (the ESD diode is normally robust and may be protected by additional external diodes), it causes a change of charge in the collector coupling capacitor. The effect is that subsequently the voltage at the controller may indicate adequate collector voltage saturation whereas the collector voltage is actually high. To avoid this in normal operation, it is desirable to apply extra base current as fast as possible when there is a collector voltage excursion. For this reason the error amplifier takes its signal from before Rpeak, rather than after.

It is desirable to be careful about the timing and magnitude of the force-on pulse; there are several considerations: * Current should be sufficiently high to provide saturation under all expected collector load conditions * Current should be high enough to provide fast turn-on, even if the collector (on-period) load is very light * Charge in the pulse should not be excessive as this can give unacceptable charge storage in conditions of light on-period load, even if the hold-on current is zero.

A particular issue results from the bipolar turn-on characteristic in relation to quasi-saturation. When force-on current is applied, the transistor conducts very quickly, but the lightly-doped extended collector region presents a high resistance until it fills with charge by diffusion from the base. This means that the collector voltage is low only if the collector current is low. As charge fills the extended region, the transistor can support higher currents at low collector voltages. For the proportional base drive to operate effectively the Ccol capacitor should be discharged "correctly" i.e. The collector voltage is representative of "saturation" at the time when the ActiveClamp switch is turned off. If the force-on pulse is short (desirable for minimising excess charge when the load is light); typical HV transistors can support only low currents at low Vce in this time (few I OOs of ns). Tn power converters, within this timescale the collector load is predominantly inductive. When force-on current is applied, there is a capacitive current pulse through Ccol and other parasitic circuit capacitance but this lasts only a few lOs of ns. After this, the transformer inductance dominates. It is not a pure inductance, having appreciable loss, but is predominantly inductive. Provided the ActiveClamp switch is turned off before inductive current rises to far/fast, Ccol can be discharged to an appropriate voltage. The important case is when there is heavy load/overload on the converter; Collector current can rise very quickly and there is a narrow time window to turn off ActiveClamp after the collector has fallen (limited by capacitances), but then rises again (as inductive current builds). Modulators The modulator module 218 of Figure 2 delivers base drive to

the power switching transistor in response to the signal provided by the controller. Depending on the sensing method either one or two phases are needed in the application of the base current.

With a "coupling capacitor" sense method: Preferably, so that the capacitor is reset to represent the initial saturation voltage of the power switch transistor, it is desirable to "force on" the transistor with an initial high current ("force-on" or" FUN" phase) Once the voltage of the coupling capacitor has been preset, a "hold-on" phase is entered subsequently where the base drive is varied in response to collector voltage. Preferably, the duration of the FON phase is minimised to prevent excess charge being applied to the base.

With a "diode" or "resistor" sensing method: Only the hold-on phase (as above) need be employed. However it may be an advantage to have a short prior FUN phase to provide fast turn-on, minimising power dissipation as the collector voltage falls.

In the context of using the "coupling capacitor" sensing method, during the force-on period a large current is applied to the base. During this period the collector voltage falls to a low value. Following this during the hold-on period the base current is modulated so that the collector voltage is held at a value so that during turn-off the storage time is minimised. Various modulation techniques can be used and are described in this section.

Pulse Amplitude Modulation (PAM) the preferred embodiment Figure 19a shows an example of pulse amplitude modulation, implemented for example by PAM system 610, a preferred embodiment of modulator 218. In this pulse amplitude modulation scheme the amplitude of the base current is varied in response to the output of the controller. If the gain of the controller is high then a response similar to the one as shown in figure 1 9b is obtained showing (undesired) oscillation of the base (or gate) drive.

Pulse Width Modulation (PWMj Figure 20 illustrates a PWM base drive scheme. In this pulse width modulation scheme the width of the base current is varied in response to the output of the controller.

Optionally, a different current level may be used fbr the force-on period and the variable-width period.

In this method, a variable charge is sent to the base by varying the time for which a (substantially) fixed base current is applied. Once the base current is stopped, the transistor is maintained in the on state by its stored charge. Generally this is effective provided the transistor is to be maintained in the on state only for a short time (typically less than approximately 20 microseconds), Charge is lost via a number of mechanisms, including: * To support base current needed as a result of the finite current gain of the transistor * Recombination of charges * Leakage As the time interval between turn-off of the base current and termination of the on-period increases, charge is lost to mechanisms other than collector current/gain. Hence the "efficiency" of base drive reduces, since an increased average base drive is used to support a given on-state current. The loss of efficiency depends on transistor construction, temperature, on-state current and the like.

At the end of the desired on period, the transistor may turn off as a result of decay of stored charge. However this is typically slow and causes power loss. Preferably, faster turn-off is achieved by taking current from the base, under control of a base turn-off pulse.

This method also applies to IGBTs but there is no method to withdraw charge at the end of the on-period.

The advantage of this technique is that it is simple to implement as an integrated circuit, particularly when using digital techniques to control timing. Apart from the efficiency of base drive noted above another shortcoming is in situations where the on-stale current increases during the on-period (e.g. inductive load). In such cases, the base drive and stored charge is minimum at the end of the desired on-period, when the on-state current is highest. This may give rise to unacceptably high on-state voltage.

Variable Slope Modulation (VSM) Figure 21 illustrates a variable slope modulation scheme. In this variable slope modulation scheme the fall time of the base current is varied in response to the output of the controller. Optionally, the fall time of current may be kept constant but the variable quantity is the trigger time at which the fall commences. In comparison to "pulse width modulation" this technique improves the drive efficiency and performance with inductive loads, but is not as effective as pulse amplitude modulation. It can help sustain a high collector current towards the end of the on period as a base (or gate) drive is still present (contrast PWM). The slope and slope commencement point of the waveform may be varied as control parameters.

Pulse freQuency modulation (PFM) Figure 22 shows an example of PFM modulation. As illustrated, the frequency of the pulses is varied in accordance with variation in the control voltage. The amplitude of the pulses in the hold-on period need not be the same as the amplitude of pulses in the force-on period.

As illustrated in Figure 22, if the pulses are relatively narrow only a relatively small quantity of charge is delivered to the base (or gate) of the bipolar transistor in each pulse which facilitates a rapid turn off Preferably the pulses are fixed width, although a pulse width may be varied. The rate of pulses may he proportional to an error signal as previously described.

Combinations of methods Combinations of the above methods may also be employed. For example PAM and PWM and slope modulation could be combined, say, for increased dynamic range. In general a potential advantage of combination of techniques is to provide a wider range of control and to reduce the problems associated with inductive loads.

Leaky peak detector with PAM modulation Figure 23 shows a preferred embodiment of a control system including preferred embodiments of sensing element 212, controller 214 and modulator 218 of Figure 2. In particular capacitor-coupled based sensing is shown in Figure 4, a leaky peak detector controller as shown in Figures 12 and 15, and pulse amplitude modulation as shown in Figure 1 9a. Like elements to those shown in these figures are indicated by like reference numerals.

in the illustrated prefelTed embodiment the error amplifier is implemented using a (differential) transconductance amplifier, preferably with a limiter, and this drives a current mirror 2302 providing a current drive to the base of transistor 208 (in an TGBT-based embodiment a voltage drive is employed). A timing generator 2304 is used to generate a set of drive circuit control systems as shown in Figure 24 including, in particular, drive and negated drive (drive_n) signals, a hold-on signal to operate switch 412 (see Figure 12), a force-on signal to operate switch 408 (again see Figure 12) and a storage sense enable signal to operate switch 808. As can be seen from the base current drive signal illustrated in Figure 24, the control system implements a pulse amplitude modulation control scheme as previously described.

Also included in the control system of Figure 23 is a base clamp circuit 2306 (system 2900 of Figure 29) that detects a negative magnetising current and provides enough base current to support this magnetising current. Also included is a turn-on dv/dt control block 2308 (system 3100 of Figure 31) which can control the dv/dt of the collector voltage. Controlling the dv/dt can limit the amount of current that flows through the Cc0i capacitor and, potentially, out of the Col pin (line 213).

Referring to Figures 23 and 24, just before drive turns on the ActiveClamp signal goes high. This signal pulls the "COL" pin to ground resetting one end of the capacitor "Ccol". The drive is now turned on. During the initial part of the drive signal (force-on period as indicated by the force-on signal) a force-on current (1FON) is applied to the power switching transistor. Even though a force-on current is optional, the force-on current quickly brings the collector voltage down to a low value and hence reducing turn-on losses. Figure 24 shows the trailing edge of the force-on signal synchronised with the active clamp signal, but this is not essential. Before the end of the ActiveClamp period the collector voltage falls from a high voltage to a low voltage (close to the saturation voltage). Since both ends of the capacitance are close to ground effectively the capacitor voltage is reset and represents the saturation voltage of the transistor. Also, the ActiveClamp transistor Ml conducts any large current flowing in/out of the "COL" pin during this period, so that the ESD transistors do not come on during turn-on. The hold-on period follows the force-on period. During the hold-on period the amount of base current is adjusted so that at the end of the drive period the transistor is just at the edge of saturation under steady state conditions. This is achieved by aiming to keep the collector voltage equal to an internal reference voltag (typically around I.2V) scaled by Ccol and Cp during hold-on period. This reduces the excess charge in the base and the transistor turns off quickly. Optionally, the "aiming voltage" of the collector may be adjusted by the value of capacitor Cp connected between COL and GND. The amount of base drive during the hold-on period is determined by the leaky peak controller and depends not only on the current value of the collector voltage but also on the previous values. The leaky peak detector is updated only during the time when the storage_sense_en signal is active. This signal can be made active either when the drive is active or after a delay from the rising edge of the drive signal.

An implementation of the Leaky Peak controller 1202 of Figure 23 is shown in Figure 25, in which the element to those previously described are indicated by the reference numerals. Transistor 2502 both buffers the sensed collector voltage and acts as unidirectional source of current for a leaky peak detector circuit which determines the amount of base drive during the hold-on period.

Figure 26 shows an embodiment of the differential transconductance amplifier/with limiter (error amplifier) 2300. The circuit includes a reference current generator 2600 mirrored by transistors 2602a, b, which limits the maximum current from output 2604 to the reference current from generator 2600 (IREF). which limits the base current if the collector voltage is high. Further this reference current may be switched off by transistor 2606 (Ml) in the off period of transistor 208, that is when Drive is off and there is no base current. The differential voltage input to the transconductance amplifier is provided by lines 1504 (the output from the leaky peak detector) and a reference voltage line 2608. Transistor 2610 enables the reference current from generator 2600 to be forced from the output 2604 when transistor 2610 is on.

In operation, during the force-on period a maximum base current (limited to FON = K * REF where K is a constant) is provided. This allows the collector to fall rapidly and thereby reducing the turn-on losses. During the hold-on period this circuits implements the transfer function shown in Figure 1 6. This circuit also acts as a limiter, limiting the maximum base current during the on time to a maximum value of FON = K * REF. Also this circuit provides the current used for clamping the base in response to the "negMag" signal coming from the negMag detector. The transistor Ml aims to ensure that the base current is only provided during the on period of the drive.

Base voltage clamping This applies particularly to the field of resonant discontinuous converters (both forward and flyback) operating with or without proportional base drive and using junction bipolar transistors.

A typical topology is illustrated in Figure 27, which shows a base voltage clamping circuit. in the off-period, energy in the system causes resonance of the BiT collector voltage. When the off-time is larger and the load is light, the collector voltage typically resonates back down to, and below, zero volts. This causes the transistor c-b junction to become forward biased, taking the base voltage below zero. This can have unfortunate consequences: damage (particularly latch-up) of a controller connected to the base and/or failure of the b-e junctions. To inhibit this, a clamp arrangement is included in the controller as shown in the circuit of Figure 27.

During resonance, the turn-off switch is kept closed; this holds the base close to OV so that when the resonance brings the collector voltage below OV, any negative collector current returns via this switch to OV. The controller initiates the next on-period (though collector current may still be negative), the turn-off switch is opened and the force-on current is connected. At the same time, S3 is closed so the prevailing (positive) base voltage is sampled on Chold; provided the negative Imag is less than the force-on current -this is a limitation on maximum Iniag. At the end of the force-on period, both the force-on current is switched off and S3 is opened. If the collector current is still negative, the base voltage will fall but this is detected by the differential amplifier and, if it falls far enough, base current is re-applied to limit the excursion.

Figure 28 shows a timing diagram illustrating a negative magnetizing current at turn-on, where the drive turns on when the magnetising current is negative during the drive disable period when the transistor is off the magnetising current will be flowing through the transistor M2 (Figure 23). When the power switch transistor 208 is turned on, especially at light loads, and if the magnetising current is negative then the base driver will have to provide this current.

Figure 29 shows an embodiment of a negative magnetising current detector 2900 including a base clamping circuit to address this problem; Figure 30 shows an example implementation of the detector of Figure 29 (in which like elements of those of Figure 29 are indicated by like reference numerals). The detector includes a discharge transistor 2902 (M2) to hold the base of transistor 208 close to zero volts when transistor M2 is on. The detector also includes a sample/hold circuit 2904 coupled to the base of transistor 208, again with a discharge transistor 2906 (Ml), the sample/hold circuit providing a sampled voltage signal (Vsample) on line 2908 to a control circuit 2910 via a limiter 2912. The control circuit also receives a signal (Vbase) from the base of transistor 208 and compares this with the signal level on line 2908 and provides an output signal negMag on line 2914. The output signal is related to the two input signals as follows: IF (Vsample -Vbase)> Vref then negMag = K*(Vsample -Vbase -Vref) where K is a constant proportionality. The signal negMag on line 2914 is used to control the base drive current to transistor 208, in general as shown in Figure 27 and in some preferred embodiments of Figure 25. Figure 30, as previously mentioned, shows a more detailed circuit implementation of the detector 2900 of Figure 29.

The following discussion assumes that, as in some preferred embodiments, this system is implemented in an integrated controller fabricated from CMOS technology. During the initial part of the drive cycle, i.e. during the FON period (refer to Figure 28), since maximum base current is provided, the base driver can support this negative magnetising current. During the switch over to the hold-on period, if there is a reverse magnetising current, the proportional part of the base driver will not provide any current. If there were no clamping function this negative magnetising current would cause conduction in the body diode of transistor M2 (Figure 30) as well as ESD (electrostatic discharge) diodes connected to the base pin. Also if we do not detect this and allow the ESD transistors to come on then the feedback capacitor may not be reset roperly to represent the saturation voltage of the power switch transistor.

The circuits shown in Figure 29 and Figure 30 detect such a condition and during the hold-on period turn base drive on to support this negative magnetising current. The voltage at the base is sampled and held by the falling edge of the FON signal.

Subsequently, in the hold-on period this voltage is compared against the voltage on the base and if the difference between the sampled voltage and the base voltage falls below a threshold (offset) level the negMag signal is turned on. The negMag signal is applied to the differential transconductance amplifier (Figure 26) which generates the required base current. The limiter helps to ensure that the base spreading resistance of the BiT does not affect the operation of this circuit. If the base spreading resistance of the BJT is high, during the force-on period a large current, if forced-on to the base, also flows through the base spreading resistance creating a significant voltage drop across it. As the force-on current is removed at the end of the force-on period the voltage at the base pin falls by an amount equal to the voltage across the spreading resistor. This could potentially lead to false triggering of (lie negMag circuit. A limiter, if included, can avoid this problem.

Collector dv/dt limiting at turn-on This applies particularly in the field of switching power converters, including forward and flyback, resonant/not resonant and using a variety of power switching device technologies (BJT, IGBT, MOSFET). The technique addresses two potential problems: Where the primary winding has a significant self capacitance, or has an additional capacitance in parallel, at turn-on of the switch the voltage across these capacitances may change rapidly and by a large amount. Correspondingly, there will be a significant capacitive current which will flow around the circuit: switch, capacitor, power source.

In this circuit current sensing may be employed for over-current protection. The capacitive current may be larger than the threshold setting of this protection needed for other purposes so could trigger the protection falsely. One method to avoid this problem is to blank (ignore) the over-current protection for a short period around the turn-on of the switch. However, this gives rise to a potential hazard that there is then no protection during this period. A further complication arises in designing controllers for switching systems; it is desirable to have a controller that can be used in a wide range of applications. However, there will be a correspondingly wide range of turn-on behaviours (duration, capacitive current amplitude and so forth) and overload protection current thresholds. Setting a particular blanking time will limit (lie range of application.

Control of dV/dt can also be useful at the instant of turnoff of the switch. At turnoff there is typically a fast rise of switch voltage caused by current flow in circuit inductance and transformer leakage inductance. In some configurations this fast rise of voltage can be troublesome particularly where it causes a large rise of voltage. A fast rise of voltage can cause unwanted radio frequency interference and a large rise of voltage can he destructive to the switch or other components of the circuit. If the rate of rise of switch voltage is limited then the energy dissipated from the circuit and leakage inductance does not manifest as a high switch voltage but is instead dissipated in the switch itself.

In embodiments of the converters we describe which use a coupling capacitor to monitor voltage across the switching device, there may be a large pulse of capacitive current through the capacitor at turn-on. If not limited, this current can be damaging to circuits connected to the coupling capacitor, particularly if they are fabricated as integrated circuits using CMOS technology. During the force-on period the ActiveClamp switch is turned on. If the FON current is not limited, the collector falls rapidly. A large dv/dt at the collector translates to a large current through the COL pin of the IC. The ActiClamp switch 406 within the IC should be sized to handle this dv/dt current. The higher the dv/dt bigger is the switch and larger the die area employed. As shown in Figure 23, the Ccol discharge current flows through the ground pin of the 1C which if not limited could result in substantial ground bounce and could affect the operation of the IC.

At turn off of the power switch 208 the Acticlamp switch coupling capacitance to ground. Thus the rate of change of voltage at turn off can be controlled in a similar way to that used at turn on. If a high current is detected in the coupling capacitance then the drive to the switch 208 may be modified to limit the level of current through the capacitor. Normally at this time there is no drive to the switch, but if the rate of change of voltage is detected to be too high (for example, above a threshold) then drive may be reapplied to the switch to limit the rate of turnoff.

A preferred embodiment of a system 3100 to control the dv/dt of the collector during the force-on period is shown in Figure 31. It uses a transconductance amplifier 3102 biased by a voltage Vbjas+VcoI. A high rate of fall of collector voltage will cause current through Ccol, leading to a negative voltage across Ron (of the ActiClamp switch). If greater than Vbias, this will cause a reduction of base drive, hence limiting the rate of fall of the collector and current into the COL connection. By selecting the value of the on resistance of the switch and the bias voltage Vbias one can control the dv/dt of the collector during the force-on period.

Figure 32 shows a circuit described below which can be used to limit the maximum turn on dv/dt by controlling the amount of base current flowing into the BJT. As shown in the figure during FON period the switch M3 is on. During the FON period the COL pin is held quite close to ground by the transistor Ml which is kept in its linear region. A current pulled out through the COL pin during turn on also flows through the transistor Ml. The voltage on the COL pin is given by = A'coi x R0 Equation 1 Where R is the on-resistance of the MOSFET Ml. The output current of this block is given by = K.(V16 - )2 where K = Equation 2 The base current is a scaled value of this out.

VgsM6 during the FON period is given by VgSA46 = Vg,cA42 + T/0, Equation 3 Substituting Equation 3 to Equation 2 we get out = K(VgsAi2 + Vcol - )2 Equation 4 During FON the current flowing through the transistor M2 is the reference current REF.

Therefore * VgM2 = V + ef where K1 = " Equation 5 Substituting Equation 5 and Equation I in Equation 4 we get - x R,,)2 Equation 6 The COL current during turn on depends on the rate at which the collector voltage falls and is given by dv cot Equation 7 Substituting Equation 7 in Equation 6 and since the base current is proportional to out base = K2 -(Cg x x R00)2 where K2 is a cons tan I Equation 8 Hence higher the dv/dt, lesser the base current, which in turn reduces the dv/dt. Also the maximum dv/dt can be controlled by changing the on-resistance of the MOSFET Ml (by changing the dimensions and/or bias).

Another method to control the dv/dt is shown in Figure 33 which illustrates a circuit with collector current feedback. The voltage on the current sense pin Vcs can be use to control the dv/dt. The maximum base current during the turn-on period can be limited to = 1' l/G+h1xRcs Where b is the base current, G is the transconductance of the amplifier, hfe is the current gain of the BJT and R5 is the current sense resistor. Choosing VREF and/or Rc's can limit the dv/dt during turn-on.

Limiting the base current during turn-on limits the collector current and hence limits the turn-on dv/dt at the collector.

Charge storage time measurement We now describe a method of deducing the presence of excess stored charge by monitoring base current during turn-off, to enable a bipolar switching device to be turned off faster.

The techniques described here apply to managing the on-state drive of bipolar transistors (BJT and IGBT) used in cyclic switching applications. As described previously, there is a balance to be struck between high drive level to minimise voltage drop in the switching device during the on-period and the increased time it takes for the device to turn off at the beginning of the desired off-period. Low levels of drive reduce the turn-off time, but increase the on-state voltage. Both parameters are important in maximising power efficiency and control in response to load conditions.

We described above techniques that monitor the collector voltage during on period and adjust the base/gate drive to maintain in a desired range. We now describe a tecirnique which monitors the turn-off behaviour in one cycle to determine the optimum base/gate drive in subsequent cycle(s).

Turn-off behaviour is characterised by a turn-off time, during which the collector-emitter voltage remains low despite base/gate drive having been removed. BJTs during this time show negative base current but may show positive base voltage; this is illustrated in Figures 34a and b.

An increased on-state gate or base drive causes increased storage time. In cyclic switching applications where the load conditions do not change by a large degree between successive cycles, the turn-off behaviour in one cycle can be used to determine the optimum drive in subsequent cycles.

This storage tune can he sensed in either BJT or IGBT applications as the time between removal of the base/gate drive and when the collector voltage rises substantially. The latter can be determined using a comparison between sensed collector voltage and a fixed threshold, or a relative rise of the collector voltage from an on-state value (e.g. by capacitive sensing as described above). Alternatively, in BJTs, the base voltage and/or current can be used. For example, the transistor can be turned off by applying a negative base current (ie pulling current out of the base); when this ceases the transistor is off. Thus measuring the charge storage time may comprise measuring a fall in a negative base current of the transistor. A further option is to detect fall in the collector or emitter current.

To turn off a BJT, the positive base (on-state) base current is removed and, preferably, current is taken from the base toa zero or negative voltage. During the period of charge storage a negative base current is observed, hence the condition of negative current can be used to determine the storage time. The base current may be compared against a threshold, the end of storage time being deduced as the time when the base current increases above the (negative) threshold. Alternatively, when the base turn-off is supplied via a resistor, the base voltage also indicates the end of the storage time; it is held at a more-positive value until the end of the storage time when it falls to the turn-off bias voltage. However, the actual base voltage during the off-period depends on the external resistor, the base spreading resistance and the turn-off bias voltage and other transistor parameters (including temperature). If the turn-off bias is a significant negative voltage then it is possible to detect end of storage time reliably, (but there remains a restriction on the magnitude of the turn-off current and, hence, on reduction of turn- off time, that can be used before detection is unreliable).

Preferably collector voltage (for BJT or IGBT) or base current (in the case of BJTs) are used to determine the storage time. A saturation control system can monitor the time between removal of base (or gate) drive and the time when the collector voltage rises substantially or the collector or emitter current falls substantially. This can then be used to control the amount of base or gate drive applied in subsequent cycles. It is preferable to have a target desaturation time so that the drive is adjusted until the desaturation time is close to the target. If thedesaturation time is longer than the target, the drive is reduced; if the desaturation time is shorter than target then the drive is increased. The target time is preferably chosen carefully: if it is set too short then low values of drive are applied and the on state saturation voltage may be too high. Conversely if it is set too long this could be inappropriate for the converter application.

Once the storage time has been sensed it may then be used to control the level of base/gate drive during subsequent on-period(s). Base/gate drive may be varied by a number of methods described previously, including pulse amplitude modulation, pulse width, frequency or slope modulation and the like. Amplitude refers to base current in the case of BJTs and gate voltage in the case of IGBTs. The control law should be arranged to reduce drive (amplitude or net duration) when storage time increases. The control scheme preferably includes a method/device, such as an integrator or peak detector, to store value(s) from one switching cycle to another. A circuit to achieve this is shown in Figure 35, the operation of which is illustrated in Figure 36.

Summary

The above-described techniques are particularly applicable to cyclic power converters where bipolar transistors (bipolar junction transistors or insulated gate bipolar transistors) are used as power switching devices. In such applications it is important to minimise power loss and provide a high degree of control of the switching periods, it is also important to achieve low on-state voltage drop in the switch while having a fast turn-off, on command from the power control system. In addition to the on-slate power loss consequent of the on-state voltage, power may be lost in the turn-off transition; fast turn off reduces this loss. In flyback converters, energy loss at turn-off directly erodes energy delivered to the load. In forward converters, though turn-off loss does not directly reduce load power, it does result in power wasted in the switching device, in all power converters, delivered power can be controlled via the on and off periods of the switch. For optimum control it is desirable that the switch can be turned off on command from a control signal with minimum delay. Particularly in conditions of overload, small extensions to on-time can degrade power control and, possibly, lead to excessive power dissipation or component failure. The techniques described using coupling capacitor(s) are particularly applicable to resonant discontinuous forward converters because the capacitor(s) can serve both to support the resonant behaviour and as means to manage the on-state switch voltage.

Thus we have described systems in which the base current is controlled by monitoring the voltage at the collector of the BiT during on time of the primary switch, and the methods of measuring the voltage at the collector of the BJT during turn-on.

We have also described the methods and apparatus for controlling the rate of change of collector voltage to control the maximum current that can flow through the COL pin during turn-on. By controlling this, significant area savings can be made within the chip. Also the magnitude of ground bounce during the turn-on can be reduced. We have still further described the methods and apparatus for detecting a negative magnetising current during the proportional drive period. This assists in resetting the feedback capacitor properly thereby facilitating the functioning of the proportional base driver.

This circuit aims to ensure that the ESD diodes are not conducting under such circumstances.

Advantages of dv/dt control include the area reduction that can be made within the chip, and that the magnitude of ground bounce during the turn-on can be reduced. Further advantages of the negative magnetising current detector include that this circuit assists in resetting the feedback capacitor properly thereby facilitating the functioning of the proportional base driver. The circuit also aims to ensure that the ESD diodes are not conducting under such circumstances.

We have described some preferred embodiments of the invention with particularly reference to common-emitter configuration bipolar transistors, but the skilled person will understand that corresponding principles may be applied to common-base or gate operation by using base bias, emitter switching and base current or gate voltage control.

Likewise, although we have described some preferred embodiments of the invention with reference to bipolar junction transistors, as previously mentioned the techniques are also applicable insulated gate bipolar transistors (IGBTs). Some preferred embodiments of the control system arc implemented on a single integrated circuit (with or without the power switching device).

Some preferred embodiments of the invention are particularly useful for power converters including (but not limited to) forward power converters such as resonant discontinuous power converters and flyback converters; these may be powered either from ac mains or from a dc source. However applications for embodiments of the invention are not limited to power converters and include other circuits with cyclic operation, as well as acyclically operating circuits.

Although in the main we have referred to analogue circuitry the skilled person will understand that embodiments of the control systems we describe may equally be implemented in corresponding digital circuitry (or in a combination of analogue and digital circuitry), using digital representations of the control signals mentioned.

No doubt many other effective alternatives will occur to the skilled person. It will be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.

Claims

CLAiMS: 1. A switching power converter, said power converter having an

input to receive an input power supply, an output to provide an output power supply, a magnetic device having at least one winding, said magnetic device being coupled between said input and said output, and a switching device coupled to switch power from said input on and off to said winding of said magnetic device to transfer power from said input to said output, and wherein said switching power converter further comprises a dv/dt limiting circuit to limit a rate of change of a voltage across said winding of said magnetic device when said switching device is turned on or off.
2. A switching power converter as claimed in claim 1 wherein said dv/dt limiting circuit comprises a dv/dt sensing circuit to sense said rate of change of voltage across said winding and a control circuit coupled to said dv/dt sensing circuit to control a drive to said switching device responsive to said sensed rate of change of voltage.
3. A switching power converter as claimed in claim 2 wherein said dv/dt sensing circuit comprises a capacitor coupled to said winding of said magnetic device and a current sense circuit coupled to said capacitor to convert a current through said capacitor to a dv/dt sensing signal.
4. A switching power converter as claimed in claim 3 wherein said current sense circuit comprises a resistance connected in series with said capacitor and wherein said dv/dt sensing signal is dependent on a voltage across said resistance.
5. A switching power converter as claimed in claim 3 or 4 wherein said control circuit has an offset and is configured to adjust said switching device drive to reduce the speed of turn on or turn off of said switching device responsive to said sensed rate of change of voltage exceeding a level set by said offset.
6. A switching power converter as claimed in claim 2, 3, 4 or 5 further comprising a circuit to apply an initial, forcing drive to said switching device when said switching device is turned on, and wherein said control circuit is configured to control a level of said initial, forcing drive.
7. A switching power converter as claimed in claim I wherein said dv/dt limiting circuit comprises a current sensing circuit to sense a current from said input power supply and a control circuit coupled to said current sensing circuit to control a drive to said switching device responsive to said sensed current.
8. A switching power converter as claimed in claim 7 wherein said current sensing circuit includes a current sensing resistor of said power converter, and wherein said current sensing resistor is additionally configured to control an output culTent limit function of said power converter.
9. A switching power converter as claimed in claim 7 or 8 wherein said control circuit is configured to adjust said switching device drive to increase an on-resistance of said switching device responsive to a difference between a signal dependent on said sensed current and a reference.
10. A switching power converter as claimed in any preceding claim wherein said switching device comprises a bipolar junction transistor (BJT) and wherein said dv/dt limiting circuit includes a transconductance circuit to provide a base drive to said BiT.
11. A switching power converter as claimed in any preceding claim wherein said power converter includes a capacitor coupled to a connection between said winding of said magnetic device and said switching device to sense a voltage on said switching device, and wherein said dv/dt limiting circuit is configured to employ said capacitor to sense said rate of change of voltage across said winding.
12. A method of limiting a current flow in a capacitance of a switching power converter, said power converter having an input to receive an input power supply, an output to provide an output power supply, a magnetic device having at least one winding, said magnetic device being coupled between said input and said output, and a switching device coupled to switch power from said input on and off to said winding of said magnetic device to transfer power from said input to said output, the method comprising limiting a rate of change of a voltage across said winding of said magnetic device when said switching device is turned on or off to limit said current flow through said capacitance.
13. A method as claimed in claim 12 wherein said capacitance comprises one or more self-capacitance of said at least one winding, a capacitance coupled in series or parallel with said winding, and a voltage sensing capacitor to sense a voltage on said switching device.
14. A method of controlling current flow through a pin of a power converter controller integrated circuit (IC), the method comprising using the method of claim 12 or 13 to limit a current flow through a capacitance coupled to said IC.