GB2445294B - Method for proactive synchronization within a computer system - Google Patents
Method for proactive synchronization within a computer systemInfo
- Publication number
- GB2445294B GB2445294B GB0802809A GB0802809A GB2445294B GB 2445294 B GB2445294 B GB 2445294B GB 0802809 A GB0802809 A GB 0802809A GB 0802809 A GB0802809 A GB 0802809A GB 2445294 B GB2445294 B GB 2445294B
- Authority
- GB
- United Kingdom
- Prior art keywords
- computer system
- proactive
- synchronization
- proactive synchronization
- computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/526—Mutual exclusion algorithms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30047—Prefetch instructions; cache control instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US71054805P | 2005-08-23 | 2005-08-23 | |
PCT/US2006/033192 WO2007025112A1 (en) | 2005-08-23 | 2006-08-23 | Method for proactive synchronization within a computer system |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0802809D0 GB0802809D0 (en) | 2008-03-26 |
GB2445294A GB2445294A (en) | 2008-07-02 |
GB2445294B true GB2445294B (en) | 2009-01-21 |
Family
ID=37607137
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0802809A Active GB2445294B (en) | 2005-08-23 | 2006-08-23 | Method for proactive synchronization within a computer system |
Country Status (7)
Country | Link |
---|---|
US (6) | US20070050563A1 (ko) |
JP (1) | JP5103396B2 (ko) |
KR (1) | KR101369441B1 (ko) |
CN (1) | CN101297270A (ko) |
DE (1) | DE112006002237B4 (ko) |
GB (1) | GB2445294B (ko) |
WO (1) | WO2007025112A1 (ko) |
Families Citing this family (55)
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WO2007025112A1 (en) * | 2005-08-23 | 2007-03-01 | Advanced Micro Devices, Inc. | Method for proactive synchronization within a computer system |
US7681020B2 (en) * | 2007-04-18 | 2010-03-16 | International Business Machines Corporation | Context switching and synchronization |
US20090125519A1 (en) * | 2007-11-13 | 2009-05-14 | Intel Corporation | Device, system, and method for regulating software lock elision mechanisms |
US8108610B1 (en) * | 2008-10-21 | 2012-01-31 | Nvidia Corporation | Cache-based control of atomic operations in conjunction with an external ALU block |
US8135926B1 (en) * | 2008-10-21 | 2012-03-13 | Nvidia Corporation | Cache-based control of atomic operations in conjunction with an external ALU block |
US8108557B2 (en) * | 2009-01-22 | 2012-01-31 | Hewlett-Packard Development Company, L.P. | System and method for measuring clock skew on a network |
US8316368B2 (en) * | 2009-02-05 | 2012-11-20 | Honeywell International Inc. | Safe partition scheduling on multi-core processors |
US9727508B2 (en) * | 2009-04-27 | 2017-08-08 | Intel Corporation | Address learning and aging for network bridging in a network processor |
US9384063B2 (en) * | 2009-06-18 | 2016-07-05 | Microsoft Technology Licensing, Llc | Eliding synchronization in a concurrent data structure |
WO2011022114A1 (en) | 2009-08-20 | 2011-02-24 | Rambus Inc. | Atomic memory device |
US8307198B2 (en) * | 2009-11-24 | 2012-11-06 | Advanced Micro Devices, Inc. | Distributed multi-core memory initialization |
US20110208921A1 (en) * | 2010-02-19 | 2011-08-25 | Pohlack Martin T | Inverted default semantics for in-speculative-region memory accesses |
US8793471B2 (en) * | 2010-12-07 | 2014-07-29 | Advanced Micro Devices, Inc. | Atomic program verification |
US9122476B2 (en) | 2010-12-07 | 2015-09-01 | Advanced Micro Devices, Inc. | Programmable atomic memory using hardware validation agent |
US8788794B2 (en) * | 2010-12-07 | 2014-07-22 | Advanced Micro Devices, Inc. | Programmable atomic memory using stored atomic procedures |
KR20120101761A (ko) * | 2011-03-07 | 2012-09-17 | 삼성전자주식회사 | 캐시 페이즈 검출기 및 프로세서 코어 |
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CN104025027B (zh) * | 2011-12-30 | 2017-08-15 | 英特尔公司 | 结构访问处理器、方法、系统和指令 |
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US10229043B2 (en) | 2013-07-23 | 2019-03-12 | Intel Business Machines Corporation | Requesting memory spaces and resources using a memory controller |
US9256553B2 (en) * | 2014-03-26 | 2016-02-09 | International Business Machines Corporation | Transactional processing based upon run-time storage values |
US9262343B2 (en) * | 2014-03-26 | 2016-02-16 | International Business Machines Corporation | Transactional processing based upon run-time conditions |
CN104035888B (zh) * | 2014-06-11 | 2017-08-04 | 华为技术有限公司 | 一种缓存数据的方法及存储设备 |
US9710381B2 (en) | 2014-06-18 | 2017-07-18 | International Business Machines Corporation | Method and apparatus for cache memory data processing |
US9740614B2 (en) * | 2014-06-27 | 2017-08-22 | International Business Machines Corporation | Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor |
US9619386B2 (en) | 2015-01-29 | 2017-04-11 | Kabushiki Kaisha Toshiba | Synchronization variable monitoring device, processor, and semiconductor apparatus |
US9513960B1 (en) | 2015-09-22 | 2016-12-06 | International Business Machines Corporation | Inducing transactional aborts in other processing threads |
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US9772874B2 (en) * | 2016-01-29 | 2017-09-26 | International Business Machines Corporation | Prioritization of transactions based on execution by transactional core with super core indicator |
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US10721185B2 (en) | 2016-12-06 | 2020-07-21 | Hewlett Packard Enterprise Development Lp | Age-based arbitration circuit |
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-
2006
- 2006-08-23 WO PCT/US2006/033192 patent/WO2007025112A1/en active Application Filing
- 2006-08-23 DE DE112006002237.7T patent/DE112006002237B4/de active Active
- 2006-08-23 US US11/508,647 patent/US20070050563A1/en not_active Abandoned
- 2006-08-23 CN CNA2006800395372A patent/CN101297270A/zh active Pending
- 2006-08-23 US US11/508,492 patent/US7606985B2/en active Active
- 2006-08-23 JP JP2008528175A patent/JP5103396B2/ja active Active
- 2006-08-23 US US11/508,493 patent/US7627722B2/en active Active
- 2006-08-23 US US11/508,646 patent/US7636819B2/en active Active
- 2006-08-23 US US11/508,494 patent/US20070050561A1/en not_active Abandoned
- 2006-08-23 KR KR1020087007115A patent/KR101369441B1/ko active IP Right Grant
- 2006-08-23 GB GB0802809A patent/GB2445294B/en active Active
- 2006-08-23 US US11/508,491 patent/US7552290B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US5142676A (en) * | 1988-12-28 | 1992-08-25 | Gte Laboratories Incorporated | Separate content addressable memories for storing locked segment addresses and locking processor identifications for controlling access to shared memory |
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Also Published As
Publication number | Publication date |
---|---|
US7627722B2 (en) | 2009-12-01 |
GB0802809D0 (en) | 2008-03-26 |
US20070050560A1 (en) | 2007-03-01 |
US7552290B2 (en) | 2009-06-23 |
JP5103396B2 (ja) | 2012-12-19 |
US20070050562A1 (en) | 2007-03-01 |
US20070067529A1 (en) | 2007-03-22 |
CN101297270A (zh) | 2008-10-29 |
WO2007025112A1 (en) | 2007-03-01 |
US20070050559A1 (en) | 2007-03-01 |
US7606985B2 (en) | 2009-10-20 |
KR101369441B1 (ko) | 2014-03-04 |
US20070050563A1 (en) | 2007-03-01 |
GB2445294A (en) | 2008-07-02 |
DE112006002237T5 (de) | 2008-06-19 |
US20070050561A1 (en) | 2007-03-01 |
DE112006002237B4 (de) | 2023-04-06 |
JP2009506436A (ja) | 2009-02-12 |
US7636819B2 (en) | 2009-12-22 |
KR20080038435A (ko) | 2008-05-06 |
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