GB2444210A - Technique for forming a copper-based metallization layer including a conductive capping layer - Google Patents

Technique for forming a copper-based metallization layer including a conductive capping layer Download PDF

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Publication number
GB2444210A
GB2444210A GB0805068A GB0805068A GB2444210A GB 2444210 A GB2444210 A GB 2444210A GB 0805068 A GB0805068 A GB 0805068A GB 0805068 A GB0805068 A GB 0805068A GB 2444210 A GB2444210 A GB 2444210A
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GB
United Kingdom
Prior art keywords
copper
capping layer
technique
forming
conductive capping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0805068A
Other versions
GB0805068D0 (en
GB2444210B (en
Inventor
Matthias Lehr
Frank Koschinsky
Markus Nopper
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102005046975A external-priority patent/DE102005046975A1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0805068D0 publication Critical patent/GB0805068D0/en
Publication of GB2444210A publication Critical patent/GB2444210A/en
Application granted granted Critical
Publication of GB2444210B publication Critical patent/GB2444210B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

By providing a conductive capping layer (106) for metal-based interconnect lines, an enhanced performance with respect to electromigration may be achieved. Moreover, a corresponding manufacturing technique is provided in which via openings (110) may be reliably etched into the capping layer (106) without exposing the underlying metal (105b), such as copper-based material, thereby also providing enhanced electromigration performance, especially at the transitions between copper lines and vias.
GB0805068A 2005-09-30 2006-08-23 Technique for forming a copper-based metallization layer including a conductive capping layer Expired - Fee Related GB2444210B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102005046975A DE102005046975A1 (en) 2005-09-30 2005-09-30 Process to manufacture a semiconductor component with aperture cut through a dielectric material stack
US11/426,346 US20070077761A1 (en) 2005-09-30 2006-06-26 Technique for forming a copper-based metallization layer including a conductive capping layer
PCT/US2006/032919 WO2007040860A1 (en) 2005-09-30 2006-08-23 Technique for forming a copper-based metallization layer including a conductive capping layer

Publications (3)

Publication Number Publication Date
GB0805068D0 GB0805068D0 (en) 2008-04-23
GB2444210A true GB2444210A (en) 2008-05-28
GB2444210B GB2444210B (en) 2008-09-17

Family

ID=37421158

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0805068A Expired - Fee Related GB2444210B (en) 2005-09-30 2006-08-23 Technique for forming a copper-based metallization layer including a conductive capping layer

Country Status (2)

Country Link
GB (1) GB2444210B (en)
WO (1) WO2007040860A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4878518B2 (en) * 2006-07-28 2012-02-15 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000075982A1 (en) * 1999-06-09 2000-12-14 Alliedsignal Inc. Fabrication method for self aligned cu diffusion barrier in an integrated circuit
WO2002025726A1 (en) * 2000-09-18 2002-03-28 Advanced Micro Devices, Inc. Method to recess interconnects in damascene patterning
US20020084529A1 (en) * 2000-12-28 2002-07-04 Dubin Valery M. Interconnect structures and a method of electroless introduction of interconnect structures
US20040048468A1 (en) * 2002-09-10 2004-03-11 Chartered Semiconductor Manufacturing Ltd. Barrier metal cap structure on copper lines and vias
US20050127511A1 (en) * 2003-12-16 2005-06-16 Chih-Chao Yang Interconnect structures and methods of making thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000075982A1 (en) * 1999-06-09 2000-12-14 Alliedsignal Inc. Fabrication method for self aligned cu diffusion barrier in an integrated circuit
WO2002025726A1 (en) * 2000-09-18 2002-03-28 Advanced Micro Devices, Inc. Method to recess interconnects in damascene patterning
US20020084529A1 (en) * 2000-12-28 2002-07-04 Dubin Valery M. Interconnect structures and a method of electroless introduction of interconnect structures
US20040048468A1 (en) * 2002-09-10 2004-03-11 Chartered Semiconductor Manufacturing Ltd. Barrier metal cap structure on copper lines and vias
US20050127511A1 (en) * 2003-12-16 2005-06-16 Chih-Chao Yang Interconnect structures and methods of making thereof

Also Published As

Publication number Publication date
GB0805068D0 (en) 2008-04-23
GB2444210B (en) 2008-09-17
WO2007040860A1 (en) 2007-04-12

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Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20130823