GB2442278A - Phase locked loop with digital compensation of environmental effects - Google Patents

Phase locked loop with digital compensation of environmental effects Download PDF

Info

Publication number
GB2442278A
GB2442278A GB0619268A GB0619268A GB2442278A GB 2442278 A GB2442278 A GB 2442278A GB 0619268 A GB0619268 A GB 0619268A GB 0619268 A GB0619268 A GB 0619268A GB 2442278 A GB2442278 A GB 2442278A
Authority
GB
United Kingdom
Prior art keywords
locked loop
phase locked
phase
digital
loop according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0619268A
Other versions
GB0619268D0 (en
GB2442278B (en
Inventor
Benjamin James Ogden Kerr
Peter Rowe
Robert Gatward
Lee Thomas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avaya ECS Ltd
Original Assignee
Avaya ECS Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Avaya ECS Ltd filed Critical Avaya ECS Ltd
Priority to GB0619268A priority Critical patent/GB2442278B/en
Publication of GB0619268D0 publication Critical patent/GB0619268D0/en
Publication of GB2442278A publication Critical patent/GB2442278A/en
Application granted granted Critical
Publication of GB2442278B publication Critical patent/GB2442278B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H03L1/026—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature by using a memory for digitally storing correction values
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A phase locked loop 200 includes a phase detector 204 and a voltage controlled oscillator (VCO) 203. A digital control system 206, which includes a microprocessor 214 and a digital to analogue converter 216, replaces the loop filter of prior art. The digital system 206 receives a phase error signal from the phase detector 204 and supplies a control voltage to the VCO 203. The digital control system also receives inputs from external sensors 218 and adapts the operation of the loop to compensate for variations in environmental conditions including supply voltage, temperature, barometric pressure or radiation.

Description

1 2442278
PHASE LOCKED LOOP
BACKGROUND OF THE INVENTION:
Field of the Invention:
The present invention relates to phase locked loops.
Description of the Related Art:
A phase locked loop (PLL) is an electronic circuit with a voltage or current driven oscillator that is constantly adjusted to match, in phase, and thus lock onto, the frequency of an input signal.
A phase locked loop may be used to stabilise a particular corninunicat.jons channel, keeping it set to a particular frequency. In addition a phase locked loop may be used to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, or multiply or divide a frequency.
Phase locked loops are frequently used in wireless communication applications, particularly where signals are carried using frequency modulation (FM), phase modulation (PM), or amplitude modulation (AM) . Phase-locked loops are also widely used in space communications for coherent carrier tracking and threshold extension, bit synchronization, and symbol synchronization.
Phase locked loops are commonly used for digital data transmission, but can also be designed for analogue information. Phase-locked loop devices are typically manufactured as integrated circuits (ICs) A typical phase locked loop includes a voltage controlled oscillator (VCO) . The voltage controlled oscillator is initially tuned to a frequency close to the desired receiving or transmitting frequency. A phase comparator causes the voltage controlled oscillator to seek and lock onto the desired frequency, based on the output of a crystal controlled reference oscillator. This works by means of a feedback scheme. If the VCO frequency departs from the selected crystal reference frequency, the phase comparator produces an error voltage that is applied to the voltage controlled oscillator, bringing the voltage controlled oscillator back to the reference frequency.
Known phase locked loop implementations typically use passive electronic components, or active electronic amplifiers, to implement the feedback loop. Typically such a phase locked loop arrangement has a fixed response that cannot be altered.
It is an aim of the invention to provide an improved phase locked loop in which one or more drawbacks of the
prior art are overcome.
SUMMARY OF THE INVENTION
In accordance with the invention there is provided a phase locked loop comprising: a phase detector for generating a phase error; a digital stage for receiving the phase error and for generating a control voltage; and a voltage Controlled oscillator for receiving the control voltage.
The digital stage is preferably a digitally adaptive stage. The digital stage preferably includes a digital-to-analogue converter.
The digitally adaptive stage preferably comprises: a programmable element for receiving the phase error; and a digital-to-analogue converter connected to the programmable element and for generating the control voltage. The adaptive stage may further comprise a program memory connected to the programmable element.
The programmable element may be adapted to receive information representative of operating conditions. The programmable element may be adapted to control the digital_to_analogue converter in dependence on the information representative of operating conditions. The information representative of operating conditions represents environmental conditions. The information representative of operating conditions represents implementation conditions.
The operating parameters may be retrieved from the memory in dependence on the operating conditions.
The phase locked loop may further comprise: a first divider for receiving an input clock and for generating a first input the phase detector; a second divider for receiving a feedback clock from the voltage controlled oscillator and for generating a second input to the phase detector, wherein the phase detector generates the phase error in dependent upon its first and second inputs.
BRIEF DESCRIPTION OF THE DRAWINGS:
The invention is now described by way of example with reference to the accompanying Figures, in which: Figure 1 illustrates a typical prior art arrangement of a phase locked loop; and Figure 2 illustrates an exemplary implementation of a phase locked loop in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS:
Figure 1 illustrates a typical prior art arrangement of a traditional phase locked loop implementation. The phase locked loop 100 includes a divider 102 having a divide-by-N ratio, a phase detector 104, a loop filter 106, a voltage controller oscillator 108, and a divider 110 having a divide-by-M ratio.
The divider 102 receives at an input thereof an input clock signal. A divided down clock signal (divided by N) is then generated by the divider 102 and provided as an input to the phase detector 104. The phase detector generates a phase error. The phase error is provided as an input to the loop filter 106. The loop filter generates a control voltage. The control voltage is provided as an input to the voltage controlled oscillator 108. The voltage controlled oscillator 108 generates an output clock at a first output thereof. At a second output thereof the voltage controlled oscillator 108 generates a feedback clock signal. The feedback clock signal is provided as an input to the divider 110. A divide down feedback clock signal (divided by M) is provided as a further input to the phase detector 104.
A phase locked loop implementation as illustrated in Figure 1 is well-known in the art. The voltage controlled oscillator 108 generates an output clock in dependence on the control voltage at its input. The control voltage itself is representative of the phase error detected in the phase detector 104. The phase error represents the phase difference (i.e. error) between the signal generated by the voltage controlled oscillator 108 and the input clock. In this way the phase locked loop provides a stable clock signal at a desired frequency.
In traditional phase locked loop implementations, as illustrated in Figure 1, the behaviour of the loop must be measured and evaluated within an expected operating range. If the operating range is ever exceeded, the phase locked loop may operate in an undefined or unexpected way. Further, the passive electronic components in a typical phase locked loop implementation may not be specified or designed to operate outside the limits the circuit was originally designed for.
The invention improves upon such traditional phase locked loop implementations by incorporating a programmable element. The invention provides, in embodiments, a digitally adaptive phase locked loop which can behave in different ways for different circumstances. The behaviour of such a phase locked loop can also be altered whilst operational to adapt to changing circumstances. A traditional phase locked loop, as illustrated in Figure 1, cannot be changed dynamically.
Figure 2 illustrates an embodiment of a phase locked loop implementation in accordance with the principles of the present invention. The digitally adaptive phase locked loop 200 includes a divider 202 having a divide-by-N ratio, a phase detector 204, an adaptive stage 206, a voltage controlled oscillator 208, and a divider 210 having a divide-by-M ratio. The adaptive stage 206, in the embodiment, includes a program memory 212, a programmable element 214, and a digital-to_analogue converter 216. In the embodiment of Figure 2 there is further illustrated a block 218 representing external sensors.
The divider 202 receives at an input thereof an input clock signal. A divided down clock signal (divided by N) is then generated by the divider 202 and provided as an input to the phase detector 204. The phase detector generates a phase error. The phase error is provided as an input to the adaptive stage 206.
The phase error is received as an input of the programmable element 214 of the adaptive stage 206. The programmable eIement 214 may further receive sensor inputs from the external sensors block 218. The programmable element 214 is provided with a bi-directional communication interface with the program memory 212. The programmable element 214 further provides inputs to the digital-to_analogue converter 216. The digital_to_analogue converter 216 provides the output of the adaptive stage 206, being a control voltage of the phase locked loop 200.
The control voltage generated by the adaptive stage 206 is provided as an input to the voltage controlled oscillator 208. The voltage controlled oscillator 208 generates an output clock at a first output thereof. At a second output thereof the voltage controlled oscillator 208 generates a feedback clock signal. The feedback clock signal is provided as an input to the divider 210. A divided down feedback clock signal (divided by M) is provided as a further input to the phase detector 204.
The program memory 212 may be implemented as any appropriate memory device, and for example may be a RAM or ROM. The programmable element 214 may be any suitable programmable controller, and may for example be a microprocessor or digital signal processor.
The external sensors provided in the block 218 may be a variety of different sensors, provided in accordance with the implementation of the phase locked loop. Different sensors may be plugged into' the adaptive stage 206 in accordance with the requirements of a given implementation or system. Non-limiting examples of external sensors are temperature sensors, altitude sensors, barometric pressure sensors, voltage (supply voltage) sensors, base frequency sensors, and radiation sensors. An input may also be provided, not necessarily from a sensor, being indicative of the device package type of which the phase locked loop forms a part. Any external parameter which may effect the operation of the voltage controlled oscillator, or indeed any other element of the phase locked loop, may be sensed and provided as inputs to the adaptive stage 206. In this way, the adaptive stage 206 may compensate for non-linearity's as is discussed in further detail herein below.
As can be seen from Figure 2 in comparison with Figure 1, the invention proposes the replacement of the loop filter 106 of the prior art arrangement with an adaptive stage 206. The programmable element 214 of the adaptive stage 206 drives a digital input to the digital-to-analogue converter 216 to emulate the behaviour of the loop filter 106 algorithmically.
In operation, the programmable element 214 monitors the output from the phase detector 204 and also monitors the signals generated by the external sensors. A software algorithm running under the control of the programmable element 214 combines these inputs to produce a digital value to be presented to the digital-to-analogue converter 214. The digital-to-analogue converter 216 then converts the digital signal into an analogue representation. The analogue signal generated by the analogue-to-digital converter 216 then drives the voltage controlled oscillator 208 to modulate the output frequency of the oscillator, therefore emulating the behaviour of a traditional prior art phase locked loop.
The digitally adaptive phase locked loop implementation of Figure 2 thus uses a software algorithm to implement a feedback control function. This algorithm can be dynamically altered to compensate for changing circumstances. Changing circumstances may be caused by changes in voltage or temperature, for example, or when a different response is required.
when a different response is required, then the programmable element 212 may access the program memory 212 in order to retrieve appropriate parameters.
Similarly, when an external sensor indicates a change in conditions, then the programmable element 214 may access the external sensor in order to access appropriate parameters for operation at that temperature in order to achieve satisfactory device performance.
There are effectively two causes for needing to adapt the operation of the PLL: (1) the capture frequency changes (e.g. due to ramp-up normal operation change, or due to a new operating use); or (ii) an external parameter such as temperature changes. In case (I) the external sensors are not needed, in case (ii) they are.
For both cases, the purpose of the program memory is to store device characteristics that need to be applied by the programmable element in order to achieve the required operation at the new capture frequency or the new temperature. In other words, when any condition changes the memory provides the data that can be used to ensure operation is unaffected.
The provision of the programmable element 214 within the adaptive stage 206 allows for the adaptation of the capture range of the phase locked loop. The capture range may, for example, be made large at device start-up. Once the device becomes closer to the desired lock-on frequency, smaller adjustments can be made and the capture range may be narrowed.
The programmable element 214 may retrieve from the program memory 212 appropriate data for a given capture range.
The software algorithm may be programmed to adapt to the non-linear characteristics of the voltage controlled oscillator 208 and the digital-to-analogue converter 216.
This allows for low-cost voltage controlled oscillators and digital-to-analogue converters to be used.
If the voltage controlled oscillator is based on a quartz crystal (in the case of a voltage controlled crystal oscillator), this crystal may exhibit long-term ageing characteristics. The digitally adaptive phase locked ioop in accordance with the invention may monitor and track the crystal aging, and adjust the control loop response to compensate. In some circumstances, it may be desirable to detect if the voltage controlled oscillator is operating outside the desired limits. In these situations, the digitally adaptive phase locked loop could be programmed to operate in a fail-safe' mode to prevent dangerous or undesirable operation.
The digitally adaptive phase locked loop in accordance with embodiments of the invention thus replaces the loop filter of a conventional implementation with a digital-to-analogue converter, uses a programmable element to implement the functionality of feedback control, and uses external sensors to provide additional control inputs into the feedback control ioop. This makes the phase locked loop more adaptable and flexible, allowing the feedback response to be altered during use, or to provide a different response depending on circumstances.
Embodiments of the invention may be utilised in a wide range of applications. Example applications include telecommunication and data communication applications where accurate phase-locked loops are required for clock and data recovery. Radio receiving devices also require very accurate phase locked loops to remain tuned' to the carrier frequency. An example could be the radio communications device on a satellite. The satellite may experience large differences in operating temperature depending on its orientation with respect to the sun. A traditional phase locked loop implementation may not be able to compensate for this large temperature differential, whereas a digitally adaptive phase locked loop could sense the external temperature and alter the response of the PLL to compensate.
It will be appreciated by one skilled in the art that the invention, and embodiments thereof, has a broad range of uses and may be used in diverse applications. --11

Claims (11)

  1. Claims 1. A phase locked loop comprising: a phase detector for
    generating a phase error; a digital stage for receiving the phase error and for generating a control voltage; and a voltage controlled oscillator for receiving the control voltage.
  2. 2. A phase locked loop according to claim 1 wherein the digital stage is a digitally adaptive stage.
  3. 3. A phase locked loop according to claim 1 or claim 2 wherein the digital stage includes a digital-to-analogue converter.
  4. 4. A phase locked loop according to claim 1 wherein the digitally adaptive stage comprises: a programmable element for receiving the phase error; and a digital-to-analogue converter connected to the programmable element and for generating the control voltage.
  5. 5. A phase locked loop according to claim 4 wherein the adaptive stage further comprises a program memory connected to the programmable element.
  6. 6. A phase locked loop according to claim 4 or claim 5 wherein the programmable element is adapted to receive information representative of operating conditions.
  7. 7. A phase locked loop according to claim 6 wherein the programmable element is adapted to control the digital-to-analogue converter in dependence on the information representative of operating conditions.
  8. 8. A phase locked loop according to claim 6 wherein the information representative of operating conditions represents environmental conditions.
  9. 9. A phase locked loop according to claim 6 wherein the information representative of operating conditions represents implementation conditions.
  10. 10. A phase locked loop according to claim 6 when dependent upon claim 5, wherein the operating parameters are retrieved from the memory in dependence on the operating conditions.
  11. 11. A phase locked loop according to claim 1 further comprising: a first divider for receiving an input clock and for generating a first input the phase detector; a second divider for receiving a feedback clock from the voltage controlled oscillator and for generating a second input to the phase detector, wherein the phase detector generates the phase error in dependent upon its first and second inputs.
GB0619268A 2006-09-29 2006-09-29 Phase locked loop Expired - Fee Related GB2442278B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0619268A GB2442278B (en) 2006-09-29 2006-09-29 Phase locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0619268A GB2442278B (en) 2006-09-29 2006-09-29 Phase locked loop

Publications (3)

Publication Number Publication Date
GB0619268D0 GB0619268D0 (en) 2006-11-08
GB2442278A true GB2442278A (en) 2008-04-02
GB2442278B GB2442278B (en) 2011-07-20

Family

ID=37434947

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0619268A Expired - Fee Related GB2442278B (en) 2006-09-29 2006-09-29 Phase locked loop

Country Status (1)

Country Link
GB (1) GB2442278B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102075191A (en) * 2009-11-24 2011-05-25 Nxp股份有限公司 High resolution overlapping bit segmented DAC
EP3633856A4 (en) * 2017-07-03 2021-03-17 ZTE Corporation Method, apparatus and system for compensating for frequency device, and computer-readable storage medium

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4972160A (en) * 1989-12-07 1990-11-20 Northern Telecom Limited Phase-lock loop circuit with improved output signal jitter performance
US20040232997A1 (en) * 2003-05-02 2004-11-25 Silicon Laboratories Inc. Method and apparatus for temperature compensation
US20060017512A1 (en) * 2004-07-26 2006-01-26 Realtek Semiconductor Corp. Circuit for detecting phase errors and generating control signals and PLL using the same
EP1814230A1 (en) * 2006-01-30 2007-08-01 Infineon Technologies AG Phase locked loop circuitry with digital loop filter

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4827225A (en) * 1988-06-13 1989-05-02 Unisys Corporation Fast locking phase-locked loop utilizing frequency estimation
US4920320A (en) * 1988-12-19 1990-04-24 Motorola, Inc. Phase locked loop with optimally controlled bandwidth
JP2979043B2 (en) * 1989-06-30 1999-11-15 東洋通信機株式会社 Multi-loop gain weakly coupled oscillator
JP2581398B2 (en) * 1993-07-12 1997-02-12 日本電気株式会社 PLL frequency synthesizer
US5392005A (en) * 1993-09-30 1995-02-21 At&T Corp. Field calibration of a digitally compensated crystal oscillator over a temperature range
US5659884A (en) * 1995-02-10 1997-08-19 Matsushita Communication Industrial Corp. Of America System with automatic compensation for aging and temperature of a crystal oscillator
US5786733A (en) * 1995-12-04 1998-07-28 Nec Corporation Phase-locked oscillating circuit with a frequency fluctuation detecting circuit
JPH09246965A (en) * 1996-03-14 1997-09-19 Nec Corp Pll frequency synthesizer
US6023198A (en) * 1998-06-08 2000-02-08 Motorola, Inc. Self-tuning and temperature compensated voltage controlled oscillator
US6933788B2 (en) * 2001-05-16 2005-08-23 Kyocera Wireless Corp. Reference oscillator
US6597249B2 (en) * 2001-09-04 2003-07-22 Prominenet Communications, Inc. Fast coarse tuning control for PLL frequency synthesizer
US7116182B2 (en) * 2003-06-03 2006-10-03 Halliburton Energy Services, Inc. Method and system for downhole clock having compensation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4972160A (en) * 1989-12-07 1990-11-20 Northern Telecom Limited Phase-lock loop circuit with improved output signal jitter performance
US20040232997A1 (en) * 2003-05-02 2004-11-25 Silicon Laboratories Inc. Method and apparatus for temperature compensation
US20060017512A1 (en) * 2004-07-26 2006-01-26 Realtek Semiconductor Corp. Circuit for detecting phase errors and generating control signals and PLL using the same
EP1814230A1 (en) * 2006-01-30 2007-08-01 Infineon Technologies AG Phase locked loop circuitry with digital loop filter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102075191A (en) * 2009-11-24 2011-05-25 Nxp股份有限公司 High resolution overlapping bit segmented DAC
EP2328274A1 (en) * 2009-11-24 2011-06-01 Nxp B.V. High resolution overlapping bit segmented dac
US7986255B2 (en) 2009-11-24 2011-07-26 Nxp B.V. High resolution overlapping bit segmented DAC
EP3633856A4 (en) * 2017-07-03 2021-03-17 ZTE Corporation Method, apparatus and system for compensating for frequency device, and computer-readable storage medium

Also Published As

Publication number Publication date
GB0619268D0 (en) 2006-11-08
GB2442278B (en) 2011-07-20

Similar Documents

Publication Publication Date Title
US6236267B1 (en) Linearization for power amplifiers using feed-forward and feedback control
US8421507B2 (en) Phase-locked loop with calibration function and associated calibration method
US5604468A (en) Frequency synthesizer with temperature compensation and frequency multiplication and method of providing the same
US7579919B1 (en) Method and apparatus for compensating temperature changes in an oscillator-based frequency synthesizer
US20130106476A1 (en) Temperature compensation in a pll
US20100277244A1 (en) All-digital phase-locked loop, loop bandwidth calibration method, and loop gain calibration method for the same
JP4929429B2 (en) Frequency offset correction technique for crystals used in communication systems
KR102418966B1 (en) Digital phase locked loop and driving method thereof
CN109150109B (en) Radio signal processing device, semiconductor device, and oscillation frequency variation correction method
KR20100031892A (en) Two-point phase modulator and conversion gain calibration method thereof
EP1884019B1 (en) Frequency synthesizer with loop filter calibration for bandwidth control
US9008252B2 (en) Circuit, method and mobile communication device
US10944359B2 (en) Temperature compensation of a quartz crystal oscillator
US10594323B2 (en) Locked loop circuit and method with digitally-controlled oscillator (DCO) gain normalization
US6404294B1 (en) Voltage control oscillator (VCO) with automatic gain control
US20240267005A1 (en) System and method of mitigating interference caused by coupling from power amplifier to voltage-controlled oscillator
US7180376B2 (en) Synthesizer and calibrating method for the same
US10944358B2 (en) Control of a quartz crystal oscillator frequency tuning array
US20090168943A1 (en) Clock generation devices and methods
GB2442278A (en) Phase locked loop with digital compensation of environmental effects
CN106941351B (en) Dual calibration loop for random spread spectrum modulator
KR100918860B1 (en) Frequency synthesizer having loop filter compensation circuit
US8085107B2 (en) Transmission module
US6546060B1 (en) Direct modulating FSK transmitter for MCA
JP2005277776A (en) Frequency-compensated voltage controlled oscillator

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20120929