GB2440006A

GB2440006A - ADC for use with digital receiver

Info

Publication number: GB2440006A
Application number: GB0613757A
Authority: GB
Inventors: Richard Simpson; Nirmal C Warke
Original assignee: Texas Instruments Ltd; Texas Instruments Inc
Current assignee: Texas Instruments Ltd; Texas Instruments Inc
Priority date: 2006-07-12
Filing date: 2006-07-12
Publication date: 2008-01-16
Anticipated expiration: 2026-07-12
Also published as: GB0613757D0; GB2440006B

Abstract

Systems and methods are provided for analog-to-digital conversion in a digital receiver system. The digital receiver system comprises an ADC, slicer and time recovery portion. The system receives an input signal having an associated signal voltage range spanning a minimum and maximum signal voltage and the ADC converts a sub-range 56 of the input voltage signal range, the voltage sub-range 56 being associated with a slicer. The ADC may comprise sets of comparators C1-C12 having respective voltage thresholds in non-contiguous ranges 52-60. The system may also convert subranges 52,54 to adjust the timing of the sample times. The voltage subranges 58,60 do not contain information of interest to the digital receiver.

Description

ANALOG-TO-DIGITAL CONVERSION IN RECEIVER SYSTEM

The invention relates generally to communications and, more particularly, to systems and methods for analog-to-digital conversion in a receiver system.

BACKGROUND

In high speed communication applications, it is often necessary to sample an analog signal at a very high rate. For example, in a serializer/deserializer arrangement along a computer backplane, it can be desirable to sample the analog signal transmitted across the computer backplane at a rate ten gigasamples per second. To this end, an analog-to-digital converter (ADC) is utilized in combination with a decision feedback equalizer to provide accurate digital samples at the desired rate. As communications technology advances, the demands on the ADC and the decision feedback equalizer increase, placing a premium on efficient sampling of a transmitted analog signal.

SUMMARY

In accordance with an aspect of the invention, a digital receiver system for a high-speed serial communications system is provided that receives and interprets an input signal having an associated signal voltage range spanning a minimum signal voltage and a maximum signal voltage. An analog-to-digital converter (ADC) converts at least a portion of the input signal into a digital value representation of the signal at. each of a plurality of sample times. A slicer determines an associated symbol value for the input signal at each sample time based on at least a portion of the digital value representation representing a subrange of the signal voltage range that is less than the signal voltage range. A timing recovery portion adjusts the timing of the plurality of sample times according to the digital value provided by the ADC.

In accordance with an aspect of the invention, a digital receiver system is provided. An analog-to-digital converter converts an analog input signal into a digital value at each of a plurality of sample times. A first set of at least one comparator has respective associated thresholds within a first voltage range. A second set of at least one comparator has respective associated thresholds within a second voltage range.

The second voltage range is not contiguous with the first voltage range. A third set of at least one comparator has respective associated thresholds within a third voltage range. The third voltage range is not contiguous with the first voltage range or the second voltage range. A slicer receives the output of the second set of at least one comparator and determines an associated symbol value for the analog signal at each sample time. A timing recovery portion receives the output of at least the first set of at least one comparator and the third set of at least one comparator and adjusts the plurality of sample times associated with the analog-to-digital converter.

In accordance with an aspect of the invention, a method is provided for configuring an analog-to-digital converter for use within a digital receiver incorporating a decision feedback equalizer. An associated overall voltage range is determined for an input signal. At least one voltage subrange is determined that does not contain information of interest to the digital filter. Comparator threshold values are selected for the analog-to-digital conzerter such that the comparator thresholds fall within the overall voltage range for the signal, but not within the at least one voltage subrange, such that the comparator threshold values are unevenly distributed across the overall voltage range.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a receiver system in accordance with an aspect of the invention.

FIG. 2 illustrates an example chart of a voltage range associated with an analog-to-digital converter.

FIG. 3 illustrates a first example analog-to-digital converter in accordance with an aspect of the invention.

FIG. 4 illustrates a second example analog-to-digital converter in accordance with an aspect of the invention.

FIG. 5 illustrates a computer serial bus system incorporating an analog-to-digital converter for use with a system backplane in accordance with an aspect of the invention.

FIG. 6 illustrates a methodology for configuring an analog-to-digital converter in accordance with an aspect of the invention.

DETAILED DESCRIPTION

FIG. 1 illustrates a receiver system 10 in accordance with an aspect of the invention. The receiver system 10 is operative to receive an analog signal, convert the analog signal into a digital value at a plurality of sample times with known periodicity, and determine a symbol value from the digital value, representing at least one bit of transmitted information. The receiver system 10 comprises an analog-to-digital converter (ADC) 12 that converts the signal into a digital value at each of a plurality of sample times controlled by a system clock 14. The ADC 12 has an associated voltage range that can be constant or can vary with a maximum amplitude of the input signal.

The ADC 12 comprises a plurality of comparators each comparator from the plurality of comparators having an associated comparator threshold. It will be appreciated that the voltage associated with each comparator threshold can vary if the overall voltage range of the ADO changes with the maximum signal amplitude such that each threshold is maintained at a specified proportion of the overall voltage range.

A first set of comparators 16 can compare the input signal amplitude to voltages within a first voltage subrange of the overall voltage range of the ADO 12. For example, the first voltage subrange can represent an uppermost portion of the overall voltage range of the ADO 12. Accordingly, any comparator thresholds associated with the first set 16 will fall within the uppermost voltage subrange. It will be appreciated that in some applications, information from the uppermost voltage subrange can be unnecessary, and that the first comparator set will contain no comparators, such that signal values within this range are intentional clipped to a maximum output value for the ADO 12. A second set of at least one comparator 17 compares the input signal amplitude to voltages within a second voltage subrange of the overall voltage range of the ADO 12. For example, the second voltage subrange can represent a center subrange of the overall voltage range of the ADO 12. In accordance with an aspect of the invention, the first voltage subrange and the second voltage subrange are not contiguous, such that a voltage gap exists between the first and second voltage subrange. It will be appreciated that this voltage gap between the first and second subranges is greater than the voltage gap between neighboring amplitude thresholds within a given voltage subrange.

A third set of comparators 18 can compare the input signal amplitude to voltages within a third voltage subrange of the overall voltage range of the ADO 12. For example, the third voltage subrange can represent a lowermost subrange of the overall voltage range of the ADO 12. In accordance with an aspect of the invention, the third voltage subrange is not contiguous to the first voltage subrange or the second voltage subrange, such that a voltage gap exists between the third voltage subrange and each of the first and second voltage subrange. As discussed above, the voltage gaps separating the third subrange from the first and second voltage subranges is greater than the voltage gap between neighboring amplitude thresholds within a given voltage subrange. It will be appreciated that in some applications, information from the lowermost voltage subrange can be unnecessary, and that the third comparator set will contain no comparators such that signal values within this range are intentional clipped to a minimum output value for the ADO 12.

The digital output from the second set of the comparators 17 is provided to a slicer 22 that determines a symbol value associated with the digital output. The slicer 22 can apply an intersymbol interference (ISI) correction to the digital output that is provided by a decision feedback equalizer 24 from previous symbols determined at the slicer 22. It will be appreciated, however, that the extent of this correction will be limited. In accordance with an aspect of the invention, the available ISI correction from the decision feedback equalizer can be used to define the second voltage subrange, such that the associated thresholds of the second comparator set all fall within a value equal to the maximum ISI correction from a slicer level associated with the slicer 22. Accordingly, the output of the second set of comparators 17 is provided to the slicer 22, while the output o the first and third comparator sets 16 and 18, which compare the input signal to voltages outside of the voltage range associated with the slicer, are not provided to the slicer.

Alternatively, the second voltage subrange can be defined according to expected values for the main cursor in a signal. In accordance with an aspect of the invention, the analog signal can be comprised of a plurality of pulses, with each symbol represented by the pulses having a characteristic amplitude. For example, a given symbol (e.g., 0 or 1) can be represented by a pulse within the signal having a peak amplitude equal to a first voltage or a pulse having trough amplitude equal to a second voltage, generally equal and opposite to the first voltage. The second voltage subrange can be selected to span these voltages.

Depending on the implementation, the second voltage subrange can be defined to encompass a peak voltage equal to the first voltage adjusted by a maximum positive ISI correction, and a trough voltage equal to the second voltage adjusted by a maximum negative ISI correction.

The receiver 10 further includes a timing recovery component 26 that ensures that the sample times provided to the ADC 12 by the system clock 14 remain synchronized with associated sample points within the analog signal. The timing recovery component 26 utilizes the digital values from the second set of comparators 17, and the first and third sets of comparators 16 andl8, if any, from the ADC 12 and data from the decision feedback equalizer 26 to determine when the timing of the system clock 14 and the analog signal deviate. It will be appreciated that the timing recovery component 26 and the slicer 22 do not require data from portions of the overall voltage range of the ADO 12 falling outside of the first, second, and third subranges to accurately decode the analog signal. Accordingly, by concentrating the resolution of the ADC into those voltage ranges that provide useful information, the overall resolution of the ADO can be increased without increasing its associated power consumption and chip space. Alternatively, the power consumption and required chip space for the ADO can be reduced without negatively impacting the resolution of the ADO.

FIG. 2 illustrates an example chart of a voltage range 50 associated with an analog-to-digital converter ranging from a maximum voltage, V, to a minimum voltage, Viri. The voltage range 50 can be divided roughly into five voltage subranges. A first voltage subrange 52 represents an uppermost portion of the ADC voltage range. A second voltage subrange 54 represents a lowermost portion of the ADC voltage range. The first and second subranges 52 and 54 can contain information (e.g., voltage levels) that is of interest for timing recovery in an associated equalizer system. This is reflected in the diagram by the presence of a plurality of comparator threshold levels, CL, C2, C11, and C12, distributed within the two subranges 52 and 54. It will be appreciated, however, that in some applications, it will be unnecessary to utilize information from these ranges in timing recovery, and no comparator thresholds need be located within the voltage subranges.

A third voltage subrange 56 represents a central portion of the ADC voltage range. A fourth voltage subrange 58 separates the third voltage subrange 56 from the first voltage subrange 52.

A fifth voltage subrange 60 separates the third voltage subrange 56 from the second voltage subrange 54. The third voltage subrange 56 contains information that is useful to extract transmitted information from the ADC output at an associated slicer. Accordingly, the boundaries, Viniax and VSlmlfl, of the third voltage subrange encompass all data that will be passed to the slicer. These boundaries can be a function of the expected main cursor values of the signal, such that VjTpa. is a characteristic peak amplitude of a pulse representing a first symbol, and TsI11rI is a characteristic trough amplitude of a pulse representing a second symbol.

Alternatively, an equalizer associated with the slicer can be operative to apply a limited amount of correction to the ADC output. to correct for intersymbol interference within the analog signal. Specifically, the equalizer can apply up to a maximum amount of positive correction, ISIp, or up to a maximum amount of negative correction, 151nq Accordingly, the third voltage subrange 56 can comprise a range from ISI1; to ISI, as any value falling outside of this range cannot be moved from one side of a slicer threshold (e.g., zero) to the other side by the intersymbol interference correction. For example, if a value is within the fourth subrange 58, even the maximum negative intersymbol interference correction cannot reduce the signal value below zero. Accordingly, data from the fourth and fifth subranges 58 and 60 is not useful at the slicer. It has also been determined, for one or more applications of interest, that values within these ranges are also not useful for timing recovery. Accordingly, the remaining comparator threshold values, C3-C1(, are distributed within the third subrange 56, with no comparator threshold values falling within the fourth voltage subrange 58 or the fifth voltage subrange 60. This ensures that the available resolution for the ADC is applied to the regions for which it will be most helpful. In some applications, such as serializer and deserializer applications, these unused subranges 58 and 60 can represent a significant portion of the total voltage range of the A]JC (e.g., approximately one-half), allowing for a significant increase in the effective resolution of the ADO or a decrease in the require power and chip space for the ADO.

FIG. 3 illustrates a first example analog-to-digital converter (ADO) 100 in accordance with an aspect of the invention. The ADO 100 comprises a plurality of comparators 102- 114 having associated comparator thresholds evenly distributed across a range from a minimum value, -6K, to a maximum value, 6K, expressed in terms of a constant K that is a function of a maximum amplitude of the input signal. In accordance with an aspect of the invention, the comparators include a first set of comparators 120, having comparator threshold values within a first voltage subrange, -6K to -5K, and a second set of comparators 122, having threshold values within a second voltage subrancge, 5K to 6K. In accordance with an aspect of the invention, the threshold values within the first and second voltage subranges are of interest in correcting the timing of the ADC and one or more other associated components. These values are thus provided to a timing recovery function 124 associated with the ADC.

In accordance with an aspect. of the invention, a third set of comparators 126 have threshold values within a third voltage subrange, 2K to 2K, that contains information useful for a slicer 128 that identifies symbols within the digitized input signal. For example, the output of the ADC 100 can be corrected by an associated equalizer to account for intersymbol interference (ISI) in the analog signal. Any information not within a maximum ISI correction value associated with the equalizer of a slicing level associated with the slicer 128 will not be useful to the slicer, as outside of that range even a maximum amount of 151 correction will not move the signal value to the other side of the slicer level. Thus, the third voltage subrange can be limited to a voltage range of a slicer level (e.g., 0) plus and minus a maximum amount of 151 correction (e.g., 2K), as this is the only data of interest to the slicer 128.

Where the comparator thresholds of the ADC 100 are evenly distributed across the voltage range, one or more comparators 104, 105, 111, and 112 will have thresholds that are not within the first, second, or third voltage subranges. These comparators do not provide sufficient information to the slicer 128 or the timing recovery function 124 to justify their power consumption or chip space. Accordingly, they can be depowered or removed from the design. In this manner, an ADC of comparable resolution can be implemented within a receiver at a decreased cost in chip space and power.

FIG. 4 illustrates a second example analog-to-digital converter (ADC) 150 in accordance with an aspect of the invention. The ADC 150 comprises a plurality of comparators 152- 164 having associated comparator thresholds with a range bounded by a minimum value, -6K, and a maximum value, 6K, expressed in terms of a constant K that is a function of a maximum amplitude of the input signal. In accordance with an aspect of the invention, the comparators include a first set of comparators 120, having comparator threshold values within a first voltage subrange, -6K to -5K, and a second set of comparators 122, having threshold values within a second voltage subrange, 5K to 6K. In accordance with an aspect of the invention, the threshold values within the first and second subranges are of interest in correcting the timing of the ADC and one or more other associated components. These values are thus provided to a timing recovery function 174 associated with the ADC.

In accordance with an aspect of the invention, a third set of comparators 176 have threshold values within a third voltage subrange, 2K to 2K, that contains information useful for a slicer 178 that identifies symbols within the digitized input signal. For example, the output of the A]JC 150 can be corrected by an associated equalizer to account for intersymbol interference (151) in the analog signal. Any information not within a maximum ISI correction value associated with the equalizer of a slicing level associated with the slicer 178 will not be useful to the slicer, as outside of that range even a maximum amount of 1ST correction will not move the signal value to the other side of the slicer level. Thus, the third voltage subrange can be limited to a voltage range of a slicer level (e.g. , 0) plus and minus a maximum amount of 151 correction (e.g., 2K), as this is the only data of interest to the slicer 178.

It will be appreciated that a fourth subrange, ranging from approximately -5K to -2K and a fifth subrange, ranging from 2K to 5K, are not represented in the comparator thresholds. Instead, the comparator thresholds are distributed unevenly, such that the resolution within the third subrange is increased in comparison to an even distribution of comparator thresholds. Thus, the effective resolution of the ADO is increased across one or more subranges of interest and decreased in less useful subranges.

FIG. 5 illustrates a computer serial bus system 200 incorporating an analog-to-digital converter 202 for use with a system backplane 206 in accordance with an aspect of the invention. An integrated circuit 210 comprises at least one data source 212 that produces at least one signal for transmission over the system backplane 206. These signals can comprise any type of electronic signal that can be sent via a backplane arrangement, such as data signals, address signals, and control signals. A serializer 214, serializes the at least one signal at a first data rate into a signal at a second, higher data rate.

The serializer 214 can multiplex the signals according to any appropriate method for combining multiple signals such as time division multiplexing, frequency division multiplexing, and code division multiplexing. In an example embodiment, a form of time division multiplexing is used to serialize the input signals into a single, high data rate signal.

The multiplexed signal is used to drive a transmitter 216 that provides a modulated analog signal across the backplane 206.

The transmitter 216 can utilize an appropriate modulation scheme for sending the signal, for example, pulse amplitude modulation.

The signal is received at a second integrated circuit 220 at a receiver 222. The receiver 222 includes an analog-to-digital converter 202 in accordance with an aspect of the invention to convert the signal into a series of digital values. The demodulated signal is then deserialized at a deserializer 226 to reconstruct the original at least one signal. The at least one deserialized signals are then provided to one or more associated destinations 228 at the second integrated circuit 220.

In view of the foregoing structural and functional features described above, a methodology in accordance with various aspect.s of the invention will be better appreciated with reference to FIG. 6. While, for purposes of simplicity of explanation, the methodology of FIG. 6 is shown and described as executing serially, it is to be understood and appreciated that the invention is not limited by the illustrated order, as some aspects could, in accordance with the invention, occur in different orders and/or concurrently with other aspects from that shown and described herein. Moreover, not all illustrated features may be required to implement a methodology in accordance with an aspect the invention.

FIG. 6 illustrates a methodology 250 for configuring an analog-to-digital converter (ADC) in accordance with an aspect of the invention. The methodology 250 begins at 252, where an overall voltage range for an analog input signal is determined.

For example, the output of the analog signal can be observed for a brief period to determine a maximum amplitude for the signal.

The determined voltage range can be used to scale comparator thresholds associated with a plurality of comparators comprising the ADC to an appropriate voltage level.

At 254, a slicer subrange is defined that contains information of use to a slicer associated with the digital receiver. The slicer receives a digital value from the ADC that has been modified by a correction value from a decision feedback equalizer (DFE) that is intended to correct for intersymbol interference (ISI) within the analog transmission. The amount of 1ST correction that can be applied by the DFE is limited in each direction to a maximum positive value and a maximum negative correction value. In an example implementation, these values can be equal and opposite in value. The slicer compares the corrected value to a decision threshold to determine a symbol associated with the sampled digital value. In accordance with an aspect of the invention, the slicer subranqe is bounded to exclude values that cannot be adjusted past the decision threshold by a maximum correction from the DFE. Accordingly, the slicer subrange includes a maximum voltage equal to the sum of the absolute value of the maximum negative correction voltage and the decision threshold and a minimum voltage equal to the difference between the decision threshold and the absolute value of the maximum positive correction voltage.

Alternatively, the slicer subrange can be determined to encompass all expected values of the main cursor in a signal.

For example, each symbol comprising the signal can be represented by a pulse having a peak amplitude equal to a first voltage or a trough value equal to a second voltage, generally equal and opposite to the first voltage. The slicer subrange can be selected to span these voltages. Depending on the implementation, the slicer subrange can be defined to encompass a peak voltage equal to the first voltage adjusted by a maximum positive ISI correction, and a trough voltage equal to the second voltage adjusted by a maximum negative ISI correction.

At 256, one or more timing subranges associated with a timing recovery portion of the analog-to-digital converter can be defined. The one or more timing subranges can represent a portion of the data that, in combination with the slicer subrange, contains information useful in correcting the sampling times associated with the ADC. Generally, these subranges will be determined as a proportion of the overall voltage prior to run-time operation of the ADC. In an example implementation, the timing subranges were found empirically to comprise two timing subranges, one at each extreme of the voltage range. In some implementations, no timing information is necessary from voltage ranges outside of the slicer subrange, and no timing subrange need be defined. At 258, at least one portion of the overall voltage range is defined as lacking information of interest to the digital receiver. For example, once the slicer range and the one or more timing ranges are identified, there will be at least one voltage gap between the identified ranges that contributes no useful information in retrieving information from the signal. It will be appreciated that in some implementations, the timing recovery will not require information from ranges outside of the slicer subrange. In these implementations, the ADC can simply be configured to clip values outside of the slicer subranqe t.o respective minimum or maximum values of t.he slicer subrange.

At 260, comparator thresholds associated with the plurality of comparators comprising the ADO are selected such that the comparator thresholds fall within the overall voltage range for the signal, but not within the at least one voltage subrange.

Accordingly, the comparator threshold values are unevenly distributed across the overall voltage range, with no thresholds falling within those subranges lacking useful timing or slicing information, and a denser concentration of threshold values within either or both of the at least one timing subrange and the slicer subrange than would be expected, given an even distribution. Accordingly, the resolution of the ADO in the useful ranges can be increased at little or no cost in chip space or power.

What has been described above includes example implementations of the invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the invention are possible.

Accordingly, the invention is intended to embrace all such alterations, modifications, and variations that fall within the scope of the claimed invention.

Claims

CLA I MS

What is claimed is: 1. A digital receiver system for a high-speed serial communications system that receives and interprets an input signal having an associated signal voltage range spanning a minimum signal. voltage and a maximum signal voltage, comprising: an analog-to--digital converter (ADC), that, at each of a plurality of sample times, converts at least a portion of the input signal into a digital value representation of the signal; a slicer that determines an associated symbol value for the input signal at each sample time based on at least a portion of the digital value representation representing a subrange of the signal voltage range that is less than the signal voltage range; and a timing recovery portion that adjusts the timing of the plurality of sample times according to the digital value provided by the ADC.

2. The system of claim 1, wherein the ABC comprises: a first set of at least one comparator having respective associated thresholds within the subrange of the signal voltage range associated with the slicer; a second set of at least one comparator having respective associated thresholds within a second voltage range that is not contiguous with the signal voltage range associated with the slicer; and a third set of at least one comparator having respective associated thresholds within a third voltage range that. is not contiguous with the one of the subrange of the signal voltage range associated with the slicer and the second voltage range; and wherein the digital value representation produced by the ABC includes the outputs of the first. set of set of at least one comparator, the second set of at least one comparator, and the third set of at least. one comparator and the portion of the digital value representation received by tue slicer does not inc:Lude the outputs of the second set of at. least one comparator and the third set of at least one comparator.

3. The system of claim 1 or 2, wherein the ADO is configured to clip the input signal at respect.ive minimum and maximum voltages associated with the subrange of the signal voltage range associated with the slicer, such that signal information outside of this voltage range is not provided to the slicer and the timing recovery portion.

4. The system of any of claims 1 -3, wherein the high-speed serial communication comprises a plurality of pulses representing at least two symbols having associated characteristic amplitudes, and the associated voltage range of the ADO is defined as to range from a maximum characteristic amplitude associated with the at least two symbols to a minimum characteristic amplitude associated with the at least two symbols.

5. The system of any of claims 1 -4, further comprising a decision feedback equalizer operative to apply a limited amount of correction to the output of the ADO to correct for intersymbol interference (ISI) / the second voltage range being determined as a function of the limited amount of ISI correction - 6. An integrated circuit incorporating the digital receiver system of any of claims 1 -5.

7. A digital receiver system, comprising: an analog-to-digital converter (ADC) that, at each of a plurality of sample times, converts an analog input signal into a digital value, comprising: a first set of at least one comparator having respective associated thresholds within a first voltage range; a second set of at least one comparator having respective associated thresholds within a second voltage range that is not contiguous with the first voltage range; and a third set. of at least one comparator having respective associated thresholds within a third voltage range that is not contiguous with the one of the first voltage range and the second voltage range; a slicer that receives the output of the second set of at least one comparator and determines an associated symbol value for the analog signal at each sample time; and a timing recovery portion that receives the output of at least the first set of at least one comparator and the third set of at least one comparator and adjusts the timing of the plurality of sample times.

8. The system of claim 7, further comprising a decision feedback equalizer operative to apply a limited amount of correction to the output of the ADC to correct for intersymbol interference (1ST) , the second voltage range being determined as a function of the limited amount of 1ST correction.

9. The system of claim 8, wherein the slicer has an associated slicer level, and the second range has a lower bound equal to the voltage of the difference between the slicer level voltage and a maximum amount of ISI correction associated with the decision feedback equalizer and an upper bound equal to the sum of the slicer level voltage and the maximum amount of 1ST correction associated with the decision feedback equalizer.

10. The system of any of claims 7 -9, wherein the first voltage subrange represents an uppermost portion of a voltage range associated with the ADC, the third voltage subranqe represents a lowermost region of the voltage range associated with the ADC, and the second subrange represents a central region of the voltage range associated with the ADC.

11. The system of claim 10, wherein the second set of at least one comparators includes a plurality of comparators having associated voltage thresholds, the difference between a first threshold voltage associated with the second set of comparators and a second threshold voltage associated with the second set of comparators being less than a difference between a lower bound of the first voltage subrange and an upper bound of the second voltage subrange.

12. The system of claim 10 or 11, the resolution of the ADO being enhanced within the second voltage region, such that a difference between a largest comparator threshold associated with the first set of comparators and a next largest comparator threshold associated with the first set of comparators is greater than a difference between a largest comparator threshold associated with the second set of comparators and a next largest comparator threshold associated with the second set of comparators.

13. The system of any of claims 7 -12, further comprising at least one comparator having an associated comparator threshold that does not fall within one of the first, second, and third voltage range, the at least one comparator being disabled such that it does not consume power.

14. An integrated circuit incorporating the digital receiver system of any of claims 7 -13.

15. A method for configuring an analog-to-digital converter (ADC) for use with a digital receiver incorporating a decision feedback equalizer, comprising: determining an associated overall voltage range for an input signal; determining at least one voltage subrarige that does not contain information of interest to the digital receiver; and selecting comparator threshold values for the analog-to-digital converter such that the comparator thresholds fall within the overall voltage range for the signal, but not within the at least one voltage subrange, such that the comparator threshold values are unevenly distributed within the overall voltage range.

16. The method of claim 15, wherein determining at least a first voltage subrange that does not contain information of interest to the decision feedback equalizer comprises: defining a slicer subrange bounded by an maximum voltage equal to the sum of the absolute value of a maximum negative correction voltage associated with the decision feedback equalizer and a decision threshold associated with the receiver and a minimum voltage equal to the difference between the decision threshold and the absolute value of a maximum positive correction voltage associated with the decision feedback equalizer; determining at least one timing subrange associated with a timing recovery portion of the digital receiver; and defining at least one portion of the overall voltage range falling between the slicing subrange and the at least one timing subrange as the at least one voltage subrange that does not contain information of interest to the digital receiver.

17. The method of claim 16, wherein determining at least one timing subrange includes determining the at least one timing subrange as a proportion of the overall voltage range empirically prior to operation of the ADC.

18. The method of claim 16 or 17, wherein the at: least one timing subrange comprises a first subrange at the uppermost portion of the overall voltage range and a second subrange at the lowermost portion of the overall voltage, and the slicer subrange is located at the center of the overall voltage range.

19. The method of any of claims 15 -18, wherein selecting the comparator threshold values for the analog-to-digital converter comprises selecting a disproportionate number of comparator thresholds that fall within the slicer subrange, such that the resolution of the ADC within the slicer subrange is superior to the resolution of the ADC within the at least one timing subrange.

20. The method of any of claims 15 -18, wherein selecting the comparator threshold values for the analog-to-digital converter comprises removing power from at least one comparator associated with the analog-to-digital converter having a comparator threshold within the at least one voltage subrange that does not contain information of interest to the digital receiver.