GB2439854A - Insertion of error detection circuits based on error propagation within integrated circuits - Google Patents

Insertion of error detection circuits based on error propagation within integrated circuits Download PDF

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Publication number
GB2439854A
GB2439854A GB0718193A GB0718193A GB2439854A GB 2439854 A GB2439854 A GB 2439854A GB 0718193 A GB0718193 A GB 0718193A GB 0718193 A GB0718193 A GB 0718193A GB 2439854 A GB2439854 A GB 2439854A
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United Kingdom
Prior art keywords
integrated circuit
errors
error detection
error
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0718193A
Other versions
GB0718193D0 (en
GB2439854B (en
Inventor
Jason Andrew Blome
Krisztian Flautner
Daryl Wayne Bradley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Publication of GB0718193D0 publication Critical patent/GB0718193D0/en
Publication of GB2439854A publication Critical patent/GB2439854A/en
Application granted granted Critical
Publication of GB2439854B publication Critical patent/GB2439854B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/004—Error avoidance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G06F17/5045—
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Abstract

A method of selecting where error detection circuits (20) should be placed within an integrated circuit uses simulation of a reference and test design with errors injected into the test design and then fan out analysis performed upon those injected errors to identify error propagation characteristics. Thus, registers (12) at which propagated errors are highly likely to manifest themselves or which protect key architectural state, or which protect state not otherwise protected can be identified and so an efficient deployment of error detection mechanisms achieved. Within an integrated circuit (68) output signals from inactive circuit elements may be subject to isolation gating (92, 94, 96, 98, 100) in dependence upon a detected current state of the integrated circuit. Thus, inactive circuit elements in which soft errors occur have inappropriate output signal; gated from reaching the rest of the integrated circuit and thus reducing erroneous operation.

Description

<p>GB 2439854 A continuation (56) cont BLOME J ET AL: "A
Microarchitectural Analysis of Soft Error Propagation in a Production Level Embedded Microprocessor". 38th INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 2005, pages 1-8, XP002364252 ANGHEL L ET AL: "Cost Reduction and Evaluation of a Temporary Faults Detecting Technique", 2000, pages 591 -598, XP010377522. The whole document.</p>
<p>CALDWELL D W ET AL: "A minimalist hardware architecture for using commercial microcontrollers in space" 1997, DIGITAL AVIONICS SYSTEMS CONFERENCE, 1997, pages 52-26, XP010256067, ISBN 0-7803-4150-3, figure 1.</p>
<p>(58) Field of Search by ISA:</p>
<p>INT CL GO6F Other: EPO-Internal</p>
GB0718193A 2005-09-22 2005-10-03 Insertion of error detection circuits based on error propagation within integrated circuits Expired - Fee Related GB2439854B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0519363.6A GB0519363D0 (en) 2005-09-22 2005-09-22 Error propagation in integrated circuits
PCT/GB2005/003800 WO2007034128A1 (en) 2005-09-22 2005-10-03 Insertion of error detection circuits based on error propagation within integrated circuits

Publications (3)

Publication Number Publication Date
GB0718193D0 GB0718193D0 (en) 2007-10-31
GB2439854A true GB2439854A (en) 2008-01-09
GB2439854B GB2439854B (en) 2010-12-01

Family

ID=35335286

Family Applications (2)

Application Number Title Priority Date Filing Date
GBGB0519363.6A Ceased GB0519363D0 (en) 2005-09-22 2005-09-22 Error propagation in integrated circuits
GB0718193A Expired - Fee Related GB2439854B (en) 2005-09-22 2005-10-03 Insertion of error detection circuits based on error propagation within integrated circuits

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GBGB0519363.6A Ceased GB0519363D0 (en) 2005-09-22 2005-09-22 Error propagation in integrated circuits

Country Status (5)

Country Link
US (1) US7926021B2 (en)
JP (1) JP4943427B2 (en)
CN (1) CN101273356B (en)
GB (2) GB0519363D0 (en)
WO (1) WO2007034128A1 (en)

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CN102073007B (en) * 2009-11-25 2013-06-26 台湾积体电路制造股份有限公司 System and method for detecting soft-fails
US8516356B2 (en) * 2010-07-20 2013-08-20 Infineon Technologies Ag Real-time error detection by inverse processing
US8384430B2 (en) 2010-08-16 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. RC delay detectors with high sensitivity for through substrate vias
US8453082B2 (en) * 2010-09-08 2013-05-28 International Business Machines Corporation Soft error verification in hardware designs
JP5609986B2 (en) * 2010-11-16 2014-10-22 富士通株式会社 Information processing apparatus, transmission apparatus, and control method for information processing apparatus
WO2014052936A1 (en) * 2012-09-28 2014-04-03 Arteris SAS Automatic safety logic insertion
US20150220667A1 (en) * 2014-02-06 2015-08-06 Infineon Technologies Ag Application-based verification coverage using metamodels
US9430599B2 (en) * 2014-02-18 2016-08-30 Optima Design Automation Ltd Determining soft error infliction probability
ES2947361T3 (en) * 2017-06-19 2023-08-07 Siemens Electronic Design Automation Gmbh System and method for the formal analysis of fault propagation
US11520963B2 (en) * 2017-06-19 2022-12-06 Onespin Solutions Gmbh System and method for formal fault propagation analysis
LU100321B1 (en) * 2017-06-19 2018-12-19 Onespin Solutions Gmbh Method for formal circuit verification
US11816410B2 (en) 2017-06-19 2023-11-14 Siemens Electronic Design Automation Gmbh System and method for formal fault propagation analysis
EP3553681B1 (en) * 2018-04-12 2022-08-17 Optima Design Automation Ltd Method and apparatus for error test coverage determination for a circuit by simulation
US10839877B1 (en) * 2019-04-23 2020-11-17 Nxp Usa, Inc. Register protection circuit for hardware IP modules
US20220198023A1 (en) * 2020-12-22 2022-06-23 Intel Corporation Simulation state to detect transient execution attack
CN112580282B (en) * 2020-12-23 2023-04-07 海光信息技术股份有限公司 Method, apparatus, device and storage medium for integrated circuit design verification
US11797373B2 (en) * 2021-12-13 2023-10-24 Nxp B.V. System and method for managing faults in integrated circuits

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Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
ANGHEL L ET AL: "Cost Reduction and Evaluation of a Temporary Faults Detecting Technique", 2000, pages 591-598, XP010377522. The whole document . *
BLOME J ET AL: "A Microarchitectural Analysis of Soft Error Propagation in a Production Level Embedded Microprocessor". 38th INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 2005, pages 1-8, XP002364252 *
CALDWELL D W ET AL: "A minimalist hardware architecture for using commercial microcontrollers in space" 1997, DIGITAL AVIONICS SYSTEMS CONFERENCE, 1997, pages 52-26, XP010256067, ISBN 0-7803-4150-3, figure 1. *
MOHANRAM K ET AL: "Cost-effective approach for reducing soft error failure rate in logic circuits" PROCEEDINGS INTERNATIONAL TEST CONFERENCE 2003. vol. 1, pages 893-901, XP010685289, ISBN 0-7803-8106-8. *
MUKHERJEE S S ET AL: "A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor". MICROARCHITECTURE, 2003. MICRO-36. PROCEEDINGS. 36TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON 3-5 DEC 2003. pages 29-40, XP010674795, ISBN 0-7695-2043-X *
SEONGWOO KIM ET AL: "Soft error sensitivity characterization for microprocessor dependability enhancement strategy" PROCEEDINGS INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS. 2002. pages 416-425, XP010600322, ISBN 0-7695-1597-5 *

Also Published As

Publication number Publication date
WO2007034128A1 (en) 2007-03-29
GB0519363D0 (en) 2005-11-02
CN101273356A (en) 2008-09-24
CN101273356B (en) 2012-03-07
US20090049331A1 (en) 2009-02-19
JP2009502037A (en) 2009-01-22
JP4943427B2 (en) 2012-05-30
GB0718193D0 (en) 2007-10-31
US7926021B2 (en) 2011-04-12
GB2439854B (en) 2010-12-01

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PCNP Patent ceased through non-payment of renewal fee

Effective date: 20161003