GB2429611A

GB2429611A - A DAB receiver channel decoder

Info

Publication number: GB2429611A
Application number: GB0517231A
Authority: GB
Inventors: Mingying Lu; Guoyu Wang
Original assignee: Individual
Current assignee: Individual
Priority date: 2005-08-23
Filing date: 2005-08-23
Publication date: 2007-02-28
Anticipated expiration: 2025-08-23
Also published as: GB0517231D0; GB2429611B

Abstract

A Coded Orthogonal Frequency Division Multiplex (COFDM) cannel decoding apparatus in which the frequency deinterleaving (or bit deinterleaving or symbol deinterleaving) step is merged with the bit-reversing step of the Fast Fourier Transform (FFT) processor (block 1). The combined function may also be combined with certain demodulation function (DQPSK or QAM) (Figure 6). The hardware/software arrangement of the COFDM decoder is simplified and has reduced memory requirements for storing intermediate results. In contrast to conventional arrangements (Figure 1) wherein the decoder performs the steps in the order of FFT processing the demodulation then deinterleaving the proposed arrangement performs FFT processing then deinterleaving before demodulation. The arrangement may be used for example in DAB, DVB-T, DVB-H or DRM systems.

Description

Means for Implementing a DAB Receiver Channel Decoder Conventional DAB

channel decoding procedure and its implementation Figure 1 shows a. conventional channel decoder block diagram, using DAB mode I as an example to indicate the size of mernones Without loss of generality, this invention can be apphed also to any of the four DAB inoaes, and to other receiver types uslng COFDM charmel decoder, such as DVB-T/H and DRM In this conventional DAB channel decoder, the received DAB symbol (I, Q data in the time domain) is first trausfoimed into 2048 frequency bins (via FFT block 1). Data in each of these bins is resolved into 1, Q data pairs (one pair per bin), through DQPSK demodulation. Each I, Q bin will ultimately represent 2 hits of data, but at this stage the result of the demodulation is "soft data" and may be represented by 2, 4, or 6 hits.

Because the DQPSK derncdu1ation requires information from both the current and preceding (history) DAB symbols, it must operate from two sets of FFT results (the cui.Tent and preceding sets of results), and these are stored in RAM 3 and 4.

Data in. the frequency bin.s has been deliberately shuffled to spread frequency fading effects introduced during transmission, and the shuffled bins are realigned in a process called frequency deinterleavmg (in DAB) or symThol deinterleâving (in DVB- T/H) or bit deinterleaving (in DRM). Not all 2048 pairs of I, Q data are used, the frequency deinterleaving process recovers the 1536 actual I, Q paiis per DAB symbol in Mode 1.

For further forward error correction (FEC). the data are also shuffled in the time domain, with data spread across II 6 CIF (Common Interleaved Frame) frames. Thus a second deinterleaving process is implemented in the receiver (time demterleaver) Both demterleaving processes are implemented through buffer memories (P.AM I arid RAM 2) in which aJJ of the interleaved data is stored, and the write and read sequences are preprogrammed to deliver the correct grouping or sequence of data.

The desired message data at this point is also still embedded within a redundant code, and may still be in soft decision form. This soft decision, redundant coded data is decoded to a hit-stream of binary data through a Viterbi Decoder. When the Viterbi decoder reads the soft decision data from the time deintericaving RAM, puncturing information is provided via Block 5, and a middle value is inserted for punctured hit data.

The size of the RAM I is normally 2048 x 2 x N bits for 2048 pairs of I, Q data, where N is the number of hits of soft decision data, usually 2, 4, or 6. For example, if N is4 hits, then RAM I would be 16,384 bits.

The size of RAM 3 & 4 combined is nonnally 2 x 2048 x 2 x d_w, where d_w is the data width of the FFT processor, usually 16 or more bits. Thus RAM 3 and RAM 4 together usually comprise 2 x 4096 x d_w bits (2048 bins, each bin has two items of data, I, Q, each data is dw bits wide). Block 8 is DQPSK read address generator that selects data from RAM3 and RAM4 for DQPSK processing.

RAM 2 normally stores 16 ClFs of (n_symbol x 1536) pairs of 1,Q data, where n_symbol is the number of symbols to be decoded in the DAB channel decoder, which relates to the total data rate that is desired to decode. The data rate of each sub- channel in i)AB ensemble is varied, from 64Kbit to l92Kbit for audio program, 384Kbit or higher for video program, 8-32Khit for data/text, or any data rate which is integer of 8Kbit. If the decoding rate is full, the n_symbol is 18 in DAB mode I. Blocks 3 and 4 are address pattern generators which are normally implemented as sequentially-addressed ROM look-up tables storing the required patterns of write and read addresses to achieve the desired deinterleaving.

Block 7 is energy disperse processor which inverts an encoding process to disrupt undesirable regular patterns of data. This is included here for completeness of COFDM decoding procedure.

The Invented DAB Channel Decoding Procedure The conventional 1)AB architecture can be simplified if the ordering of the DAB channel decoding procedures is altered. This invention describes an altered DAB channel decoding procedure, which moves the frequency deinterleaving function to the place after the FFT, but before the DQPSK. Deinterleaving the frequency bins before DQPSK demodulation does not alter the functionality of the COFDM channel decoder.

The FFT processor itself normally contains a final dc-shuffling step (called the bit- reverse step because the shuffle can be done simply by reversing the binary address patterns of the data). The invented channel decoding method merges the DAB frequency deinterleaving function with the bit- reverse step of the FFT processor. Both steps re-order the same set of data, and they can therefore be executed as one combined re-ordering that achieves the expected result. The conventional and altered FFT architectures are shown in Figure 2 & Figure 3. The size of FFT result RAM in Figure 3 is 1536 x 2 x n_bit, which is smaller than the size of FFT result RAM in Figure 2.

Figure 4 shows one implementation of the invented DAB channel decoder block diagram, using the merged FFT and frequency deinterleaving processor. It is obvious that block 3 and RAM I in Figure 1 are eliminated from the hardware implementation of the invented method in Figure 4. It is able to select the 1536 1, Q pairs before the DQPSK process, so the size of the history and current symbol RAMs (RAM 3 & RAM 4) is smaller (1536 words) in Figure 4 than that (2048 words) in the conventional method in Figure 1.

Figure 5 and Figure 6 show a further potential improvement based on the new procedure, invented implementation 2. The FFT processor is implemented without the bit-reverse step, and the result of the FFT is directly available via two FFT working RAMs, which as befbre will hold the current and history DAB symbols. here the bit- reverse step of FFT and the step of frequency deinterleving are implemented by virtue of the sequence in which the FFT working RAM data is read out and sent to the 1)QPSK processor. Block 8 generates desired addresses to perform this merged reading sequence. The total system RAM requirement is further reduced in this implementation, as shown in the following comparison.

Comparison of Memory and Processor Requirements As summarized in the following table, the invented method offers significant size and organizational advantages in terms of RAM requirements over the conventional architecture (assumes 4 bits of soft decision data, 16 bits of FFT output data, and 18 DAB symbols): Conventional Invented Invented Implementation Implementation I implemenlation 2 (the frequency (the bit-reverse step of deinterleaving FF1 and frequency merged with the bitdeinterleaving merged reverse step of FF1) with data reading sequence ot DQFSK -- _______________ ______________ process) FFT working 2048 x 2 x l6bit 2048 x 2 x Iobit 2 x 2048 x 2 x lohil

RAM ____ ____

RAM 1 2048 x 2 x l6bit - - RAM3 f ftAM4 2x2048x2x I6hit 2x l536x2x16bit saving over the 0 96Kbit, I 28Kbit, conventional 37.5% 50% iIcmcntation - - ___________ In addition to these RAM savings, the invented method reduces the DQPSK processing requirements: Data processed per DAB Symbol Conventional 2048 pairs Invented 1536 pairs Implementation It will be appreciated that the invented means described and illustrated here may he realized in software, or in hardware, or in a mixture of these two, with some functions being executed in hardware and some in software.

Extension to other COFDM decoders The techniques disclosed here are generally applicable to all COFDM decoders, including those other than DAB. For example, the same techniques may he used to save power and cost in the COF1)M decoder of I)VB-T (1)igital Video Broadcast Terrestrial), I) V13-IJ (Digital Video Broadcast Handheld) receivers.

Claims

claims Means for rea!izrng a digital COFDM decoder in which the frequency

deinterleaving (in DAB) or the symbol deinterleaving (in DVB-T/1I) or the bit dcinterleaving (in DRM) function precedes the demodulator, such as DQPSK and QAM, in the sense of dataflow through the decoder.

2. Means as in I, where the frequency/symbol/bit deinterleaving function is merged with the FFT bit-reverse function.

3. Means as in I, where the frequency/symbol/bit deinterleaving function and FFT bit-reverse function are effected within a single ordered and merged reading sequence of data from FFT memories associated with the demodulation.

Amendments to the claims have been filed as follows

C

Claims 1. A COFDM decoder in which the frequency deinterleaving in DAB or the symbol deinterleaving in DVB-'I'/H or the bit deinterleaving in DRM function precedes the demodulator, such as DQPSK and QAM, in the sense of dataflow through the decoder.
2. Means as in Claim 1, a COFDM decoder wherein the frequency/symbol/hit deinterleaving function is merged with the FF1' bit-reverse function.
3. Means as in Claim I, a COFI)M decoder wherein the frequency/symbol/bit deinterleaving function and FFT bit-reverse function are effected within a single ordered and merged reading sequence of data from FFT data buffers during the DQPSK/QAM etc. demodulation.
4. A COFDM decoder in I)AB according to Claim 1 & 2, comprises: - At least one FF'l' + frequency deinterleaving combined processor which converts DAB symbol from time domain to frequency domain, and select only valid frequency carrier bins by removing invalid frequency carrier bins from all carrier bins; - FFT output data buffers which are provided fur the valid frequency carrier bins of two DAB symbols ( current and history); - At least one DQPSK demodulator which further derives the soft- decision data by processing the valid frequency carrier bins only; - At least a time deinterleaving procedure precedes to a Viterbi decoder; - At least one Viterbi decoder which recovers binary data from the soft- decision data.

- At least one energy disperser which reverses a disperse process at COFDM encoder side.
5. A COFDM channel decoder structure according to Claim 4, wherein the combined bit reverse and the frequency/symbol/bit deinterleaving procedure are completed before DQPSK demodulation, and implemented in a re-ordered addresses sequence during writing FFT result data to its result data buffers.
6. A COFI)M decoder in DAB according to claim 1, 2 & 3, comprises: - At least one FFT without bit reverse step which converts DAB symbol from time domain to frequency domain, the FFT result data is available from its working data buffers which store two DAB symbols (current and history'); At least an address generator which implements the FF1' bit reverse, the frequency deinterleaving and the reading sequence of the DQPDK demodulation into a single re-ordered address sequence.

- At least one DQPDK demodulator which further derives the soft-decision data from the valid carrier bins; At least a time deinterleaving procedure precedes to a Viterbi decoder: - At least one Viterbi decoder which recovers binary data from the soft- decision data.

- At least one energy disperser which reverses a disperse process at COFDM encoder side.
7. A COFE)M channel decoder structure according to Claim 6, wherein the FFT result without hit reverse step stays in FF1' working data buffer, the combined hit reverse and the frequency/symbol/bit deinterleaving procedure are completed during data reading sequence of DQPSK demodulation, and implemented with the data reading sequence of DQPSK demodulation in a single re-ordered addresses sequence.