GB2428509A - Driver circuit for a display element - Google Patents

Abstract

A display driver (205) for a display element such as an LCD is used for generating a drive signal in response to a multi-bit input signal. The driver (205) comprises an adder 302 arranged to repetitively perform addition of the input signal to a feedback signal to generate a multi-bit sum signal and a single-bit carry signal, where the carry signal represents the sum of the input signal and the feedback signal. A latch 303 receives the sum signal for each repetition and stores it to form the feedback signal for the next repetition. The output drive signal is formed in dependence on the carry signal; ideally the drive signal represents the magnitude of the carry signal. The adder 302 preferably repeats the addition at a frequency greater than 50Hz. The driver (205) may comprise a second latch 301 for temporarily storing the multi-bit input signal and a filter (204) may be provided for smoothing the single-bit carry signal.

Description

1 2428509

DRIVER CIRCUIT FOR A LIQUID CRYSTAL DISPLAY

The present invention relates to a driver circuit for a display device. In particular, the present invention relates to a simple circuit for converting a digital signal to an analogue signal that is suitable for driving a liquid crystal display.

A typical LCD consists of a layer of light-polarising liquid (the "liquid crystals") contained between two transparent polarising sheets. The liquid crystals used for LCDs are typically nematic, which means that the molecules tend to adopt an ordered ladder-type structure. In LCDs, the liquid crystals have a twisted structure.

This twisted structure is generally created by sandwiching a layer of liquid crystals between two polarising sheets that have microscopic grooves in their surface.

When a layer of liquid crystals is applied to a sheet having microscopic grooves in its surface, the crystals closest to the surface of the sheet align themselves with those grooves. A second polarising sheet, which has grooves at 90 to the grooves in the first sheet, may then be placed on the opposite surface of the liquid crystal layer. The liquid crystals closest to the second sheet also align themselves with the grooves in its surface, which are at 900 to those in the first sheet. Each successive layer of crystals is therefore gradually twisted, until the uppermost layer is at a 900 angle to the bottom layer.

The molecules within a liquid crystal display structure also polarise light to match their own orientation. In an LCD, the first polarising sheet polarises incoming light to be in the same orientation as the grooves in the sheet's surface. Consequently, light transmitted through the first polarising sheet has the same orientation as the liquid crystal molecules at the surface of the first sheet. The twisted structure of the liquid crystal then gradually rotates the incoming, polarised light so that when it reaches the second polarising sheet, it has been rotated by 90 . The second polarising sheet also polarises light to be at the same orientation as the grooves in its surface. Therefore, the second polarising sheet filters light at 900 to the first polarising sheet. As the light is rotated by 900 by the liquid crystal structure, when it reaches the second polarising sheet it is at the correct orientation to be transmitted through the second polarising sheet. Therefore, the LCD transmits incoming light and appears to be transparent.

The twisted arrangement of liquid crystals in the LCD can be made to untwist by applying an electric charge to the liquid crystals. Therefore, if an electric charge is applied to the liquid crystal layer, the twisted structure untwists and incoming light is no longer rotated through 900. Therefore, light reaching the surface of the second polarising sheet is at the same orientation as when it was transmitted through the first polarising sheet. As the light filters of the first and second polarising sheets differ by 900, the light reaching the surface of the second polarising sheet is blocked by the filter and the LCD appears to be opaque.

LCDs use this effect to display information. By attaching transparent electrodes to one of the polarising sheets, an electric charge can be applied to the layer of liquid crystals beneath the electrode. When an electric charge is applied to the liquid crystal layer, the area of the display covered by the electrode will not transmit light, whereas the rest of the display will be transparent. By backlighting the LCD display or by reflecting ambient light through the display, opaque sections of the display can be used to display information.

Each segment of an LCD may have has its own electrical contact through which an electrical signal is supplied. The electrical signal that drives each segment is provided by an external circuit. However, this arrangement becomes unwieldy when the number of segments increases. Therefore, larger displays use what is known as a passive matrix structure. In this structure there is one set of contacts for each row of segments (or pixels) and another set of contacts for each column. The disadvantage of this arrangement is that only one pixel can be addressed at any one time. The remaining pixels have to remember their previous state until the control circuit revisits them, which causes slow response time and reduced contrast. This problem is addressed by using what is known as an active matrix structure.

An active matrix LCD is also known as a thin film transistor (TFT) display. An example of an active matrix display is shown in figure 1. The active matrix 101 is similar to the passive matrix, in that it consists of a grid of conductors 102, 103 with a pixel 104 located at each intersection of the grid. However, an active matrix has a transistor located at each pixel intersection. Using a transistor at each intersection means that less current is required to control the luminance of a pixel. Similarly to the passive matrix structure, to address a particular pixel in the active matrix, the appropriate row is switched on and a charge is passed down the appropriate column.

In both active and passive displays, the contrast of the display can be controlled by limiting the amount by which the structure of the liquid crystal "untwists" at each pixel.

This is achieved by carefully controlling the voltage applied to a particular pixel.

Modern complex LCDs are driven by complex waveforms on the common and segment lines, which effectively act as row and column addressing for each segment of the display. The complex waveforms allow each segment to be controlled with the minimum number of pins. Displays may typically have up to eight common signal lines. However, although more than eight common signal lines are possible, with each additional common line in the multiplexed array the waveforms required to drive the LCD become progressively more complex. For example, in a four-way multiplexed display there are four common signals and four different voltage levels required on all of the voltage and segment lines. Generating these voltage levels requires specialised, on-chip analogue circuitry.

Therefore, there is a need for an improved method and apparatus for generating the required waveforms for driving an LCD.

According to an embodiment of the present invention, there is provided a display driver for generating a drive signal for driving a display element in response to a multi-bit input signal, the display driver comprising an adding unit arranged to repetitively perform addition of the input signal to a feedback signal to generate a multi-bit sum signal and a single-bit carry signal representative of the sum of the input signal and the feedback signal and a latch for receiving the sum signal for each repetition and storing it to form the feedback signal for the next repetition, the driver being arranged to form the drive signal in dependence on the carry signal.

The display driver preferably comprises a second latch for storing a received value of the input signal, the adding unit being arranged to perform addition of the value stored in the second latch to the value stored in the first latch to generate the sum and carry signals The adding unit may be arranged to repeat the said addition at a frequency greater than 50 Hz. Preferably, the adding unit is arranged to repeat the said addition at a frequency sufficiently high to substantially avoid flicker of the display element.

Preferably, the drive signal is representative of the magnitude of the carry signal.

The display driver may comprise a filter for smoothing the magnitude of the carry signal. The drive signal is preferably representative of the output of the filter. The display element is preferably connected so as to receive the drive signal and operate with a brightness dependent on the drive signal.

The present invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 shows a liquid crystal display having an active matrix structure; Figure 2 shows an LCD driver circuit according to an embodiment of the present invention; Figure 3 shows the waveform generator component of the LCD driver circuit in more detail; and Figure 4 shows examples of digital signals output by the waveform generator and the resulting analogue signals obtained by filtering those digital signals.

Embodiments of the present invention can provide simple, low cost circuits for controlling LCD displays that uses predominantly digital components. Figure 2 shows an LCD driver circuit according to an embodiment of the present invention. The driver circuit can be considered as a simple digital-to-analogue converter (DAC), shown generally at 205. The DAC 205 comprises a waveform generator 201, which is a logic unit for converting an incoming N-bit parallel data stream into a single-bit output data stream, and an off-chip single pole RC filter 204, which consists of a resistor 202 and a capacitor 203. The waveform generator is supplied with a parallel data stream of N bits from the CPU and outputs a single bit data stream to the RC filter.

The RC filter is a low-pass filter that filters the single-bit data stream to produce an analogue signal suitable for driving an LCD display.

Figure 3 illustrates the waveform generator 201 in more detail. The waveform generator 201 consists of two N-bit latches 301, 303 and an adder 302. The waveform generator 201 is clocked at a much higher rate than the data that is fed to it through the N-bit parallel data line. Therefore, the DAC 201 of the present invention can be considered as a noise-shaped DAC. For example, the waveform generator may be clocked 256 times faster than the incoming data. This value is given for the purposes of example only and the present invention may be implemented using any suitable clocking frequency.

The N-bit latch or register 301 acts as a buffer between the incoming data stream and the waveform generator by holding an incoming N-bit value for the period of those N bits. The latch 301 therefore holds the value of the input signal until the next N-bit value is received on the incoming parallel data line. For example, if the incoming data stream has a frequency of lIT Hz, then the latch 301 will hold an incoming N-bit value for T seconds before receiving the next incoming N-bit value.

The adder 302 takes the N-bit value being held by the latch 301 and adds it to the N- bit result of the previous addition, which is held in N-bit latch 303. The resulting N-bit value is fed-back to be stored in N-bit latch 303 and used in the next addition step.

The carry bit from the addition operation is output from the waveform generator as a single-bit data stream, 304 and input into the RC filter illustrated in figure 2. The RC filter removes the high frequency components of the single-bit data stream, effectively performing a smoothing' operation, which results in an analogue waveform that can be fed to an LCD display.

The operation of the LCD driver circuit will now be described in more detail with reference to figure 4 and tables 1 to 3.

Figure 4 and tables I and 2 relate to an illustrative embodiment of the present invention in which the LCD display is a four-way multiplexed display. In the four-way multiplexed display there are four common signal lines, and four different voltage levels are required to control the display via the common and segment lines.

Therefore, the DAC 201 receives a 2-bit incoming parallel data stream from the CPU and latches 301, 303 of the waveform generator are 2-bit latches.

As explained above, the waveform generator of the present embodiment is clocked at a higher frequency than the incoming data stream from the CPU. So, the adder 302 is clocked at a higher frequency than the incoming data. Multiple addition operations are therefore performed on a single 2-bit value, until that value is replaced in latch 301 by a new value output from the CPU.

To illustrate the operation of an embodiment of the present invention in a straightforward manner, tables I and 2 contain the bit values held by the latches 301, 303 and output by the single-bit carry out signal 304 for each clock cycle of the waveform generator when the 2-bit values incoming from the CPU are 01' and 10' respectively.

Table I lists the values stored in the latch 301, the result from the addition operation performed by the adder 302, the carry-out bit that is output by the adder as a single- bit data stream 304 and the value stored in latch 303 in the feedback loop for each clock cycle when the CPU outputs 01' on the 2-bit parallel data stream. As shown in table 1, the input of 01' from the CPU generates a single-bit output stream that is a sequence of three zeros and a one. Although table I only lists the output bits for the first 8 clock cycles, the values generated during subsequent clock cycles will follow the same pattern of ones and zeros and this pattern will continue until a new 2- bit value is output by the CPU.

For the purposes of example only, the result of the last addition operation to be performed using the previous 2-bit value received from the CPU has been assumed to be 00' in table 1. Obviously the value of the previous result affects the summation and result and carry-out bit for the first few clock cycles with a new 2-bit value.

However, the influence of the previous result is limited and the singlebit output stream will stabilise around the normal pattern of ones and zeros e.g. for an incoming value of 01' the output data stream will stabilise to a sequence of three zeros followed by a one.

The single-bit data stream that results from the carry-out of the adder is output to the single-pole, off-chip filter 202 (see figure 2). The sequence of ones and zeros generated by having the value 01' output from the CPU, which is listed in the final column of table 1, is shown as signal 401 in figure 4. This signal is smoothed' by the RC filter 204 to produce an analogue signal 402. The average voltage level of the analogue signal is approximately equal to the voltage level associated with the CPU output value of 01', which might be e.g. IV according to table 3. The signal output by the RC filter 204 will be somewhat bumpy'. However, whereas some display technologies respond to peak or average voltage or current levels, LCDs are sensitive to RMS (root-mean-square) voltage. Therefore, an LCD segment can still operate from an input voltage that fluctuates to some extent an ideal voltage level.

The amount of fluctuation that occurs around the ideal voltage level of the analogue signal produced by the RC filter depends on the RC time constant of the filter, which is a function of the resistance of resistor 202 and the capacitance of capacitor 203.

The larger the time constant, the smoother the resulting analogue signal will be.

However, a large time constant means that the response time of the filter is slow.

The signals illustrated in figure 4 are simplified for explanatory purposes and it should be understood that the present invention is not limited to these specific waveforms. In particular, it should be noted that with LCDs it can be necessary to reverse the polarity of the voltage at all segment locations at regular intervals, so that a zero net DC voltage is applied, in order to prevent irreversible electrochemical action from destroying the display.

Table 2 lists the bit-values that result when the DAC receives an input value 10' from the CPU. This input value represents the second highest voltage level of the 4-way multiplexed display, which could be e.g. 2V according to table 3. As can be seen from the final column of table 2, the carry-out signal alternates between ones and zeros. Therefore, when the single-bit stream 403 is fed to the filter 204, the resulting analogue signal has a higher average voltage level than was generated from signal 401. This is to be expected, since the larger the N-bit value output from the CPU, the greater the proportion of ones' in the single-bit output stream.

Table 3 gives examples of voltage levels that might be required in the analogue input signal required to drive a display and the corresponding values output from the CPU.

It should be understood that these values are given for the purposes of example only, and are not intended to limit the present invention to these voltage levels.

From the above description and the accompanying figures, it can be seen that the present invention provides a simple method for generating an analogue signal suitable for driving a display. Firstly, a higher frequency, single-bit data stream is generated from an incoming N-bit data stream in which the ratio of ones to zeros is proportional to the N-bit value of the incoming data stream, and secondly, the single- bit data stream is smoothed' to produce the analogue signal required to drive a display.

The LCD driver circuit of embodiments of the present invention can be advantageous because of the small size of the on-chip implementation. For example, if a four-way multiplex signal were required then the DAC resolution (N) would only need to be 2 bit. The resulting logic would then consist of 2 off 2 bit latches and a 2 bit adder per signal line, which represents less than 30 logic gates (2-input NAND equivalent) and thus an LCD that had 4 common lines and 25 segment lines (able to have up to 100 individual segments) would have a digital gate requirement of less than 870. For example, in a modern semiconductor process, such as an "0. l8um" geometry, this would occupy less than 0.0087 mm2 of die area. The further advantage is that the circuit can be implemented in purely digital logic on the chip, rather than requiring on- chip specialised analogue circuits.

In the above description, the invention has been described in relation to a specific implementation in which the waveform generator consists of two latches or registers and an adder and the analogue signal is produced by a low-pass filter (e.g. as shown in figures 2 and 3). However, the present invention is not limited to this specific implementation i.e. to a circuit having these specific components, but instead encompasses all variations on the embodiments described herein that are suitable for putting the invention into effect.

Also, although the embodiments of the present invention described above have been described in relation to liquid crystal displays, it should be understood that the present invention is not limited to any particular type of display. Indeed, the present invention may be used to generate analogue drive signals for any suitable components.

The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims (8)

1. A display driver for generating a drive signal for driving a display element in response to a multi-bit input signal, the display driver comprising: an adding unit arranged to repetitively perform addition of the input signal to a feedback signal to generate a multi-bit sum signal and a single-bit carry signal representative of the sum of the input signal and the feedback signal; and a latch for receiving the sum signal for each repetition and storing it to form the feedback signal for the next repetition; the driver being arranged to form the drive signal in dependence on the carry signal.

2. A display driver as claimed in claim 1, comprising a second latch for storing a received value of the input signal, the adding unit being arranged to perform addition of the value stored in the second latch to the value stored in the first latch to generate the sum and carry signals

3. A display driver as claimed in claim I or 2, wherein the adding unit is arranged to repeat the said addition at a frequency greater than 50 Hz.

4. A display driver as claimed in any preceding claim, wherein the drive signal is representative of the magnitude of the carry signal.

5. A display driver as claimed in claim 4, comprising a filter for smoothing the magnitude of the carry signal and the drive signal is representative of the output of the filter.

6. A display driver as claimed in any preceding claim and the display element, the display element being connected so as to receive the drive signal and operate with a brightness dependent on the drive signal.

7. A display driver as claimed in claim 6, wherein the adding unit is arranged to repeat the said addition at a frequency sufficiently high to substantially avoid flicker of the display element.

8. A display driver substantially as herein described with reference to the accompanying drawings.