GB2425699A - Display apparatus and method using multiple graphics cards - Google Patents

Display apparatus and method using multiple graphics cards Download PDF

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Publication number
GB2425699A
GB2425699A GB0508548A GB0508548A GB2425699A GB 2425699 A GB2425699 A GB 2425699A GB 0508548 A GB0508548 A GB 0508548A GB 0508548 A GB0508548 A GB 0508548A GB 2425699 A GB2425699 A GB 2425699A
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United Kingdom
Prior art keywords
display card
chipset
socket
display
card
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0508548A
Other versions
GB0508548D0 (en
GB2425699B (en
Inventor
Cho-Hsine Liao
Ju-Yi Hung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Giga Byte Technology Co Ltd
Original Assignee
Giga Byte Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Giga Byte Technology Co Ltd filed Critical Giga Byte Technology Co Ltd
Priority to GB0508548A priority Critical patent/GB2425699B/en
Publication of GB0508548D0 publication Critical patent/GB0508548D0/en
Publication of GB2425699A publication Critical patent/GB2425699A/en
Application granted granted Critical
Publication of GB2425699B publication Critical patent/GB2425699B/en
Active legal-status Critical Current
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1438—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using more than one graphics controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Abstract

A display apparatus for a multi-display card and displaying method of the same is disclosed. The display apparatus for a multi-display card comprises: a first chipset with a first socket, a second chipset with a second socket, a first display card, a second display card, and a connector. The first display card is inserted into the first socket and the second display card is inserted into the second socket, and the connector is connected between the first display card and the second display card. The first display card and the second display card are controlled separately through the first chipset and the second chipset for handling image processing, and the first display card and the second display card are co-operated through the connector to output a video signal. Thereby, it increases the efficiency of the image processing.

Description

DISPLAY APPARATUS AND METHOD USING MULTIPLE
GRAPHICS CARDS
The present invention relates to a display apparatus and method, and more particularly to a display apparatus and method for multiple display (graphics) cards.
3D computer games and high-definition dynamic image technology has advanced at an astounding speed of late. There is a continuing need to provide faster image processing so as to process larger and larger amounts of data to meet the demands both of consumers and the producers of this kind of technology. For a computer system, the display (graphics) card is the main device for handling image processing. Hence, in order to accelerate processing speeds, it is not only necessary to increase the capabilities of the display card's Graphic Processing Unit (GPU), but also to use multiple display cards.
Reference is made to Fig. 1 that shows one system architecture according to the prior art, namely the architecture of a SLI (Scalable Link Interface). In SLI technology two display cards are inserted on a motherboard. A north bridge chipset 70 on the motherboard provides a first socket 71 and a second socket 72 has a separate PCI-E (PCI-Express) interface. A first display card 81 is inserted into the first socket 71 and a second display card 82 is inserted into the second socket 72. Moreover, a connector 90 is connected between the first display card 81 and the second display card 82 for transmitting data between the first display card 81 and the second display card 82.
Furthermore, the GPU of the first display card 81 and the second display card 82 provide support for communication protocols, and the first display card 81 and the second display card 82 also provide support for connection of a high-speed digital interface to a connector 90 for transmitting data between the first display card 81 and the second display card 82 thereby controlling the dynamic load balancing, the advanced rendering, and synthesis between the first display card 81 and the second display card 82.
However, the north bridge chipset 70 provides two PCI-E X 16 sockets to allow two display cards to be inserted. Hence, it causes a heavy workload for the north bridge chipset 70.
An object of the present invention is to overcome or alleviate at least some
of the problems of the prior art.
In one aspect a method for displaying a multi-display card, comprises: (a) inserting a first display card into a first socket, wherein the first socket is controlled through a first chipset; (b) inserting a second display card into a second socket, wherein the second socket is controlled through a second chipset; (c) connecting the first display card with the second display card through a connector; and (d) outputting a video signal; wherein the first display card and the second display card arc controlled separately through the first chipset and the second chipset for handling image processing, and the first display card and the second display card are co-operated through the connector to output a video signal.
In another aspect a display apparatus for a multi-display card, comprises: a first chipset with at least a first socket; a second chipset with at least a second socket; a first display card inserted into the first socket; a second display card inserted into the second socket; and a connector connected between the first display card and the second display card for transmitting data between the first display card and the second display card; wherein the first display card and the second display card are controlled separately through the first chipset and the second chipset for handling image processing, and the first display card and the second display card are co-operated through the connector to output a video signal.
A preferred embodiment of the invention is described below by way of example only with reference to Figures 1 and 2 of the accompanying drawings, wherein: Fig. 1 is a system architecture according to the prior art; and Fig. 2 is a system architecture according to a preferred embodiment of the present invention.
Reference is made to Fig. 2, which is a system architecture according to a preferred embodiment of the present invention. The present invention provides a display apparatus for providing support for a SLI (Scalable Link Interface) technology, which comprises a first chipset 10, a second chipset 20, a first display (graphics) card 3 1, a second display (graphics) card 41, and a connector 50.
Furthermore, a first socket 11 and a second socket 21 are supported separately through the first chipset 10 and the second chipset 20, thereby the first chipset 10 is a north bridge chipset and the second chipset 20 is a south bridge chipset. Moreover both the first socket 11 and the second socket 21 are PCI-E (PCI-Express) interfaces according to a preferred embodiment of the present invention.
A first display card 31 is inserted into the first socket 11, a second display card 41 is inserted into the second socket 21, and a connector 50 is connected between the first display card 31 and the second display card 41 for transmitting data between the first display card 31 and the second display card 41.
Furthermore, both of the first display card 31 and the second display card 41 provide support for SLI operations, each of the GPUs of the first display card 31 and the second display card 41 (not shown in figure) provide support for communication protocols. The first display card 31 and the second display card 41 also provide support for high-speed digital interface (not shown in figure) to transmit data.
Moreover, the first display card 31 and the second display card 32 arc controlled separately through the first chipset 10 and the second chipset 20 for handling image processing, and the connector 50 is connected between the first display card 31 and the second display card 41 for transmitting data between the first display card 31 and the second display card 41 to control the dynamic load balancing, the advanced rendering, and synthesis between the first display card 3 1 and the second display card 41.
In addition, when a video signal is outputted through the first display card 3 1, the second display 41 will share the amount of processed data.
As mentioned above, the present invention provides two chipsets with PCIE X 16 sockets for two display cards to be inserted correspondingly. The two chipsets are processed separately to increase the efficiency of the image processing.
Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof

Claims (12)

  1. CLAIMS: I. A method of using multiple display cards, comprising: (a)
    inserting a first display card into a first socket, wherein the first socket is controlled through a first chipset; (b) inserting a second display card into a second socket, wherein the second socket is controlled through a second chipset; (c) connecting the first display card with the second display card through a connector; and (d) outputting a video signal; wherein the first display card and the second display card arc controlled separately through the first chipset and the second chipsct for handling image processing, and the first display card and the second display card are co-operated through the connector to output a video signal.
  2. 2. A method as claimed in claim 1, wherein both the first socket and the second socket are PCI-E (PCI-Express) interfaces.
  3. 3. A method as claimed in claim 1 or claim 2, wherein the specification of the
  4. 4. A method as claimed in any preceding claim, wherein the first chipset is a north bridge chipset and the second chipset is a south bridge chipset.
  5. 5. A method as claimed in any preceding claim, wherein the video information is outputted through the first display card.
  6. 6. A method as claimed in any preceding claim, wherein in step (d) the first display card and the second display card cooperate through the connector which enables their operation loads to be balanced by a driver.
  7. 7. A display apparatus comprising: a first chipset with at least a first socket; a second chipset with at least a second socket; a first display card inserted into the first socket; a second display card inserted into the second socket; and a connector connected between the first display card and the second display card for transmitting data between the first display card and the second display card; wherein the first display card and the second display card are controlled separately through the first chipset and the second chipset for handling image processing, and the first display card and the second display card are co-operated through the connector to output a video signal.
  8. 8. A display apparatus as claimed in claim 7, wherein both the first socket and the second socket are PCI-E (PCI-Express) interfaces.
  9. 9. A display apparatus as claimed in claim 8, wherein the specification of the
  10. 10. A display apparatus as claimed in any of claims 7 to 9, wherein the first chipset is a north bridge chipset and the second chipset is a south bridge chipset.
  11. 11. A display apparatus as claimed in any of claims 7 to 10, wherein the video signal is output through the first display card.
  12. 12. A computer graphics arrangement substantially as described hereinabove with reference to Figure 2 of the accompanying drawings.
GB0508548A 2005-04-27 2005-04-27 Display apparatus and method using multiple graphics cards Active GB2425699B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0508548A GB2425699B (en) 2005-04-27 2005-04-27 Display apparatus and method using multiple graphics cards

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0508548A GB2425699B (en) 2005-04-27 2005-04-27 Display apparatus and method using multiple graphics cards

Publications (3)

Publication Number Publication Date
GB0508548D0 GB0508548D0 (en) 2005-06-01
GB2425699A true GB2425699A (en) 2006-11-01
GB2425699B GB2425699B (en) 2007-04-11

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Application Number Title Priority Date Filing Date
GB0508548A Active GB2425699B (en) 2005-04-27 2005-04-27 Display apparatus and method using multiple graphics cards

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6681270B1 (en) * 1999-12-07 2004-01-20 Texas Instruments Incorporated Effective channel priority processing for transfer controller with hub and ports
US20050088445A1 (en) * 2003-10-22 2005-04-28 Alienware Labs Corporation Motherboard for supporting multiple graphics cards

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6681270B1 (en) * 1999-12-07 2004-01-20 Texas Instruments Incorporated Effective channel priority processing for transfer controller with hub and ports
US20050088445A1 (en) * 2003-10-22 2005-04-28 Alienware Labs Corporation Motherboard for supporting multiple graphics cards

Also Published As

Publication number Publication date
GB0508548D0 (en) 2005-06-01
GB2425699B (en) 2007-04-11

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