GB2420056A

GB2420056A - RFID device

Info

Publication number: GB2420056A
Application number: GB0520675A
Authority: GB
Inventors: Joakim Baengs
Original assignee: Innovision Research and Technology PLC
Current assignee: Broadcom Innovision Ltd
Priority date: 2004-10-11
Filing date: 2005-10-11
Publication date: 2006-05-10
Also published as: WO2006040544A1; GB0422552D0; GB0520675D0

Abstract

An RFID device for communicating wirelessly with another RFID device, comprising: a radio frequency antenna; an RFID processor for processing data, the processor being arranged for communicating with one or more addressable units, by writing data to an addressable unit and/or for reading data from an addressable unit, in which said one or more addressable units comprise an input/output unit in communication with the radio frequency antenna, the input/output unit being adapted for encoding data for transmission by the radio frequency antenna and/or decoding data received by the radio frequency antenna. The invention may be embodied as an RFID transponder, RFID transceiver or NFC device, and also relates to an electronics device comprising such an RFID device.

Description

1 2420056

RFID DEVICE

Field

This invention relates to a radio frequency identification device (RFID device), and electronics devices such as vending machines, mobile telephones, personal digital assistants or computers comprising such an RFID device.

Background

RFID devices have been known for some time. In this context, RFID devices are generally capable of the transmission of data by a radio frequency antenna, either by the transmission of an internally generated radio frequency signal or by load

modulation of an incoming radio frequency field.

For example, WO 02/093881 describes the use of various RFID devices and US 6,650,870 describes the use of RFID devices within games apparatus. Such RFID devices use either state machines (in which the logic functions are dispersed around the RFID device) or programmable microcontrollers, for example reduced instruction set computers (RISC) processors or complex instruction set computers (CISC) processors (where set logic functions are centralized). Such processors and state machines tend to take up substantial silicon area and in addition limit the flexibility of the end RFID device design. Although such processors may be programmable, as with RISC processors, the functionality of such processors and therefore silicon area utilized by such processors is set at the start of the design. This is particularly problematic where design flexibility is required to cater for a wide variety of end RFID device functionality or alternatively flexibility is required with low silicon area.

Summary

A first aspect of the present invention provides an RFID device for communicating wirelessly with another RFID device, comprising: a radio frequency antenna; and an RFID processor for processing data, the processor being arranged for communicating with one or more addressable units, by writing data to an addressable unit and/or for reading data from an addressable unit, wherein said one or more addressable units comprise an input/output unit in communication with the radio frequency antenna, the input/output unit being adapted for encoding data for transmission by the radio frequency antenna and/or decoding data received by the radio frequency antenna.

The invention in this aspect provides an entirely new design architecture for RFID devices, allowing the design of RFID devices having a reduced silicon area and increased design flexibility over the RFID devices of the prior art.

The processor may comprise a single instruction computer, preferably a conditional move processor (CMP) or a subtract and branch if negative (SBN) processor.

The input/output unit may be arranged to turn the processor on in response to a first predetermined event. This allows the processor to only use energy when it is needed, therefore reducing the energy consumption of the processor.

The first predetermined event may comprise the detection of an electromagnetic signal of a predetermined intensity at the radio frequency antenna.

The first predetermined event may comprise the detection of a modulation in an electromagnetic signal at the radio frequency antenna.

The first predetermined event may comprise the elapse of a predetermined amount of time.

The processor may be arranged to turn off in response to a second predetermined event.

The second predetermined event may comprise the elapse of a predetermined amount of time.

The second predetermined event may comprise the detection of a drop in intensity of an electromagnetic signal received by the radio frequency antenna.

The one or more addressable units may comprise an arithmetic unit.

The one or more addressable units may comprise data storage means.

The data storage means may comprise a non-volatile memory.

The data storage means may comprise EEPROM.

The data storage means may comprise a register. The register may be present in addition to any non-volatile memory, EEPROM memory or program memory.

The register may comprise at least one flip flop.

These different types of addressable units allow the functionality of the RFID device to be increased in a flexible manner, if extra functionality is needed.

The RFID device may comprise a program memory.

The program memory may comprise a mask-programmed ROM.

The processor may communicate with the data storage means via a first bus and the program memory via a second bus.

This allows the program memory to be responsive to a different edge of the clock cycle to the, or each, other addressable unit, thereby allowing the operation of the RFID to speed up without increasing the integrated circuit area.

The RFID device may comprise a transponder.

The RFID device may comprise a transceiver.

The RFID device may comprise an NFC device.

A second aspect of the present invention provides an RFID device for communicating wirelessly with another RF1D device, comprising: a radio frequency antenna; an RFID processor for processing data; and an input/output unit in communication with the radio frequency antenna, the input/output unit being adapted for encoding data for transmission by the radio frequency antenna andlor decoding data received by the radio frequency antenna wherein the input/output unit is arranged to turn the processor on in response to a first predetermined event.

A third aspect of the present invention provides an RFID device for communicating wirelessly with another RFID device, comprising: a radio frequency antenna; and an RFID processor for processing data, wherein said RFID processor is a single instruction computer.

The invention further relates to electronics devices comprising an RFID device as described above.

Further aspects, features and advantages will become apparent from the following description of preferred embodiments of the invention, given by example only, which refers to the accompanying drawings.

Brief Description of the Drawings

Figure 1 shows an RFID processor according to a first embodiment of the present invention; Figure 2 shows an RFID processor according to a second embodiment of the present invention; Figure 3 shows an RFID processor according to a third embodiment of the present invention; Figure 4 is a flow diagram showing the operation of the RFID processor according to the third embodiment present invention; Figure 5 shows an RFID processor, program memory and associated addressable units according to an embodiment of the present invention; Figure 6 is a timing diagram; Figure 7 shows a program counter according to an embodiment of the present invention; Figure 8 shows an address unit according to an embodiment of the present invention; Figure 9 shows a control unit according to an embodiment of the present invention; Figure 10 shows a control bit according to an embodiment of the present invention; Figure 11 shows an arithmetic addressable unit according to an embodiment of the present invention; Figure 12 shows an JIO unit according to an embodiment of the present invention; Figure 13 shows an RFID device according to an embodiment of the present invention; and Figure 14 shows an RFID device according to a further embodiment of the present invention.

Detailed Description

Figure 1 shows one embodiment of an RFID device of the present invention.

The RFID device 200 may be any device comprising RFID functionality. The RFID device 200 may be stand-alone or comprised within a larger device or system, for example a mobile telephone, a personal digital assistant, a printer, a personal computer, a vending machine or a games console. The RFID device may be an RFID transponder (for example a passive or active transponder or tag), an RFJD transceiver (for example an RFID reader) or a near-field communication device (NFC device) ,for example an RFID device comprising both transponder and transceiver functionality.

Such an RFID device 200 may communicate in accordance with various communication protocols such as those specified by international standard ISO/IEC 14443, ISO/JEC 15693, ISO/IEC 18092 and ISO/IEC 21481. In all cases such RFID devices communicate through the modulation of a radio frequency (RF) signal. The RF signal being modulated may be generated by a second device or generated by the RFID device carrying out the modulation. Modulation may, for example, be via phase modulation, frequency modulation, amplitude modulation or load modulation.

The RFID device 200 may have a power denver (not shown), so that it may derive its power supply from a received RF signal or RF field. Alternatively, the RFID device may contain its own power source, for example a battery or fuel cell or may share a power source with a larger device or system.

In its simplest form (and therefore smallest form) the RFID device 200 comprises an RFID processor 201, an 110 unit 206, a memory 202 and an analogue interface 203 connected to an antenna 204. The RF[D processor 201, the memory 202 and the 1/0 unit are connected by a bus 205. In the example shown in Figure 1 the memory 202 represents both a program memory and a data memory. The data and program memories could be formed as one unit, could be formed as two units having one address on the bus 205, or could be formed as two separate units having different addresses, but being addressable via the same bus (in which case Figure 1 should be taken to show the memory schematically). In embodiments of the present invention the program memory may be mask-programmed ROM and the data memory may be a non-volatile memory, such as EEPROM. Alternatively, both may be non-volatile.

Operation of the RFID device 200 is controlled via the RFID processor 201 which preferably comprises a single instruction computer (SIC) and more preferably a conditional move processor (CMP) or a subtract and branch if negative (SBN) processor. The RFID processor 201 controls the operation of the RFID device through the movement of data between the 110 unit 206 and the memory 202 via the bus 205. Movement of data by the RF1D processor is through the use of one instruction, for example "MOVE" where the RFTD processor comprises a CMP. The analogue interface 203 may comprise one or more of: a power denver, an RF signal generator, a modulator, a demodulator and converts received analogue signals into their digital equivalents. Such digital signals are sent to the 110 unit 206 via a data link 211. Receipt of the digital signal by the 110 unit will result in at least one data transfer between the I/O unit and the RFID processor 201 and/or the memory 202.

The amount of processing (for example decoding of the digital signal) carried out by the 110 unit will depend on the type of 110 unit. For example the I/O unit may detect changes in the digital signal level received. Those changes will result in a bit-level change in the 110 unit which can then be detected by the RFID processor which then carries out decoding of the received digital signal. In another example the 110 unit may carry out some decoding of the received digital signal and the resulting data is then detected by the RFID processor.

Where required the RFID processor 201 also controls modulation of RF signals via the 110 unit 206 and the analogue interface 203.

The antenna 204 is shown as a coil in Figure 1 but may alternatively comprise

an E-field antenna such as, for example, a dipole.

The bus 205 comprises an address bus, a data bus and control signals. The memory 202 and 110 unit 206 are both addressable units connected to the bus 205. As shown in Figure 1 the RFID device 200 may comprise additional addressable units, for example, extra registers 207 and arithmetic units 208 andlor other addressable units. The registers 207 may include additional data storage, for example temporary memory storage. In embodiments of the present invention the registers may comprise at least one flip flop, and may further comprise an address decoder. The number and nature of the addressable units comprised within an RFID device 200 will depend on the functionality required by the RFID device 200. Therefore, by using the RFID processor according to embodiments of the present invention, increased design flexibility can be obtained. For example, where the RFID device 200 is a simple RFID transponder which responds to receipt of an RF field by modulating that incoming RF field in accordance with data in the memory 202, no additional addressable units will be required. However, where, for example, the RFID device 200 is a reader and is therefore required to carry out collision detection or a series of arithmetic functions, then a series of addressable units such as those shown in Figure 1 may be required. Another example may be where the RFID device comprises part of a larger device or system, in which case the interface with the larger device or system may comprise an addressable unit connected to a bus 205.

Included within the logic within the RFID processor 201 is a program counter, which is updated during execution of a current instruction to point to the memory address where the next instruction resides. The RFJD processor 201 carries out repeated versions of the same instruction and in each case data may be fetched from one or more of the addressable units (shown as 202, 206, 207 and 208 in Figure 1), operated upon according to the single instruction, and the resultant data is stored according to the instruction performance. Example outcomes following performance of the single instruction include movement of data, arithmetic operations upon data, and changing the content of the program counter for program jumps (or branching).

The RFID device 200 uses the computer architecture known as von Neumann architecture, where the program memory is contained within the memory used for storing data 202 and only a single bus 205 is used.

Figure 2 shows a further embodiment of an RFID device 300 in accordance with an embodiment of the invention. As with the RFID device 200 the RFID device 300 may be any device comprising RFID functionality, for example an RFID transponder, an RFID transceiver or an NFC-device. The RFID device 300 uses the computer architecture known as Harvard architecture, where the program memory 309 is separate and has its own bus 310. All items with numerical references 301 to 308 have been incremented by 100 from the equivalent items in Figure 1 and each item has similar functionality to those shown in Figure 1. As with Figure 1, the number of arithmetic units, registers and other addressable units will depend on the functionality required in the device. The RFID processor 301, which preferably comprises a single instruction computer (SIC) and more preferably a conditional move processor (CMP) or a subtract and branch if negative (SBN) processor, is operable to control the additional bus 310 connected to the separate program memory 309. The data memory 302 in this case is used to store data and not to store program instructions. In Figure 2 the RFID processor 301 controls operation of the RFID device 300 through the movement of both program instructions from the program memory 309 via the bus 310 and through the movement of data to and from the bus 305 and in and out of the various addressable units 302, 306, 307 and 308.

Figure 3 shows a further embodiment of an RFID device 400. As with the RFID devices 200 and 300, the RFTD device 400 may be any device comprising RFID functionality, for example an RFID transponder, an RFID transceiver or an NFC- device. An analogue interface 403 comprises the same elements as the analogue interface 203 in Figure 1. The analogue interface 403 and an antenna 404 have similar or equivalent function to the analogue interface 203 and the antenna 204 in Figure 1. The equivalent to the bus 305 of Figure 2 comprises, in this embodiment, signal bus groups: a data bus 405, an address bus 412, and a control bus 411. The RFID device 400 in this example comprises an RFID processor 401, an 110 unit 406, a data memory 402, registers 407 and an arithmetic unit 408. However, the number and type of addressable units attached to these signal bus groups will depend on the functionality required in the RFID device 400. The RFID processor 401 is operable to control the buses 411 and 405 (control bus and data bus respectively). The RFID processor is also operable to control a separate program memory 409, through a bus 410, and receives data from the program memory 409 through an instructionladdress bus 413. The RFID processor is also connected to the instructionladdress bus 412, which is also connected to the addressable units. In this example, the RFID processor 401 is a CMP and is operable to permit moving of data only when certain conditions are met.

When the RF1D processor (201, 301 or 401 in Figures 1, 2 and 3) comprises a CMP, it only moves data from a source to a destination. For example, data is moved from the I/O unit 406 to the data bus 405 and then to a data memory 402.

For an RFID processor in accordance with embodiments of the invention there is no need for an instruction format; for example, for a CMP the instructions can simply be the source address and the destination address. To reduce execution time, in a preferred embodiment such a CMP is equipped with an additional address mode (referred to below as "immediate operand") and an additional decision mechanism (referred to below as "conditional move"). The address modes available in the source part of the instruction are immediate operandl data and direct addresses. The address mode for the destination is preferably a direct address; the destination instruction provides for whether the move is unconditional or conditional.

In one example, the instruction format can be illustrated as "Sbbbbbbbb" and "Daaaaaaaa". S and D refer to source and destination instruction bits. The "b's" and "a's" refer to source data/address and destination address bits respectively. Where S=1, the operand is immediate and the "b's" will designate a number. Otherwise the "b's" will designate an address in an addressable unit. The instruction will be a conditional move where D=1. If the condition is not fulfilled (for example, if the msb of the previously moved data = 0) the source data will not be moved to the address designated by the "a's". If the condition is fulfilled or if the operand is not conditional then the source data will be moved to the address designated by the "a's".

In either case, the msb of the source data is held within the RFID processor 401.

In Figure 3, the most significant bit (msb) input via the bus 413 characterizes the operation of the RFID processor. The msb of the source instruction (S) above determines whether the operand is immediate or not and the msb of the destination instruction (D) determines whether the data move is or is not conditional. The least significant byte (LSB) input via the bus 412, comprising the least significant eight bits (aaaaaaaa and bbbbbbbb above), is used either as an address for all addressable units (internal and external to the RFID processor 401) or as the actual number (data) to be moved. The instruction/address buses 412 and 413 therefore have a dual function: carrying both the instruction to be executed in the form of the "msb"s and data andlor addresses in the form of the LSBs.

The embodiment shown in Figure 3 has the advantages of a pipelined method without the use of an instruction pipeline and also has the additional advantage that no time is wasted for jumps/branches; no time is wasted fetching instructions and jumps/branches occur immediately without time wastage due to pipeline flushing. An additional advantage of the embodiment shown in Figure 3 is that register usage for temporary storage is significantly reduced thereby facilitating minimum use of integrated circuit area.

Figure 4 is a flow diagram showing the conditional variations of the move instruction carried out within the RFID processor 401 of Figure 3, in the case where such RFID processor comprises a CMP. As stated above, the move instruction moves data from a source to a destination. Each move instruction comprises two adjacent memory locations within the program memory 409 of Figure 3. Each of these memory locations comprises nine bits where the most significant bit (msb) of each location signifies a variation to the move instruction. The flow diagram of Figure 4 shows the logical steps that can occur within the RFJD processor 401.

Referring to Figure 4, the move instruction starts at step S501. At step S502 source information is read out from program memory 409 and consists of nine bits; a most significant bit (msb) and a least significant byte (LSB). At step S503 the value of the source msb is checked by the RFID processor 401, and if it is equal to I step S504 is carried-out, otherwise step 505 is carried-out. At step 504 the source LSB is used as the actual data to be moved to the destination, and is output to the data bus 405. However, if step 505 is carried out instead of step 504, then the source LSB is used to address an addressable unit, and the content of the addressed location is output to the data bus 405. After step S504 or step S505, at step S506 the data bus 405 contains data due to be moved to the destination. At step S507, the destination information is read out from the next program memory location and again consists of nine bits; a most significant bit (msb) and a least significant byte (LSB).

At step S508 the value of the source msb is checked, and if it is equal to 1 step S511 is carried out, otherwise step 509 is carried out. If step S5 11 is carried-out, then if the msb of the data byte moved in the previous move instruction was equal to 1, step S509 is carried out, otherwise the move instruction is not carried out and the data is not moved to the destination. If step 509 is carried out, the LSB output from program memory 409 is used as the address of the destination, then at step S510 the move instruction is carried out; the data on the data bus 405 (step S506) is moved to the address pointed to by the address bus 412 (step S509).

An example of the "move" instruction with an RFID processor can be represented in machine language as two 9-bit words as follows, where the first bit (msb) is shown as a 0 or I and the last 8-bits (LSB) are shown as a variable: {0, As) (0, At) where As is the source address and At is the target address (the execution of this move instruction example is represented in Figure 4 by a path through the flow diagram of steps S501-503 and then S505-510, where S509 is reached directly from S508); or {1, Ns}{0, At) where Ns is an actual number to be moved and At is the target address (the execution of this move instruction example is similarly represented in Figure 4 but where the path goes by step S504 instead of S505).

The "0" in the second bracket (destination) in each case indicates that there is no condition i.e. there is no need to check the msb of any previously moved byte. By changing this to a 1, the RFID processor is instructed to check the msb of the previously moved byte (step 511 of Figure 4) i.e. the move becomes conditional.

Whether the move is actually carried out will then depend on the msb of the previously moved byte.

The "0" or "1" in the first bracket (source) in each case indicates whether the LSB is an address of a number, or an actual number, to be moved i.e. where 1 indicates an immediate operand (step S504 in Figure 4).

Persons skilled in the art will realise that alternative CMP architectures are possible that use more or less data bits. Persons skilled in the art will also realise that alternative CMP architectures are possible that use more control bits and these extra control bits (in addition to program memory msb described herein) may then be used to control additional functions and/or additional conditions. In addition, persons skilled in the art will realise that the order within program memory of the control and data bits is immaterial and may be altered from that described herein.

Figure 5 illustrates an embodiment of the RF1D processor, program memory and associated addressable units in accordance with an embodiment of the invention.

The RFID processor 401, which in this example is a CMP, contains a control unit (CU) 701, a program counter (PC) 702, an address unit (AU) 703 and a control bit (CB) 704. The addressable units 705 will include data memory units and 110 units operable to control the RFID functionality and may comprise additional addressable units such as registers and arithmetic units. Each such addressable unit is connected to the various buses and signals (708 - 712) in the same way.

The addressable units and blocks within the RFID processor 401 are responsive to positive-going edges of the master clock and have a clockinput symbol shown as a small triangle 706. However, the program memory 409 is different and outputs data following negative-going edges of the master clock and is indicated by the small circle (referenced 707) adjacent to the clock-input symbol.

In Figure 5 the data bus 708 is the same as the data bus 405 in Figure 3. The address bus 709 is the same as the instruction/address bus consisting of412 and 413 in Figure 3. The signals write/not_read (WRNIRD) 710, enable (EN) 711, and reset 712 together form the control bus 411 in Figure 3. The program memory address bus (shown in Figure 3 and labeled 410) is shown in Figure 5 as connecting the least significant bit (lsb) to the signal write/not_read (which acts to point at the source and destination words of the move instructions), and the remaining bits being connected to the count output bus from the program counter.

The WRNRD signal is also used to signify the data bus 708 direction; if WR_NRD = 0 before a positive clock edge then the following clock cycle signifies data moved from (or read from) an addressable unit, and conversely if WR_NIRD = I before a positive clock edge then the following clock cycle signifies data moved to (or written to) an addressable unit.

The reset-in 713 signal is synchronized to a clock positive edge by the control unit 701. The synchronized signal is output from the control unit as the reset signal 712, which resets the RFID processor and the addressable units. The signal reset-in 713 may be derived from an RFID device power-on reset circuit.

The master enable signal 714 may be used by the addressable units or by a larger system to halt RFID processor operations. If master enable is low, the RF!D processor halts at its present state (and resumes operations when master enable returns to the high logic level).

The program counter (PC) 702 points to the current operation in the program memory. The PC is addressed (can be read or written to) like any other addressable unit and this feature is used for program jumps (branching) and subroutine jumps.

Where no jump is required, the PC is incremented by one to point to the next sequential instruction.

Figure 7 shows an example of the PC 702 of Figure 5. The PC comprises a decoder 751, a multiplexer (MTJX) 752, a counter register 753, an add one function 754, a backup register 755, a flip-flop 757 and a tri-state buffer 756. Data from the data bus 708, the decoder 751 and the add one function 754 are input into the multiplexer 752. The count output 750 is connected to the program memory and forms the most significant eight bits of the program memory address. The following table shows the PC address map with example addresses (alternative addresses could be used). The R/W column shows data moves to the PC as a write, and data moves from the PC as a read.

Program counter address map ADDRESS R/W ACTION OOh Write Data bus is loaded into counter register (use for program _________ ________ JUMP) OOh Read Content of backup register is output to data bus (use: save __________ return address) Olh Write Data bus is loaded into counter register and nextcount 758 __________ is saved into the backup register Olh Read Same as a read from OOh Additional addresses may be allocated. The program counter range may be expanded by allowing a separate write cycle to preload a "higher bits" register from which the PC will parallelload along with information on the data bus when the lower 8 bits (a short jump/branch) are addressed.

Referring again to Figure 5, the address unit (AU) 703 stores direct data and controls the memory enable signal 711. The AU decodes the instruction control bit (the address-mode/conditional-move bit which is the msb of instruction word) output from the program memory 409, the bus transfer phase (WR_NRD) output from the control unit 701, and the condition bit to set the data bus enable (EN) high or low output from the control bit 704. During the load/read bus transfer phase, if an immediate operand is implied by the instruction control bit, the operand is read from the instruction word into the AU register and put on the data bus 708 (EN is decoded low to prevent other units from interpreting the instruction word as an address and attempt to write to the data bus too). During the store/write phase EN is high when the instruction control bit indicates a normal move but is low if the condition bit is not set during a conditional move.

Figure 8 shows an example of the AU 703 of Figure 5. The AU comprises a decoder 801, a data register 802, a flip-flop 803 and a tn-state buffer 804. The condition signal 805 is received from the control bit 704 as shown in Figure 5. The bus labeled "instruction" 709 is so-labeled because the function of the address unit is to use the dual-function bus 709 (Figure 5) to respond to instruction variations where such variations are determined by the current instruction msb and also the msb of the previously moved data (the condition signal). The enable signal 711, which is output from the address unit, is described in more detail in relation to Figure 6. The following table shows the address unit truth table.

Address unit truth table

INPUTS ______ _____ OUTPUTS

Reset WR/NRD Instr: b8 Cond EN Action on CLK +ve edge 1 X X X 0 Buffer -)highZ 0 0 0 X 1 Buffer -)highZ 0 0 1 X 0 Load register and Buffer -)On 0 1 0 0 1 Buffer -)highZ 0 1 0 1 1 Buffer -)highZ 0 1 1 0 0 Buffer -)high Z 0 1 1 1 1 Buffer -)high Z Referring again to Figure 5, the control unit (CU) 701 controls the reset and WR_NRD signals. Figure 9 shows an example of the CU 701 of Figure 5. The CU comprises a flip-flop 901 and a flipflop 902.

Referring again to Figure 5, the control bit (CB) 704 stores the most significant bit (msb) of the previously moved data to facilitate a conditional move.

The conditional move is made if the msb indicated a negative 8-bit number (i.e. the msb was set high). The condition is not satisfied and the conditional move is not made if the msb indicated a positive number (i.e. the msb was set low). The CB output bit is used by the address unit to determine if a conditional move is to be executed or not. Using the control bit 704 in this way enables the RF1D processor architecture to be kept as small as possible. The control bit 704 may be separate or built into the address unit 703. Increased flexibility in terms of external addressable unit control of conditional moves can be maintained by keeping the control bit 704 separate from the address unit 703.

Figure 10 shows an example of the CB 703 of Figure 5, comprising a flipflop 1001. The input signal 1002 is connected to the msb of the data bus 708 (shown in Figure 5). The output signal 805 is connected to the condition input of the address unit (shown in Figure 5). A transfer may be made conditional in various alternative ways; for example, an external addressable unit could act as a mask where different carry flags from previous addressable unit calculations, moves and operations can be selected depending on the condition required.

Referring again to Figure 5, persons skilled in the art will realise that blocks or parts of blocks generating control signals may or may not be combined in other functional blocks within the RFID processor 401.

The way in which addressable units 705 are addressed and utilized by the RFID processor will be exactly the same for any additional addressable units that may be included within the RFID device or larger system. The essence of the interaction between the RFID processor and addressable units is that data is moved from (read from) or moved to (written to) each addressable unit.

Figure 6 is a timing diagram showing example data flows from a source to a destination during move instructions carried-out by the RFID processor 401 of FigureS. The signals and signal buses numbered 706 and 708 to 713 have been initially shown in Figure 5. The program memory address 410 is shown in Figure 3.

The signal CB-output 805 is shown in Figure 10. Each move instruction starts two clock cycles from the last move instruction, whether the program counter 702 is reloaded for a jump/branch or whether the program counter is incremented by one to follow the previous instruction. The instruction/address bus 709 operates as described for the instruction/address bus 412 in Figure 3.

Enable (EN) 711, when at a logic high state (at a 1 level), enables addressable units to store data from, or to output data to, the data bus 708.

On the negative clock, referenced 601 in Figure 6, the first source (address or number) is put on the address/instruction bus 709 (indicated as FROM). At this stage (the read cycle), EN is controlled by the msb of the source instruction. If the msb of the source instruction is low it means that the rest of the word is the source address; in this case EN goes high (at reference point 603) and a read from the instruction LSB (operand) address is made possible. Conversely, if msb is high it means that the rest of the instruction word is the operand (i.e. the number to be moved); in this case EN will be low at reference point 603 and no addressable units are allowed to output onto the data bus. This means that at a reference point 604 on the next positive clock edge, source data, whether from an addressable unit or whether the source number (from the address unit 703 in Figure 5), is output onto the data bus 708.

On the following negative clock edge 605, the destination address (indicated as TO) is put on the address/instruction bus. A write to that address is completed at the following positive clock edge 606 if EN is high, and EN is high during the write phase if either one of two conditions are fulfilled. The first condition is when the msb of the instruction word is low (this is shown as the sequence of steps S508, S509 and S5 10 in Figure 4). The second condition is if the msb of the instruction word is high and the msb of the last moved byte (stored in control bit and shown as CB-output in the timing diagram) is high, signifying that the last moved byte was a negative signed number or an unsigned number greater than 127 (this is shown as the sequence of steps S508, S51 1, S509 and S510 in Figure 4). This second condition is the only means of decision making that the RFID processor has itself.

As an alternative to the two-cycle transfer (shown in Figure 6), one full move of data from one address to another could be achieved in one clock cycle. This can be achieved using either a dual port RAM structure with dual address and decode or a dual edge operation RAM and logic blocks. However, these alternatives will increase RAM size, which will increase the overall integrated circuit size and will therefore increase cost.

In microprocessor architectures, it is common to use pipelining to ensure that data memory reads and writes occur in alternate clock cycles. The timing diagram of Figure 6 shows that by making the program memory (instruction and address) read half a cycle ahead of data, the need for pipelining is removed; which means that integrated circuit area is saved because registers are not required to store pipelined data.

As stated above, one of the advantages of the present invention is that the architecture allows for flexibility through the selection of addressable units. Example addressable units might include: adder units, subtractor units, rotator units and increment and shift units.

In one preferred embodiment the RFID processor may be arranged to address an arithmetic unit in addition to, for example, a memory unit and an 110 unit.

Figure 11 shows one example of an arithmetic addressable unit 1100. The arithmetic addressable unit comprises a first register "register 1" 1101 an 8-bit register, a second register "register 2" 1102 an 8-bit register, a first multiplexer 1103, a second multiplexer 1104, a decoder 1105 into which the address bus 708 and the EN and WR_NRD control signals are input, a third multiplexer 1106 the output of which is input into the first and second multiplexers 1103 and 1104, an OR logic block 1107, an AND logic block 1108, an exclusive-OR (XOR) logic block 1109, a reduction-OR logic block 1110, an ADD logic block 1111, a fourth multiplexer 1112 into which the outputs of the logic blocks 1107 to 1111 and the decoder 1105 are input, a flip- flop 1114 into which the output of the decoder 1105 is input, and a tn- state buffer 1113 into which the outputs of the fourth multiplexer and the flip-flop 1114 are input. The output of the tn-state buffer 1113 is output onto the data bus 708.

The OR logic block performs a bit-wise logical OR operation on the outputs of the first and second registers 1101 and 1102. Similarly, the AND, XOR and ADD logic blocks perform such bit-wise operations. The reduction-OR logic block 1110 outputs a single bit by performing a logical OR operation on all 8-bits from the XOR logic block 1109. The decoder 1105 decodes the address bus, and the EN and WR_NRD control signals to determine which, if any, read or write operations are to be carried out (such operations are described in the table below).

The first and second registers 1101 and 1102 are used to perform arithmetic operations; data is moved into one or both of the registers and then one or more arithmetic operation results can be moved out of the arithmetic unit 1100. Data is put into either the first or second register 1101 or 1102 from the data bus when the RFID processor moves data to specific addresses. Examples of these specific addresses are shown in the address map below. The R/W column shows data moves to the arithmetic unit registers as "write", and data moves from the arithmetic unit tn-state buffer as "read".

Address map _________ __________________________________________________

ADDRESS RJW ACTION

04h Write Register 1 (Reg 1 or Ri) is set to Data 05h Write Register 2 (Reg 2 or R2) is set to Data 06h Write Register 1 is set to Data and Register 2 is set to Olh 07h Write Register 2 is set to Data and Register 1 is set to Olh 08h Write Register 1 is set to Data and Register 2 is set to 80h 09h Write Register 2 is set to Data and Register 1 is set to 80h OAh Write Register 1 is set to Data and Register 2 is set to FFh OBh Write Register 2 is set to Data and Register I is set to FFh OCh Write Register I is set to Data and Register 2 is set to Carry ODh Write Register 2 is set to Data and Register 1 is set to Carry OEh Write Register 1 is set to Data and Register 2 is set to OOh OFh Write Register 2 is set to Data and Register 1 is set to OOh 04h Read Reads the result Regi OR Reg2 05h Read I Reads the result Regi AND Reg2 06h Read Reads the result Regi XOR Reg2 07h Read Reads the result Reduction OR (Regi XOR Reg2) 08h Read Reads the result ROL (Regi) 09h Read Reads the result ROR (Regi) OAh Read Reads the result RCL (Regi) OBh Read Reads the result RCR (Regi) OCh Read Reads the result Regi + Reg2 ODh Read Reads the carry of Regi + Reg2 OEh Read Not used in this example: Future functions could be shift ___________ _________ in one from left (SOL) and shift in one from right (SOR) OFh Read Not used in this example: Future functions could be shift __________ ________ in one from left (SOL) and shift in one from right (SOR) When data is put into the first register 1101, for example, the second register 1102 may be automatically loaded with specific data, and this is determined by the address specified by the RED processor; examples of these addresses together with descriptions of the data that will be loaded into the other register, are shown in the address map above. When such register loading is completed, the RFID processor may read from (carry out a move from) one of the addresses shown on the address map and the corresponding logical or arithmetic operation will be output onto the data bus 708. The RFID processor may continue to read from different addresses from the address map to obtain different logical or arithmetic operations performed on the content of the two registers.

For example, where the REID processor wishes to write data to the first register 1101 within the arithmetic unit 1100, the destination address bits may specify address 04. The relevant data will then be moved into the first register 1101 within the arithmetic unit. Alternatively, where, for example, the REID processor wishes to read a bit-wise logical AND of the data contained within the first and second registers 1101 and 1102 of the arithmetic unit, the source address bits will specify, for example, 05 and the data resulting from the logic AND operation will be read out of the arithmetic unit.

With regard to the specific addresses shown in the address map, persons skilled in the art will realise that these addresses are examples and that alternative addresses may be used. Persons skilled in the art will realise that if desirable, for example to save integrated circuit area, some of the arithmetic logic could be omitted.

Similarly, persons skilled in the art will know that if desirable, additional arithmetic functions can be added, such as a multiplier, for example.

In all cases, the RFID processor will be operable to communicate with an I/O unit or multiple 110 units comprising the digital RFID functionality.

Figure 12 shows one example of an 110 addressable unit 1200 comprising the RFID functionality of an RFID device according to embodiments of the present invention, such as the RFID device 400 shown in Figure 3. In every case the I/O unit 1200 will be arranged to receive digital signals from the analogue interface 403, to decode such received signals and to output encoded digital signals to the analogue interface 403.

In a preferred embodiment and as shown in Figure 12 the 110 unit 1200 can be used to control operation of the RFID processor 401 and prevent the need for the RFID processor to continuously poll. This control is carried out by a sleep/wake-up process and the advantages of using such a process include power saving and reducing the necessary RFID processor program length. For example, the processor 401 could be switched on or off in response to a predetermined event. A detailed discussion of this is given below.

In the example shown in Figure 12 the I/O unit 1200 is an 8-bit programmable reset/alarm timer and encoder. The 110 unit 1200 is constructed specifically so that, in conjunction with an RFID processor, RFID signals are decoded and RFID signals are encoded according to one or more protocols, such as international standard ISO/IEC 14443, ISO/IEC 15693, ISO/IEC 18092 and ISO/IEC 21481. The RFID processor moves data into registers within the 110 unit in order to set-up the 110 unit according to the required protocol. Persons skilled in the art will realise that the 110 unit 1200 may be adapted to decode and/or encode signals conforming to alternative protocols.

The 1/0 unit 1200 and an associated RFID processor together decode incoming RFID signals one bit at a time and together encode RFID signals one bit at a time. This decoding and encoding will often require the use of a timer contained within the 110 unit. A time out event (TOE) occurs when the timer reaches a predetermined time. Where incoming RFID signals have an appropriate logic level transition, this transition is detected as a modulation event (MOE). A TOE and/or a MOE may be used to reset the timer as part of the decoding or encoding process.

In addition, and also as part of the decoding or encoding process, a TOE and/or a MOE may be used to wake up the RFID processor from being in sleep mode.

When the REID processor receives the wake-up signal it is re-enabled and continues its program sequence (having previously halted itself by putting itself into sleep mode). This sleep/wake process may be used by the RFID processor to avoid polling.

The wake-up signal to the RFID processor occurs when the 110 unit 1200 sets the signal MASTER_ENABLE 714 to a high logic level. The RF1D processor may set itself to sleep mode by setting a particular bit in one of the 110 unit's set-up registers (which is explained in more detail below).

A TOE and/or a MOE may additionally be used within the 1/0 unit during the decode process to stop further incoming RFID signal logic level transitions causing a MOE for a predetermined time period. This process of stopping MOEs for a period is controlled by the RFID processor during the protocol setup process andlor during the decode process, and is used to reduce the likelihood that undesirable incoming RFID signal transitions (glitches) will cause incorrect decoding. This process is referred to as controlled gating, and is explained in more detail below.

The 110 unit 1200 receives incoming RFID signals GAP iN 1201 and/or MOD IN 1202 from the analogue interface (not shown). Such signals will be dependent on receipt of an externally generated modulated RF signal by the signal receiving means (for example at the antenna coil 404 (from Figure 3)) and conversion of such an analogue signal to a digital signal by the analogue interface (for example the analogue interface 403 shown in Figure 3). This digital signal is then decoded and set as a received data bit (RX).

Conversely, where the RFID device comprising the I/O unit 1200 responds to an external device or supplies a modulated RF signal to an external RFID device, a data bit for transmission (TX) is set and encoded and supplied to the analogue interface (for example 403 in Figure 3) via the digital signal MOD OUT 1203. The analogue interface will convert such a signal into a modulated analogue signal which will then be transmitted via, for example, the antenna coil 404 shown in Figure 3.

The 110 unit 1200 has a number of set-up and control registers that are used to set-up the required protocol, load cyclic redundancy check (CRC) data, and to set the data bit value to be encoded. In this example these registers comprise a decoder setup register (DSR) 1204, a time out register (TOR) 1205, a master enable and synchronisation register (MSR) 2106, an encoder set-up register (ESR) 1207, registers within a CRC generator 1217, and transmit-bit registers within an encoder 1215. The number of registers and the data stored therein will depend on the functionality of the unit.

Data is moved between the I/O unit and other addressable units by the RFID processor along the data bus 708. This data bus corresponds with the data bus 708 of Figure 5. Where the data is moved to in the 110 unit will depend on the source and destination addresses and the control signals utilized by the RFID processor (not shown). The address bus 709, the enable signal 711, the WR_NRD signal 710 and the reset signal 712 correspond to the similarly labeled signals of Figure 5 and are input into a decoder 1218 in the I/O unit. The RFID thus controls the movement of data into the set-up and control registers by controlling the inputs into the decoder 1218.

The RFID processor also controls the movement of data out of the 110 unit using the address bus 709, the enable signal 711, the WR_NRD signal 710 and the reset signal 712 input into the decoder 1218. The outputs from the decoder 1218, the CRC generator 1217, the decode block 1208 and the timer/encoder block 1213 are input into a multiplexer 1219. The output of the multiplexer is input into a tn-state buffer 1220. An output of the decoder 1218 is input into a flip-flop 1221, and the output of the flipflop 1221 is also input into the tn-state buffer 1120. The tn-state buffer outputs data onto the data bus 708. The decoder effectively selects an input of the multiplexer 1219 to be output onto the data bus 708 depending on the address input into the decoder 1218.

The following table provides examples of addresses which might be used and the result of the data move. It will be apparent to the skilled man that different addresses or move instructions may be used to control the operation of the 1/0 unit 1200. The RIW column in the table indicates whether the RFID processor is moving data into the 110 unit, represented as "write", or moving data from the I/O unit, represented as "read".

I Address map _______________________________________________ ADDRESS I R/W ACTION I Oh Write TOR set (loads data into the time out register) 1 lh Write MSR set (loads data into the master enable and ___________ synchronisation register) 12h Write DSR set (loads data into the decode setup register) 1 3h Write ESR set (loads data into the encoder setup register) 14h Write TX bit set (sets bit level to be encoded at timer reset) 1 5h Write TX bit set with CRC & parity update (sets bit level to be encoded at timer reset, where CRC and parity are also desired). Setting this bit can also be used as part of the _________ decode process as described for the DSR below.

1 6h Write CRC_LOW set (loads data into the least significant byte of ___________ _________ the CRC generator) 17h Write CRC_HIGH set (loads data into the most significant byte __________ _________ of the CRC generator) lOh Read TOS Bit read (Time out status bit = logic high for detected _________ _______ TOE) 1 lh Read Timer value at time of read 12h Read Not used (Returns 0) 1 3h Read Not used (Returns 0) 14h Read RX Bit = read receive bit logic level. (The logic level of the MOD IN 1202 signal that has been sampled and/or ___________ _________ manipulated according to values set in DSR).

1 5h Read Read parity bit logic level. (Parity starting state, I for odd ____________ __________ or 0 for positive, is set in DSR).

16h Read Read CRC_LOW (least significant byte of CRC ____________ __________ generator 1217) I 7h Read Read CRC_HIGH (most significant byte of CRC ____________ ___________ generator 1217) Where single bit values are read or written, in this example, the bit will be the most significant bit (msb) and the seven least significant bits are not used and will be at a zero. Such single bit writes are shown above at addresses I 4h and 1 5h. Such single bit reads are shown above from addresses lOh, 14h and 15h.

The DSR, TOR, MSR, and ESR (1204 to 1207 respectively) are described in more detail below. The CRC generator 1217 may be used during the decoding and/or encoding process. Serial data paths to and from the CRC generator (not shown) provide encoded or decoded data.

When a digital signal GAP IN 1201 or MOD IN 1202 is received from the analogue interface it is decoded by a decode block 1208. Elements within the decode block 1208 are used during the process to decode incoming RFID signals according to the RFID protocol. The RFID processor, when settingup the I/O unit 1200 according to the required RFID protocol, will select which of the two incoming RFID signals GAP IN 1201 or MOD IN 1202 to respond to. This selection is done by setting the value of bit 4 in the DSR. If the GAP IN signal is to be used then the protocol is such that decoding is carried out by making use of the timer functionality 1214 within the timer/encoder block 1213 with reference to the times between when GAP IN transitions from a low to a high logic level (when GAP IN goes high a MOE occurs via the gated event detect and wake up control block 1210). If the MOD [N signal is to be used then the protocol is such that decoding may be carried out by making use of the timer functionality and/or the level of the MOD IN signal after it has been manipulated according to the values set in the DSR 1204 (the manipulated signal level is read from the 110 unit as shown in the address map table above). Where MOD IN is used for the decoding, each signal level transition (from high to low, or from low to high) is detected in the mod event detect block 1209 and used to give a MOE (via the gated event detect and wake up control block 1210), and hence time intervals between MOEs may be used for the decoding process.

The 110 unit 1200 also comprises a timer/encoder block 1213, the timing function of which is used for determining TOEs. The timer/encoder block 1213 also sets the master enable signal 714, output to the RFID processor, and encodes signals to be sent to the analogue interface. The timer/encoder block 1213 comprises a timer 1214, an encoder 1215 and restart/gate/wakeup logic 1216. After the timer is reset it starts incrementing its value, synchronised to the system master clock. When the value of the timer reaches the same number as that set in the TOR 1205 a TOE occurs. The timer may be reset by a TOE and/or a MOE according to the setup of the MSR. The setup of the MSR 1206 also controls whether a MOE andlor a TOE cause the RFID processor to wake up (from a sleep state) by setting the MASTER ENABLE signal 713 to a high logic level. The restart/gate/wakeup logic 1216 is used to control the timer 1214 and encoder 1215.

A TX bit set (set by the RFID processor by writing to address l4h or 15h as described above) is used by the encoder 1215 to encode the TX bit according to the RFID protocol chosen by setting values in the ESR 1207. A timer TOE may be used during the encode process to wake up the RFID processor, thereby facilitating the RFID processor to load the next TX bit that is required to be sent. The encoding possibilities such as the use of one or more subcarriers are further described below

during the description of the ESR 1207.

According to the particular RFID protocol being used, the decoder block 1208 and the timer/encoder block 1213 will be used as described, together with the RFID processor, to decode incoming RFID data (from GAP IN 1201 or MOD IN 1202) or to encode RFID data to be transmitted (from MOD OUT 1203). The uses of the decoder block 1208 and the timer/encoder block 1213 are further clarified during the descriptions of the DSR 1204, the TOR 1205, the MSR 1206 and the ESR 1207 below.

The following table shows what effect individual bits in the DSR 1204 have on the operation of the decoder block 1208.

DSR (Decoder setup register)

Bit Name Description

7 Manchester Bit value to XOR or XNOR manipulate the logic level of the Code Polarity sampled signal MOD IN 1202. XORIXNOR selected by _______________ bit 5. This bit resets to 0.

6 Parity Set 0 = Even number of ones.

1 = Odd number of ones.

The value is XOR:ed with each update bit and will change for every transmittedlreceived logical one (provided it's been _____________ written to the TX & CRC address 15h).

MSAMPLE Manchester polarity sample manipulation: 0= XOR (Sampled MOD IN 1202 is XOR:ed with bit 7).

- ____________ I = XNOR (Sampled MOD IN 1202 is XNOR:ed with bit 7).

4 MOD_NGAP Selects gap or modulation event detection mode and input: 0 = Gap input and sign sensitive MOE mode selected (MOE occurs when GAP iN 1201 goes high) 1 = Modulation input and sign insensitive MOE mode _____________ selected (MOE occurs when MOD iN 1202 changes level) 3:0 GLOW (Gate Sets number of clock cycles following a TOE or MOE LockOut controlled gate reset during which MOE gating is suspended Word) (length of deglitching period). The clock edge marking the end of the gate lockout also triggers the modulation input sample. If enabled in the MSR, a TOE andlor MOE stops further input signal transitions causing another MOE for up ______________ to 15 clock cycles.

The following table shows what effect individual bits in the ESR 1207 have on the operation of the encoder 1215. The ESR controls bitwise encoding format and modulation output status (on or off). If subcarrier A or subcarrier B are selected then encoding is done according to the formula NOT(SubA''(TX bit level) + SubB), where the TX bit level is set by the RFID processor writing to address I 4h or 1 5h.

ESR (Encoder setup register)Bit Name Description

7 TX Enable 0 Off. MOD OUT 1203 is set LOW at the next timer restart.

1 = On. MOD OUT 1203 starts output of encoder sequence at _______________ the next timer restart.

6 SubA Invert Subcarrier A invert select: 0 = Subcarrier A is not inverted.

_____________ 1 = Subcarrier A is inverted.

5:4 SubA[1:0] Subcarrier A Select: 00 = D128 (Divide by 128 - 106kbps) 01 D64 (Divide by 64 - 2 12kbps) = D32 (Divide by 32 - 424kbps) _______________ 11 D16(Dividebyl6-824kbps) 3 SubB Invert Subcarrier B invert select: o = Subcarrier B is not inverted.

_____________ 1 = Subcarrier B is inverted.

2 SubB Subcarrier B Select: o No Sub Carrier B. ____________ 1 = Sub Carrier B (D16 - Divide by 16- 824kbps).

1 Direct 0 = Encoder Driven Modulation Modulation I = MOD OUT 1203 is what each TX bit has been set to Select 0 _____________ Not used The following table shows what effect individual bits in the MSR 1206 have on the operation of the timer and encoder 1213 and decoder block 1208. The MSR enables or disables the effect that a MOE andlor a TOE has on: controlled gating of MOEs, wakeup (sets master enable 714) and timer restart.

MSR (Master enable and synch register)

Bit Name Description

7 SLEEP 0 = master enable 714 goes HIGH (resets to this state) 1 = master enable 714 goes LOW.

Resets to 0 (master enable goes HIGH) by MOE andlor TOE if _____________ bits 5 and 1 are appropriately set.

6 MOC GATE Modulation event controlled gating: 0 = MOE controlled gating disabled.

1 = MOE controlled gating enabled.

A gated MOE suspends gating of subsequent MOEs for the number of clock cycles set in the gate lock out word (GLOW) ______________ in DSR (this is to filter out transition glitches).

MOC_UP Modulation event controlled wake-up: 0 = MOE controlled wake up is disabled.

1 = MOE controlled wake up is enabled.

____________ A gated MOE resets bit 7 (Master Enable 713 goes HIGH) 4 MOCR Modulation event controlled timer restart: 0 = MOE controlled timer Restart is disabled.

1 = MOE controlled timer Restart is enabled.

_____________ A gated MOE restarts the timer.

3 TOS Reset Time out status reset: 0 = TOS bit remains unchanged.

____________ 1 = TOS bit is reset.

2 TOC_GATE Time out event controlled gating: 0 = TOE controlled gating disabled.

1 = TOE controlled gating enabled.

A TOE suspends gating of subsequent MOEs for the number of clock cycles set in the gate lock out word (GLOW) in DSR (this ______________ is to filter out transition glitches).

I TOC_UP Time out event controlled wake-up: o = TOE controlled wake up is disabled.

1 = TOE controlled wake up is enabled.

TOE resets bit 7 (master enable 713 goes HIGH). If TOE is cause for or happened in the same clock cycle as a gated MOE ____________ wake up signal was detected the TOS bit is set HIGH.

0 TOCR Time out event controlled timer restart: o = TOE controlled timer restart is disabled.

I = TOE controlled timer restart is enabled.

_____________ A TOE restarts the timer As discussed briefly above, the processor can be arranged to turn on or off in response to a predetermined event, in order to conserve power. First, the case where the processor is off is considered. In this case bit 7 of the MSR is set high, meaning that master enable is low. When a predetermined "turn on" event occurs the 110 unit re-sets bit 7 of the MSR; the bit re-sets to a low value, which causes the master enable to be set high. As discussed above, this causes the processor to turn on.

When a predetermined "turn off' event occurs the processor sets bit 7 in the MSR to a high value. This means that master enable output by the I/O unit is set low, thereby turning the processor off.

For example, the processor could be turned on when the intensity of the received signal increases above a certain threshold level (for example, one which is strong enough to allow data to be extracted therefrom), or when the analogue interface detects that the received signal is modulated, or when a predetermined amount of time has elapsed. Furthermore, the processor can turn off when, for example, the intensity of the received signal on the antenna drops, or when a predetermined amount of time has elapsed. The relevant "turn off' event, for example elapsed time or reduced intensity, would be detected by the processor based on the input received by the 110 unit. The processor would then effectively turn itself off by setting bit 7 in the MSR to a high value as discussed above.

The TOR 1205 contains the 8-bit value at which a TOE occurs. The TOR output is fed to the timer and encoder block 1213 and is compared to the value of the timer 1214 output, and when the timer output is equal to the TOR output a TOE occurs. A TOE may cause one or more of three things to occur (timer restart, wakeup, MOE gating suspension) and these are enabled or disabled from occurring when the RFID processor sets the values of bits 0 to 3 in the MSR. In addition a TOE sets the timeout status bit (TOS) to a high logic level.

In the examples described herein the master enable 714 signal is used as part of the sleep/wake-up interaction between the RFID processor and the I/O unit.

However, the master enable signal could alternatively be used with an RFID processor, which is responsive to the master enable signal as an interrupt signal. The adapted RFID processor may for example, use such an interrupt signal when it has completed a current move instruction, to start an interrupt routine.

Figure 13 shows an example of an RFID device 1500 in accordance with a further embodiment of the invention. The RFID device 1500 is in this example an RFID transponder or an RFID tag. In this example the RFID tag 1500 is a passive tag, capable of deriving its power supply from a received RF field. The RFID tag will respond to receipt of an RF field by deriving power from the received RF signal and once sufficient power has been derived by load modulating the incoming RF field in accordance with data stored in the memory 1505. Load modulation in this example occurs through modulation of the impedance of the signal reception circuitry 1506 and 1512.

An externally generated magnetic field (for example from an RFID transceiver or NFC device) induces an AC voltage across the signal reception circuitry, which comprises a capacitor 1512 and an anteima 1506 formed as a coil inductor. The induced voltage is fed to power deriving means 1502, which in this example comprises a diode 1508, an energy storage capacitor 1509, and an over-voltage protection means 1510. The over-voltage protection means 1510 operates to stop voltages on either positive or negative half-cycles of the induced AC voltage from rising to a level where damage could occur to any part of the RFID tag 1500. The output of the power deriving means 1502 feeds a DC supply voltage to all circuitry within the RFID tag 1500 requiring a supply voltage.

The analogue interface in this case comprises two parts: a demodulator analogue interface 1501 and a modulator analogue interface 1515. The 1/0 unit 1513 sends a modulation signal 1511 to a transistor 1503 (comprising the modulator analogue interface 1515). The modulation signal 1511 consists of binary data to be sent according to predetermined patterns relating to a 1' or a 0'. The content of the signal 1511 is controlled by the RFID processor 1504 according to one or more of: a control sequence arranged to operate within the RFID processor 1504; data contained within an electrically erasable programmable read only memory (EEPROM) 1505; and data received by the RFID tag 1500 as modulation to the RF signal and demodulated by tag demodulator 1501. Control by the RFID processor 1504 is as described above and is based on the moving of data between the various registers within the 110 unit 1513 and the memory 1505. Data is moved to and from the data bus 1514 which corresponds with the bus 205 in Figure 1. A single bus is used to transfer data, control signals and address signals. As shown in Figures 2 and 3 multiple buses and separate program memory may be utilised as an alternative.

The modulation signal 1511 is fed to the transistor 1503, which has a known on-resistance, and so when the modulation signal switches-on the transistor 1503, an impedance is switched on across the signal reception circuitry 1506 and 1512. The impedance change caused by the transistor 1503 switching on is coupled to the external RFID device emitting the RF signal, since the impedance change causes a signal variation that is demodulated by a demodulator within the external RFID device.

In this example the RFID processor may be any single instruction computer, for example a conditional move processor.

Figure 14 shows a further example of an RFID device in accordance with an embodiment of the invention. In this case the RFID device 1600 is an RFID reader which generates an RF field at signal circuitry 1607 (referred to below as a carrier signal). The field may be modulated in accordance with data held by memory 1663.

The RFID reader 1600 will await a response from any external RFID device within range, for example a second RFID reader, an NFC device or an RFID tag, and will be able to respond to the external RFID device. The response may be via load modulation of the carrier signal generated by the RFID device 1600, by interference with the carrier signal, or alternatively, by receipt of an independently generated RF

field independent of the carrier signal.

The RFID device 1600 comprises an analogue interface 1665 (comprising an RF signal generator 1657, a differential driver 1658 and a demodulator 1662), signal circuitry 1607, an RFID processor 1616 and a series of addressable units including an unit 1664, a memory 1663 and an arithmetic unit 1668. The arithmetic unit may, for example, be required for collision detection and collision avoidance by the RFTD device in accordance with established RFID protocols.

An RFID processor 1616 controls operation of the RFID device 1600 through the moving of data along a bus 1666 between the addressable units shown 1664, 1663 and 1668. The bus 1666 is shown as a signal bus and therefore carrying data, control and instruction/address signals. The bus may be split into constituent signals and a separate program memory may be used as shown, for example, in Figures 2 and 3. In this example the RFTD processor may be any single instruction computer for example a conditional move processor.

The RF signal generation means 1657, in this example, generates an RF carrier signal at for example 13.56MHz. An I/O unit 1664 (under control of the RFID processor 1616) provides modulation control signals 1659 to the differential driver means 1658. These signals are represented as including, for example, MOD OUT signal 1203 in Figure 12. The nature of the MOD OUT signal will be determined in accordance with the set-up of the encoder setup register, the master enable and synch register and the time out register (1207, 1206 and 1205 respectively in Figure 12) as controlled by the RFID processor 1616 by moving data into the registers.

incoming RF signals or modulated carrier signals are received at the antenna 1607 and demodulated by the demodulator 1662 before being passed to the I/O unit 1664. The resulting modulation status will be used by the I/O unit 1664 and processed in accordance with instructions received from the RFID processor 1616.

The received signal from the analogue interface 1665 may, for example, be represented as the GAP IN and/or MOD IN signals in Figure 12 (1201 and 1202).

The received modulation signal will be used in accordance with the set-up of one or more of the decoder setup register, the master enable and the synch register and time out register (1204, 1206 and 1205 respectively in Figure 12) as controlled by the RFID processor 1616 by moving data into the registers. The modulation control signals 1659 (including for example MOD OUT 1203 in Figure 12) control, in this example, the amplitude of the RF carrier signal that the differential driver means provides to the antenna circuitry. The differential driver means 1658 outputs complimentary pulses using techniques known to persons skilled in the art.

The antenna circuitry consisting of capacitors 1601, 1602, 1650 and 1651 and a coil 1607 form a tuned circuit and function to reduce unwanted carrier harmonics.

However, the main function of the coil 1607 is to act as an antetma to emit the modulated RF carrier signal. The RFID processor 1616 will typically use modulation control signals 1659 sent to the differential driver means 1658 to alter the signal level, the modulation depth, relating to binary data desired to be sent according to predetermined patterns relating to a 1' or a 0'. Where an un-modulated RF carrier signal is desired, the modulation control signals 1659 control the differential driver means 1658 to output a full amplitude RF carrier signal. An unmodulated carrier signal is usually used when an external RFID tag, or an NFC device in tag-mode, is signalling back to the RFID reader. An unmodulated carrier signal may additionally be desired where an external RF1D tag for example does not expect to receive data, but simply uses the RF carrier signal, for example, to derive power and/or to signal back to the RFID reader.

The capacitors 1655 and 1656 limit the amplitude of the signal input to the demodulator 1662 so as to avoid over-volt damage to the demodulator. The demodulator 1662 is used to demodulate signals from an external device within range, such as an RFID tag for example, where modulated signals are coupled to the antenna 1607. The demodulator 1662 outputs demodulated signals in binary form to unit 1664.

In this example the RF signal generation means 1657 is constructed to generate the RF signal by sine synthesis. The RF signal generation means 1657 provides a pulse-width modulated (PWM) or a pulse-density modulated (PDM) digital signal to the differential driver means 1658. The PWM or PDM signal is generated from a code stored on a read only memory (ROM). The ROM data is fed to a shift register (SR), the output of which forms the PWM or PDM serial data stream. The ROM code is generated by a sine synthesis technique known to persons skilled in the art. Persons skilled in the art will realise that the sine synthesis PWM or PDM code could be generated by alternative means such as a processor means running a preconfigured algorithm or other techniques such as direct digital synthesis. Persons skilled in the art will realise that signals for any of the above-mentioned sine synthesis methods could be generated from within the RFID processor 1616 itself. The PWM or PDM data stream controls the differential driver means 1658 such that complimentary pulses are output in the most advantageous way to minimize unwanted RF signal frequencies being emitted. System configurations and requirements may obviate the need for the capacitors 1650 and 1651 where the nature of the signals from the differential driver means 1658 maintains the avoidance of infringing emissions regulations. If the sine synthesis technique were not used, then to conform to emissions regulations, additional filtering circuitry would be required, for example additional inductors and capacitors at the signal nodes 1652 and 1653.

As alternatives to the RFID devices described in Figures 13 and 14, the RFID device may be an NFC device. Such devices comprise the ability to communicate reader to reader' or NFC device to NFC device. Depending on the way in which the NFC device is designed the NFC device may act as an RFID reader similar to that described for Figure 14 above or as an RFID tag similar to that described for Figure 13 above. As such, the NFC device may communicate with other NFC devices, RFID readers or RFID tags. The RFID devices described above in Figures 13 and 14 are near-field RFID systems operable at ranges up to, for example, 1 metre. Such devices rely on communication using the H-field around the antenna or signal circuitry. RFID devices may also operate at further distances and in such instances utilise the E-field. Examples of such devices can be found in the electronic product code (EPC) global standard. The frequency of operation of such far-field device tends to be higher, for example 2.4 GHz and communication of data may be via modulation of the RF signal generated or via frequency hopping techniques or a combination of both. The RFID processor in accordance with this invention can be utilised equally in a far-field RFID device as in the near field devices described for Figures 13 and 14 above.

The above embodiments are to be understood as illustrative examples of the invention. Further embodiments of the invention are envisaged. It is to be understood that any feature described in relation to any one embodiment may be used alone, or in combination with other features described, and may also be used in combination with one or more features of any other of the embodiments, or any combination of any other of the embodiments. Furthermore, equivalents and modifications not described above may also be employed without departing from the scope of the invention, which is defined in the accompanying claims.

Claims

Claims 1. An RFID device for communicating wirelessly with another RFID

device, comprising: a radio frequency antenna; and an RFID processor for processing data, the processor being arranged for communicating with one or more addressable units, by writing data to an addressable unit andlor for reading data from an addressable unit, wherein said one or more addressable units comprise an input/output unit in communication with the radio frequency antenna, the input/output unit being adapted for encoding data for transmission by the radio frequency antenna and/or decoding data received by the radio frequency antenna.
2. An RFID device according to claim 1, wherein the processor comprises a single instruction computer.
3. An RFID device as claimed in claim 2, wherein the single instruction computer comprises a conditional move processor.
4. An RFID device as claimed in claim 2, wherein the single instruction computer comprises a subtract and branch if negative processor.
5. An RFID device as claimed in any preceding claim, wherein the input/output unit is arranged to turn the processor on in response to a first predetermined event.
6. An RFID device as claimed in claim 5, wherein the first predetermined event comprises the detection of an electromagnetic signal of a predetermined intensity at the radio frequency antenna.
7. An RFID device as claimed in claim 5 or 6, wherein the first predetermined event comprises the detection of a modulation in an electromagnetic signal incident on the transceiver.
8. An RFID device as claimed in any of claims 5 to 7, wherein the first predetermined event comprises the elapse of a predetermined amount of time.
9. An RFID device as claimed in any preceding claim, wherein the processor is arranged to turn off when a second predetermined event is detected.
10. An RFID device as claimed in claim 9, wherein the second predetermined event comprises the elapse of a predetermined amount of time.
II. An RFID device as claimed in claim 9 or 10, wherein the second predetermined event comprises the detection of a drop in intensity of an electromagnetic signal received by the radio frequency antenna.
12. An RFID device as claimed in any preceding claim, wherein said one or more addressable units comprise an arithmetic unit.
13. An RFID device as claimed in claim 12, wherein said one or more addressable units comprise data storage means.
14. An RFID device as claimed in claim 13, wherein said data storage means comprises a non-volatile memory.
15. An RFID device as claimed in claim 14, wherein said data storage means comprises EEPROM.
16. An RFID device as claimed in claim 13, wherein said data storage means comprises a register.
17. An RFID device as claimed in claim 16, wherein said register comprises at least one flip flop.
18. An RFID device as claimed in any preceding claim, wherein said RFID device comprises a program memory.
19. An RFID device as claimed in claim 18, wherein said program memory comprises mask-programmed RUM.
20. An RF[D device as claimed in any preceding claim, wherein the RFID device comprises an RFID transponder.
21. An RFID device as claimed in any preceding claim, wherein the RFID device comprises an RFID transceiver.
22. An RFID device as claimed in any preceding claim, wherein the RFID device comprises an NFC device.
23. An RFID device for communicating wirelessly with another RFID device, comprising: a radio frequency antenna; an RFID processor for processing data; and an input/output unit in communication with the radio frequency antenna, the input/output unit being adapted for encoding data for transmission by the radio frequency antenna and/or decoding data received by the radio frequency antenna, wherein the input/output unit is arranged to turn the RFID processor on in response to a first predetermined event.
24. An RFID device for communicating wirelessly with another RFJD device, comprising: a radio frequency antenna; and an RFJD processor for processing data, wherein said RFID processor is a single instruction computer.
25. An electronics device comprising an RFID device according to any preceding claim.
26. An electronics device according to claim 25, wherein the electronics device comprises a vending machine, mobile telephone, personal digital assistant or computer.