GB2416416B - Multi-node computer system implementing global access state dependent transactions - Google Patents
Multi-node computer system implementing global access state dependent transactionsInfo
- Publication number
- GB2416416B GB2416416B GB0521527A GB0521527A GB2416416B GB 2416416 B GB2416416 B GB 2416416B GB 0521527 A GB0521527 A GB 0521527A GB 0521527 A GB0521527 A GB 0521527A GB 2416416 B GB2416416 B GB 2416416B
- Authority
- GB
- United Kingdom
- Prior art keywords
- computer system
- system implementing
- access state
- node computer
- global access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000001419 dependent effect Effects 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US46203003P | 2003-04-11 | 2003-04-11 | |
PCT/US2004/011098 WO2004093408A2 (en) | 2003-04-11 | 2004-04-09 | Multi-node computer system implementing global access state dependent transactions |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0521527D0 GB0521527D0 (en) | 2005-11-30 |
GB2416416A GB2416416A (en) | 2006-01-25 |
GB2416416B true GB2416416B (en) | 2006-11-22 |
Family
ID=33299894
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0521527A Expired - Lifetime GB2416416B (en) | 2003-04-11 | 2004-04-09 | Multi-node computer system implementing global access state dependent transactions |
Country Status (3)
Country | Link |
---|---|
US (1) | US7606978B2 (en) |
GB (1) | GB2416416B (en) |
WO (1) | WO2004093408A2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8185602B2 (en) | 2002-11-05 | 2012-05-22 | Newisys, Inc. | Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters |
US7539190B2 (en) * | 2004-01-05 | 2009-05-26 | Topside Research, Llc | Multicasting in a shared address space |
US7957474B2 (en) | 2006-01-26 | 2011-06-07 | Texas Instruments Incorporated | Robust detection of packet types |
US7941560B1 (en) | 2006-07-14 | 2011-05-10 | Intuit Inc. | Client caching of target addresses for network requests |
US9288163B2 (en) * | 2013-03-15 | 2016-03-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Low-latency packet receive method for networking devices |
JP6142783B2 (en) * | 2013-11-25 | 2017-06-07 | 富士通株式会社 | Memory controller, information processing apparatus, and memory controller control method |
US20160188468A1 (en) * | 2014-12-26 | 2016-06-30 | Intel Corporation | Implementation of data coherence among devices |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0817073A2 (en) * | 1996-07-01 | 1998-01-07 | Sun Microsystems, Inc. | A multiprocessing system configured to perform efficient write operations |
US5926829A (en) * | 1995-12-22 | 1999-07-20 | Sun Microsystems, Inc. | Hybrid NUMA COMA caching system and methods for selecting between the caching modes |
US20020087778A1 (en) * | 2000-12-29 | 2002-07-04 | Schoinas Ioannis T. | Storing directory information for non uniform memory architecture systems using processor cache |
US20020124144A1 (en) * | 2000-06-10 | 2002-09-05 | Kourosh Gharachorloo | Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector |
EP1255201A1 (en) * | 2001-05-01 | 2002-11-06 | Sun Microsystems, Inc. | Shared memory multiprocessing system employing mixed broadcast snooping and directory based coherency protocols |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5297269A (en) * | 1990-04-26 | 1994-03-22 | Digital Equipment Company | Cache coherency protocol for multi processor computer system |
US5434993A (en) | 1992-11-09 | 1995-07-18 | Sun Microsystems, Inc. | Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories |
US5394555A (en) | 1992-12-23 | 1995-02-28 | Bull Hn Information Systems Inc. | Multi-node cluster computer system incorporating an external coherency unit at each node to insure integrity of information stored in a shared, distributed memory |
US6088768A (en) | 1993-12-28 | 2000-07-11 | International Business Machines Corporation | Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication |
JPH08278916A (en) | 1994-11-30 | 1996-10-22 | Hitachi Ltd | Multichannel memory system, transfer information synchronizing method, and signal transfer circuit |
US5978874A (en) * | 1996-07-01 | 1999-11-02 | Sun Microsystems, Inc. | Implementing snooping on a split-transaction computer system bus |
US5940860A (en) * | 1996-07-01 | 1999-08-17 | Sun Microsystems, Inc. | Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains |
US5734922A (en) * | 1996-07-01 | 1998-03-31 | Sun Microsystems, Inc. | Multiprocessing system configured to detect and efficiently provide for migratory data access patterns |
US5864671A (en) * | 1996-07-01 | 1999-01-26 | Sun Microsystems, Inc. | Hybrid memory access protocol for servicing memory access request by ascertaining whether the memory block is currently cached in determining which protocols to be used |
US5802582A (en) | 1996-09-10 | 1998-09-01 | International Business Machines Corporation | Explicit coherence using split-phase controls |
US6209064B1 (en) | 1998-01-07 | 2001-03-27 | Fujitsu Limited | Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system |
US7266587B2 (en) * | 2002-05-15 | 2007-09-04 | Broadcom Corporation | System having interfaces, switch, and memory bridge for CC-NUMA operation |
US6944719B2 (en) * | 2002-05-15 | 2005-09-13 | Broadcom Corp. | Scalable cache coherent distributed shared memory processing system |
US7003631B2 (en) * | 2002-05-15 | 2006-02-21 | Broadcom Corporation | System having address-based intranode coherency and data-based internode coherency |
US6970872B1 (en) | 2002-07-23 | 2005-11-29 | Oracle International Corporation | Techniques for reducing latency in a multi-node system when obtaining a resource that does not reside in cache |
-
2004
- 2004-04-09 US US10/821,394 patent/US7606978B2/en active Active
- 2004-04-09 GB GB0521527A patent/GB2416416B/en not_active Expired - Lifetime
- 2004-04-09 WO PCT/US2004/011098 patent/WO2004093408A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5926829A (en) * | 1995-12-22 | 1999-07-20 | Sun Microsystems, Inc. | Hybrid NUMA COMA caching system and methods for selecting between the caching modes |
EP0817073A2 (en) * | 1996-07-01 | 1998-01-07 | Sun Microsystems, Inc. | A multiprocessing system configured to perform efficient write operations |
US20020124144A1 (en) * | 2000-06-10 | 2002-09-05 | Kourosh Gharachorloo | Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector |
US20020087778A1 (en) * | 2000-12-29 | 2002-07-04 | Schoinas Ioannis T. | Storing directory information for non uniform memory architecture systems using processor cache |
EP1255201A1 (en) * | 2001-05-01 | 2002-11-06 | Sun Microsystems, Inc. | Shared memory multiprocessing system employing mixed broadcast snooping and directory based coherency protocols |
Also Published As
Publication number | Publication date |
---|---|
GB2416416A (en) | 2006-01-25 |
WO2004093408A2 (en) | 2004-10-28 |
WO2004093408A3 (en) | 2005-09-22 |
US20040268056A1 (en) | 2004-12-30 |
GB0521527D0 (en) | 2005-11-30 |
US7606978B2 (en) | 2009-10-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
AU2003281389A8 (en) | Multi-processor computer system | |
EP1645069A4 (en) | Trusted computer system | |
GB2377284B (en) | Computer storage systems | |
IL165578A0 (en) | Computer navigation | |
AU2003270317A8 (en) | Prefetching data in computer system | |
GB2415067B (en) | Bus transaction management within data processing systems | |
GB0323695D0 (en) | Computer implemented trading system | |
GB2394100B (en) | Computer system storage | |
GB2402814B (en) | Multi-computer system | |
GB0308102D0 (en) | System for secure transactions | |
GB0317479D0 (en) | 3-Dimensional computer graphics system | |
GB2416416B (en) | Multi-node computer system implementing global access state dependent transactions | |
GB2391335B (en) | Computer system | |
AU2003202151A8 (en) | Input device for computer system | |
FR2799018B1 (en) | SECURE COMPUTER SYSTEM | |
GB2407409B (en) | Computer system having direct media access mode | |
TW577575U (en) | Notebook computer | |
GB2399431B (en) | Computer system | |
GB2399188B (en) | Reducing the boot-up time of a computer system | |
EP1533693A4 (en) | Computer system | |
GB0322798D0 (en) | Railway computer systems | |
PL360129A3 (en) | Computer processor cooling system | |
GB0202970D0 (en) | Computer system | |
PL355117A1 (en) | Computer processor cooling system | |
GB0108221D0 (en) | Computer system for data management |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PE20 | Patent expired after termination of 20 years |
Expiry date: 20240408 |