GB2416236A

GB2416236A - Signal processing circuit

Info

Publication number: GB2416236A
Application number: GB0415735A
Authority: GB
Inventors: Il Song Han
Original assignee: University of Sheffield
Current assignee: University of Sheffield
Priority date: 2004-07-14
Filing date: 2004-07-14
Publication date: 2006-01-18
Anticipated expiration: 2024-07-14
Also published as: WO2006005957A2; WO2006005957A3; GB2416236B; GB0415735D0

Abstract

A signal processing circuit such as an arithmetic circuit for performing arithmetic operations such as multiplication and/or addition/subtraction and a circuit having a voltage-controlled transconductance has a first MOSFET arrangement M1,M2,M3,M4 for performing an arithmetic operation for given first operands VIN, VC and, preferably, at least one other MOSFET M5 for performing substantially the same arithmetic operation for given second operands with the second operands being chosen to influence the output of the first MOSFET circuit by at least reducing, and preferably, eliminating, the presence of an undesirable component of the output of the first MOSFET circuit.

Description

24 1 6236

SIGNAL PROCESSING CIRCUIT

Field of the Invention

The present invention relates to a signal processing circuit and, more particularly, to a VLSI signal processing circuit.

Background to the Invention

The role played by VLSI technology in realising neural networks is well understood by those skilled in the art. Neural networks or, more particularly, neural networks circuits comprise a number of processing elements, connected by weighted synaptic inputs and outputs, to perform particular tasks. A processing element typically comprises a number of multipliers to apply weightings to the synaptic inputs and outputs and a summer for producing a synaptic output from the weighted synaptic inputs.

Those skilled in the art understand that the implementation of a multiplication function performs a pivotal role in the performance of the neural networks. Any such multiplier should preferably be flexible to accommodate various interfaces to existing technologies and algorithms such as, for example, different neural networks paradigms or neural data representations.

Previously three approaches have been taken to addressing these technical problems A first approach was to use conventional digital computer technology in implementing neural networks. This approach has been relatively successful up to a certain level of complexity or for dedicated applications. However, a significant disadvantage of this approach is limited capacity even though an advantage of the first approach is the flexible interface to conventional computer technology. Examples of this approach are, for example, HNC lOONAP, Adaptive solution CNAPS, Intel Nestor NilOOO and IBM ZISC036. A second approach has been to construct dedicated analogue circuits for simulating neural network operations. This approach has the advantage of being able to realise significantly larger neural networks and/or enables flexible sensory interfaces to be implemented. However, it can be difficult to implement such circuits since they require specialised manufacturing technology and it can be difficult to interface such an analogue realisation with conventional computer technologies. An example of this approach can be found in the Intel 801 70N E TANN p roduct. T he t bird approach h as b een t o a ttempt t o c ombine t he advantages of both the analogue and digital approaches. However, one encounters manufacturing technologyissues that are similar to those Uncounted for the second approach.

It is an object of embodiments of the present invention to at least mitigate some of the

problems associated with the prior art.

Summary of Invention

Accordingly, an aspect of embodiments of the present invention provides method of analogue signal processing using non-linear devices operable in respective triode regions (operable with non-linear current-voltage relationship); the method comprising the steps of producing an input current (ITN=IDS+IDs2) using respective currents of a pair of the nonlinear devices, the input current having a linear current voltage characteristic with respect to a selected parameter (VDS) of the pair of non linear devices; the input current comprising a first portion (a(Vc.Vx) ) representing an arithmetic operation between first (Vc) and second voltages (V,N=VX+VTP) applied to first and second terminals associated with the non-linear devices to induce the flow of the respective currents.

A further aspect of embodiments of the present invention provides a signal processing circuit comprising at least a pair of non-linear devices operable together to induce a. ,.

current (IN) varying linearly with respect to the parameter (VDS); wherein respective currents of the pair of non-linear devices vary non- linearly (0(2)) with respect to the parameter (VDS); at least a first device of the pair of non-linear devices comprising a., . r first input terminal for receiving a first input signal to induce the flow of the respective currents. Advantageously, embodiments of the present invention allow mixed analogue and digital signal processing to be realised. A further advantage is that a multiplication function suitable for use in neural networks can be realised that has at least one of the following advantages (a) low power consumption, (b) high-speed operation and (c) supports asynchronous operation.

Embodiments of the present invention use a voltage controlled linearised transconductance or resistance to produce various signal processing elements or computing components. The signal processing elements can comprise, for example, an electronically tuneable filter, a programmable transconductance amplifier, a polyphase filter for communication systems, an analogue decoder or an artificial neural network element.

Embodiments provide a method of analogue signal processing using nonlinear devices operable with non-linear current-voltage relationships with respected to a selected parameter; the method comprising the steps of producing an input current (IIN=IDSI+IDS2) using respective currents of a pair of the non-linear devices, the input current having a linear current-voltage characteristic with respect to the selected parameter (VDS) of the pair of non-linear devices; the input current comprising a first portion (a(Vc.Vx)) representing an arithmetic operation between first (Vc) and second voltages (VIN=VX+VTP) applied to first and second terminals associated with the non-linear devices to induce the flow of the respective currents.

Embodiments of the present invention relate to a signal processing circuit and, more particularly, to an arithmetic circuit for performing arithmetic operations such as, for example, multiplication and/or addition/subtraction operations, as well as to a circuit having a voltagecontrolled transconductance. The circuit comprises a first MOSFET arrangement for performing an arithmetic operation for given first operands and, preferably, at least one other MOSFET for performing substantially the same arithmetic operation for given second operands with the second operands being chosen to the influence the output of the first MOSFET circuit by at least reducing, and preferably, eliminating, the presence of an undesirable component of the output of the first MOSFET circuit.

It can be appreciated that the signal processing elements are realised using a relatively small number of transistors, preferably MOSFET transistors, arranged to compensate for the nonlinearity of MOSFET resistance in the triode region.

The signal processing elements advantageously implement functions that are equivalent to the linear equations for multiplication or summation using a small number o f M OSFET d evices. Furthermore, t he flexibility i n c ircuit c onfigurations accommodates either a pulse-based implementation or an analogue based implementation of electronic synapses that use multiplication or summation.

A still further advantage of embodiments of the present invention is the scalability of the signal processing elements and/or that a low power consumption is achieved for large system integration since only the parts of the signal processing element that are active consume power.

A still further advantage of embodiments of the present invention is that they are operable using a single voltage source a rather than the typical positive and negative voltage sources used in prior art implementations see, for example, UK patent application GB 2 261 093 A, which discloses a MOSFET multiplier using positive and negative, Vx and -Vx, voltage sources.

Brief Description of the Drawings

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings in which: figure 1 shows a first embodiment of a signal processing element; figure 2 illustrates a second embodiment of a signal processing element having an improved offset, that is, improved accuracy; . figure 3 shows a third embodiment of a signal processing element without an offset; . ' figure 4 depicts a fourth embodiment of a signal processing element; and figure 5 illustrates a first embodiment of a signal processing element also having an improved offset. , .,

Detailed Description of Preferred Embodiments

Referring to figure 1, there are shown a MOSFET circuit 100 comprising first M1 and second M2 MOSFETs arranged in parallel. The sources of the first M1 and second M2 MOSFETs are connected to ground. The drains of the first M1 and second M2 MOSFETs are connected to the drain of a third MOSFET M3, the source of which is connected to a first input terminal 102 for receiving a first input signal, VIN. It will be appreciated that the first input signal represents an embodiment of an operand or a signal from which such as operand can be derived.

The sources of the first M1 and the second M2 MOSFETs are connected to the respective substrates of those MOSFETs. Similarly, the source of the third MOSFET M3 is connected to its substrate. It can also be appreciated that the drains of the first M1 to third M3 MOSFETs are connected to the gate of the third MOSFET M3. The gate of the second MOSFET M2 is also connected to the first input terminal 102 for input signal, Via. The gate of the first MOSFET M1 is connected to a second input terminal 104 used to receive an input signal, Vc, which represents a second operand or at least a signal from which a second operand can be derived. Optionally, the signal representing the second operand can be Vc=VcDc+vsg' where VCDC represents the DC component of Vc and vile represents the AC component of Vc.

The gate of the third MOSFET M3 is connected to the gate of a fourth MOSFET M4.

The source of the fourth MOSFET M4 is also connected to the first input terminal 102. The drain of the fourth MOSFET M4 is connected to the drain of a fifth MOSFET M5. The source of the fifth MOSFET M5 is connected to ground.

Therefore, it can be appreciated that the fourth and fifth MOSFETs are connected in series between the first input terminal and ground. It will be appreciated by those skilled in the art that the fourth MOSFET M4 acts as a current mirror to mirror the current flowing through the third MOSFET M3. The fifth MOSFET M5 is used as a I.'' bias to control or at least provide an output current offset. It can be appreciated that ' ' the sources of the fourth and fifth MOSFETs M4 and M5 are connected to their respective substrates. ..

It will be appreciated by those skilled in the art that the first, second and fifth....

MOSFETs M1, M2 and M5 are e-type MOSFETs, that is, nMOSFETs. It will also be. . appreciated that the third and fourth MOSFETs M3 and M4 are p-type MOSFETs, that is, pMOSFETs.

The operation of the basic embodiment of the present invention shown in figure 1 can be described by the following equations. In general, the drain-source current, IDS, for a MOSFET operating in the linear or triode region is given by s IDS = ct[(VGS - VT) VDS - VDS / 2] (1) It will be appreciated by those skilled in the art that or is the MOSFET process parameter, VGS, VDS and VT are the transistor" ale-source voltage, transistor drain- source voltage and the threshold voltage respectively. It will be appreciated by those skilled in the art that the combination of MOSFETS M1 and M2 allow a linear voltage multiplier to be realised. The purpose of the second MOSFET M2 is to remove the second order teen V2DS/2. Therefore, the currents, IDS} and IDS2, flowing through the first and second MOSFETS M1 and M2 are given by IDS! Ct[(VC VT) VDS - VDS I 2] (2) 1 0 IDS2 = CX[(VIN - VT) VDS VDS I 2] ( ) Therefore, the total c urrent, IIN, for the first and s econd M OSFETS M 1 and M2 i S given by IIN = IDS! + IDS2 = cx[(VC - VT) VDS - VDS I 2 + (VIN VT) VDS VDS I] 1 5 = cr[(Vc + VIN 2 VT) VDS VDS] (4) It will be appreciated that the third MOSFET, M3, functions as a diode by dropping the voltage, VIN, presented at the first input terminal 102 by an amount equal to the threshold voltage for the third MOSFET, M3. Therefore, assuming the voltage at the drains of the first and second MOSFETS M1 and M2 to be Vx, that voltage is given by VX=(VIN-VTP), where VTP is the PMOS threshold voltage of the third MOSFET, M3. It willbe appreciatedthatVTp is usually oftheorderof Vet. It will be also appreciated that the current, IM3, of the third MOSFET, M2, is equal to IIN. Therefore, the current through the third MOSFET, M3, is given by IM3 cz[(VC + VIN 2 VT) VDS - VDS] LX[(VC + Vx + VTP 2 VT) VX - VX] [(VC + VTP 2 VT) VX + VX -VX] = X(vc + VTP 2 VT) VX = Ct(Vc + It) Vx Since the fourth MOSFET, M4, acts as a current mirror to mirror the current flowing through the third MOSFET, M3, that is, to mirror IM3, the current in M4 is linearly proportional to both the control voltage, Vc, and the input voltage, VrN' (or VX+VTP), or the multiplied result of Vc and Vx.

Furthermore, by controlling the gate bias voltage, Vb,as, applied to the fifth MOSFET, M5, the offset value, aVOffserVx, of the output current can be controlled, that is, the current flowing through the fifth MOSFET, M5, is subtracted from the current flowing through the fourth MOSFET, M4, to give an output current, I out, as IOUT = IIM3 IBIAS (6) It w ill b e appreciated b y t hose s killed i n the art t hat b oth e xcitation and i nhibition properties of a synaptic current can be realised using the output current, IOUT, that is, addition and/or subtraction can be performed according to the bias voltage applied to the fifth MOSFET, M5. Furthermore, the output current, IOUT, is linearly proportional to Vc or VIN : ' Referring to figure 2, there is shown a second embodiment of a MOSFET circuit 200.

The second MOSFET circuit 200 comprises two circuits 202 and 204. It can be appreciated that the circuits 202 and 204 are substantially similar to the circuit 100 of the first embodiment. However, the biasing for the fifth MOSFET, M5, is derived from the second circuit 204. More particularly, the bias voltage, Vb,as, for the fifth MOSFET, M5, is derived from the voltage at the drains of fourth and fifth MOSFETs, M4A and M5A, of the second circuit 204. It can be appreciated that first and second input terminals 206 and 208 are used to supply operands, VIN and Vc, respectively, to the first MOSFET circuit 202. It can be appreciated that third and fourth input terminals 210 and 212 are used to supply operands, VIN and VCDC, respectively, to the second MOSFET circuit 202.

It will also be appreciated that the second circuit 204 is substantially identical to the first circuit 100 but for the gate of the fifth MOSFET, M5A, being tied to its drain.

Those skilled in the art will appreciate that the current flowing through the fourth MOSFET, M4, of the first circuit 202 will be influenced by the operation of the first, MIA, to fifth, M5A, MOSFETs of the second circuit 204. The arrangement of the fifth MOSFETs, M5 and M5A, in operation, replicates the current flowing through the fourth MOSFET, M4A, of the second circuit 204 to the fifth MOSFET, M5, of the first circuit 202. The current, IBIAS, in the fifth MOSFET, M5, of the first circuit 202 mirrors the currents flowing in any of the fifth, fourth of third MOSFETs, M5A, M4A or M3A, of the second circuit 204. This bias current, IBIAS, is, therefore, given by IBUS IM3A C((VCDC + VTP 2 VT) VX (7), where VCDC is a DC (or offset) component of Vc, that is, Vc=VcDc+vsg. It will be appreciated that the output current, IOUT, from the equations (5), (6) and (7), by IOUT = IIN IRMS = IM -I = oz. (VC + VTP -2 VT) VX a(VCDC + V7p 2 V7- ) Vx = (sin) VX . . = (x(Vsig) (VIN VTP) (8) .: It will be appreciated from an examination of equation (8) that the output current, .' IOUT, it can be thought of as implementing a multiplication function. Furthermore, it ''.

can also be appreciated that the MOSFET circuit 200 shown in figure 2 is operable to provide a voltage-controlled linear transconductance. Still further, assuming that VrN comprises both DC and AC components, VrNDc and v,n, such that the VrN=vrNDc+vn' then the output current, IOUT, can be regarded as a linear calculation.

Figure 3 shows a MOSFET circuit 300 according to a third embodiment. The MOSFET circuit 300 comprises first 302 and second 304 circuits. It will be appreciated that the first circuit 302 is substantially identical to the MOSFET circuit of the second embodiment. The operation of the first circuit 302, therefore, will not be described in detail as its operation can be understood from the description given in relation to the MOSFET circuit 200 of the second embodiment. It will also be appreciated that the second circuit 304 of the third embodiment is substantially similar to the MOSFET circuit 200 described above. However, it should be noted that the configurations of the fifth MOSFETs, M5B and M5C, are different to the configurations of the fifth MOSFETs, M5 and M5A, of the second embodiment of the MOSFET circuit 200. The fifth MOSFET, M5B, of the second circuit 304 is arranged so its gate is coupled to its drain. The other fifth MOSFET, M5C, is arranged so that its gate is coupled to the drain or gate of the fifth MOSFET, M5B. It can be appreciated that an output terminal is provided that is connected to the drains of the fourth MOSFETs M4 and M5C of the first 302 and the second 304 circuits of the third embodiment.

Referring to the first circuit 302 of the third MOSFET circuit 300, it can be seen that a total of four inputs terminals 302a to 304d are provided. The upper circuit 306 of the first circuit 302 comprises two inputs terminals 302a and 302b for receiving operands VIN and Vc. The lower circuit 308 of the first circuit 302 of the third embodiment comprises two inputs terminals 302c and 302d for operands VrN and VCDC. The second circuit 304 comprises two inputs terminals 304a and 304b for operands VINDC and Vc for the upper circuit 310 and two inputs terminals 304c and 304d for operands VINDC and VCDC for the lower circuit 312.

The operation of the MOSFET circuit 300 according to the third embodiments can be described by, and understood from, the following equations.

IOUT = IM3 -IM3A IM3B + IM3C (IM3 IM3A) (IM3B IM3C) = (V51g) (V - VTP) (V51g)(VDC VTP) = (X(Vsig) (Vn) (9) Therefore, the MOSFET circuit 300 according to the third embodiments can be used as a very precise analogue multiplier, where the output is provided as a current, which can be summed by wired- OR connections. Furthermore, when the MOSFET circuit 300 is used as a transconductance amplifier, the transconductance, Gm, is programmable in response to VIN or vie according to the degree of precision required by an application for that amplifier.

It can be appreciated that the above embodiments provide varying levels of arithmetic accuracy and complexity such that an appropriate embodiment can be matched with a corresponding application requiring a respective degree of accuracy.

Using wired-OR logic it is possible to provide functions necessary for a soft- exclusive-OR gate or a large neural network implementation. The soft- exclusive-OR gate, which is a sum-product module, can be described as follows P3( )=P,(0)eP2(0)+P(l)eP2(1) (10) P3(1) =P'(1)eP2(0)+P,(0)eP2(l) where P,(0) and P,(1) are the probabilities of "0" and "1", Pa.) and P2(.) are inputs respectively, as is well understood by those skilled in the art see, for example, "Decoding in Analog VLST', Hans-Andrea Loeliger, Felix Tarkoy, Felix Lustenberger and M arkus H elfenstein, IEEE C ommunications Magazine, April 1 999, pp 9 9-101, which is incorporated herein in its entirety by reference for all purposes. : .'.

Referring to figure 4, there is shown a fourth MOSFET circuit 400, which is a MOSFET resistance based analogue multiplier. The fourth MOSFET circuit 400 comprises a first MOSFET, M1, connected in series with a second MOSFET, MD2.

The drains of the first M 1 and second MD2 MOSFETs are coupled together. The, sources of the first M1 and second MD2 MOSFETs are connected to ground and to an, input terminal 402 respectively. The input terminal 402 is used to supply an operand, VIN, to the circuit. It can be appreciated that the substrates of both MOSFETs M1 and MD2 are coupled to their respective sources. The gate of the second MOSFET, MD2, is connected to its drain. The first MOSFET M1 has its gate connected to a second input terminal 404 for receiving a second operand, Vc.

The fourth MOSFET circuit 400 also comprises a series of arrangement of a retype MOSFET, MD3, and an e-type MOSFET, M2. The drains of these MOSFETs, MD3 and M2, are coupled together. The sources of these two MOSFETs are coupled to the input terminal 402 and ground respectively. It can be appreciated that the substrates of these two MOSFETs are connected to their respective sources. The gate of the third MOSFET, MD3, is connected to the gate of the second MOSFET, MD2. An output terminal 406 is taken from the coupled drains of the third and fourth MOSFETs, MD3 and M2.

The fourth MOSFET circuit 400 further comprises a fifth e-type MOSFET, MR2, arranged in series between the input terminal 402 and ground, with a sixth, e-type, MOSFET, MD4. The substrate of the fifth MOSFET, MR2, is coupled to its source.

The source of the fifth MOSFET and the drain of the sixth the MOSFET are coupled together. The fourth MOSFET, M2, is arranged, or operable, as a current mirror to mirror the current flowing through the sixth MOSFET, MD4. The current flowing through the fifth MOSFET, MR2, is IMR2. It can be appreciated that the gate of the fifth MOSFET, MR2, is coupled to a third input terminal 408 for receiving a respective operand. It can be appreciated that in the embodiment shown the respective operand is VCDC. The current, IMI, of the first MOSFET transistor, M1, and the current, IMR2, of the fourth MOSFET transistor, M2, influence the output current, IOUT, since the third MOSFET, MD3, mirrors the current of the second MOSFET, MD2.' : ' It can be appreciated that the fourth MOSFET circuit 400 comprises three input terminal 402, 404 and 408 for receiving operands Via, Vc and VCDC respectively, that are connected to the sources of MOSFET transistors MD2, MD3 and MR2, and the gates of MOSFET M1 and MOSFET MR2 respectively..

The operation of the fourth embodiment, that is, the fourth MOSFET circuit 400, can..

be explained in terms of the following equations IM! (X[(VC VT) VX -VX /2] (1 1) IMR2 oc[(VCDC VT -VT) VX -VX / 2] (12) IOUT = IM] IMR2 = a[(Vc -VCDC VT) VX] = a(vSg-VT) VX = a(V5ig -VT) (VRV VTP) (13) It can be appreciated that the output current, IOUT, of equation (13) is very similar to the output current defined by equation (5) and can be used for the same purposes or substantially the same purposes.

Similarly, a MOSFET circuit 500 according to a fifth embodiment, as shown in figure 5, operates in a substantially similar manner to the embodiment corresponding to equation (9), that is, to the third embodiment shown in figure 3. It can be appreciated that the current, IM2A, of MOSFET M2RA and the current, IMIA, of MOSFET MIA, produce a similar result to the corresponding currents in equation (9), where VINDC replaces VIN in equations (11) and (12). Therefore, the operation of the MOSFET circuit 500 according to the fifth embodiment can be described by the following equations: IOUT = IMI -IM2 + IM2A IM1A (IM1 IM2) (IMP IM2A) = a(vSg -VT) (VIN -VTP)-a(Vslg VT) (VINDC VTP) ( 6) = a(vSig -VT) (din) It can be appreciated that the expression for the output current, IOUT, of the MOSFET.

circuit 500 according to a fifth embodiment, has the same properties as equation (9) relating to the third embodiment. Therefore, the fifth MOSFET circuit 500 can also.2 be used to implement signal processing functions, neural networks, tuneable filters, polyphase filters, programmable transconductance amplifiers, analogue decoding elements such as, for example, soft gates, etc. It will be appreciated that embodiments of the present invention progressively reduce, and, preferably, remove undesirable currents from the output current until a desired degree of arithmetical accuracy is attained.

Although the above embodiments have been described with reference to nMOS transistors operating in the triode region, embodiments can equally well be realised in which pMOS transistors are arranged to operate in the triode region. In effect, the n- type and p-type transistors in the above-described embodiments are switched for p- type and e-type transistors.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All ofthe features disclosed in this specification (including any accompanying claims, abstract and drawings) and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features: disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method ' or process so disclosed. Be. 1 1 1 8 ..

Claims

1. A method of analogue signal processing using non-linear devices operable in respective triode regions (operable with non-linear currentvoltage relationship); the method comprising the steps of producing an input current (I=IDS+IDs2) using respective currents of a pair of the nonlinear devices, the input current having a linear current-voltage characteristic with respect to a selected parameter (VDS) of the pair of non-linear devices; the input current comprising a first portion (oc(Vc. Vx)) representing an arithmetic operation between first (Vc) and second voltages (VIN=VX+VTP) applied to first and second terminals associated with the non-linear devices to induce the flow of the respective currents.

2. A method as claimed in any preceding claim, in which a gate of a first device of the pair of non-linear devices forms the first terminal; and in which the step of producing the input current comprises the steps of applying the first voltage to the gate of the first device of the pair of non linear devices.

3. A method as claimed in any preceding claim in which a drain of a third device of the non-linear devices forms the second terminal and in which the step of producing the input current comprises the step of applying the second voltage (VIN=VX+VTP) to the drain of the third non-linear device of..

the non-linear devices; the third non-linear device being connected to ground via a parallel combination of the pair of non-linear devices between. . a terminal. ' .

4. A method as claimed in any preceding claim, further comprising the step.

of deriving an output current (IOUT) associated with the input current (IIN) . '

5. A method of analogue signal processing as claimed in claim 4 in which the step of deriving the output current comprises the step of mirroring, using a fourth non-linear device (M4) of the non-linear devices, the input current.

6. A method of analogue signal processing as claimed in any preceding claim further comprising the step of influencing (excitation or inhibition, ie addition/subtraction) the output current using a bias current (IBIAS) of a fifth non-linear device (M5).

7. A method of analogue signal processing as claimed in claim 6 in which the fourth (M4) non-linear device is connected in series with the fifth non linear device between second (YIN) terminal and ground.

8. A method as claimed in either of claims 6 and 7 in which the step of influencing comprises the step of generating the bias current according to a second portion (cc(VOffsevx)) of the input current.

9. A method as claimed in claim 8 in which the step of generating the bias current is such that the bias current (IBIAS) eliminates the second portion ( C(Voffselvx)).

10. A signal processing circuit comprising at least a pair of non-linear devices operable together to induce a current (IIN) varying linearly with respect to the parameter (VDS); wherein respective currents of the pair of non-linear devices vary non-linearly with respect to the parameter (VDS); at least a first device of the pair of non-linear devices comprising a first input terminal for receiving a first input signal.

11. A signal processing circuit as claimed in claim 10 further comprising a.... . third non-linear device (M3) connected in series with a parallel.

arrangement of the pair of non-linear devices between a second input terminal, for receiving a second input signal, and ground.

12. A signal processing circuit as claimed in claim 11 further comprising means for deriving an output current from the induced current; the output.

current representing an arithmetic operation associated with the first and., . second input signals.

13. A signal processing element as claimed in claim 12 in which the means for deriving the output current comprises a further device operable as a current mirror to mirror the induced current in producing the output current.

14. A signal processing element as claimed in any preceding claim further comprising means to influence the output current in response to a third input signal (VBTAS).

15. A signal processing element as claimed in claim l 4 in which the means to influence comprises a further non-linear device operable, in response to the third input signal, to produce a biasing current (IBIAS) for influencing the output current (IOUT)

16. A signal processing element as claimed in either of claims 14 and 15 in which the means to influence is operable to remove an offset current from the output current.

17. A signal processing circuit substantially as described herein with reference to and/or as illustrated in any of the accompanying drawings.

18. A signal processing method substantially as described herein with reference to and/or as illustrated in any of the accompanying drawings. e... . .- .