GB2415583A

GB2415583A - A frame including two error detection codes, one of the codes masking additional information such as a terminal identifier or Walsh code identifier

Info

Publication number: GB2415583A
Application number: GB0515178A
Authority: GB
Inventors: Cheol Woo You; Young Jo Lee; Young Woo Yun; Suk Hyon Yoon; Soon Yil Kwon; Ki Jun Kim
Original assignee: LG Electronics Inc
Current assignee: LG Electronics Inc
Priority date: 2001-12-05
Filing date: 2002-12-02
Publication date: 2005-12-28
Anticipated expiration: 2022-12-02
Also published as: GB0515178D0; GB2415583B

Abstract

An initial error detection code is calculated for information which is to be transmitted in a frame across a wireless communication network using CDMA. The error detection code is then combined with one or more identifiers, such as a terminal identifier for the terminal which is to receive the frame or/and a Walsh code allocation (WCA) identifier, to produce a first error detection code. The frame contains the information, the first error detection code and a second error detection code which protects both the information and the first error detection code. This method allows additional information (i.e. the identifiers) to be implicitly transmitted, without adding overhead. Preferably the frame is transmitted on PDCCH control channel. The error detection codes may be generated using CRC. The combining operation may be performed using an Exclusive-OR operation, or by initialising CRC registers with identifier bits. The frame may also include tail bits.

Description

ERROR DETECTION CODE GENERATING METHOD AND ERROR

DETECTION CODE GENERATOR

BACKGROUND OF THE INVENTION

I Field of the Invention

The present invention relates to a communication system, and more particularly, to an error detection code generating method and an error detection code generator In a mobile communlcanon system.

2 Backund of the Rclated Art Tvprcally, radio cornmuncaton systems for transferring packet data use physical channels, such as, Pacliet Data Channel (hereinafter referred to as PITCH)' lack.et Data Control Channel (hereinafter referred to as PDCCH) and so forth The PDCH Is a channel for use of transferring packet data that actually needs to be transferred to a relevant terminal, mobile station or user (hereinafter being used interchangeably) Nlany users prefer the POCK based on the Tmc Dvsron T\luluplexmg so stern (hereinafter referred to as TOM system). 'lithe PDCCH contains control nformaucn, enabling a terminal to rccere the data being transEcrred through the PDCE-I without error.

I:gure I Illustrates a control message format and a number of information bits transmitted through PD(.CH according to a related art for a 'TOM system 'he ARQ t (automatic request) channel Denver and subpacket Denver are binary information bits informing the terminal of whether information including PDCH corresponding to PDCCH is to be retransmitted or not. The encoder packet size is binary information bits Informing a data information bit number transmitted on PDCH. The SYNC Identifier Is a terminal dentlficr, and values except (OOOOOOj2 Indicate that control Information of PDCCH Is transferred to \vhich terminal.

When a base station transEcrs packet data using TDAI system, or schedules data and later sending the data to each terminal In sequence, the packet data, which Is transmitted to every terminal, al\vays uses all of the available resources, e.g., Walsh codes, In the PDCIl.

Even \vhen only a part of the Salable resources needs to be used, all of the resources are still used for the packer data. As a result thereof, most of other resources are hasted at the same urne.

For example, data sent on PDCH need to be coded and decoded based on Walsh codes Scnal bits arc converted to >parallel, and the parallel bits are coded using the Walsh codes In order to decode the data, the information regarding the Walsh codes is sent on the PDCCH.

In I D>r system, there arc plurality of un1e intervals 1, 2, 3, 4, 5, 6, etc. and only one of a plurality of terminals Is allotted for each time Interval where a PDCH and PDCCH are sent to the tcrmmal during this allotted umc Interval. For example, if there are users 1 and 3 and torte intervals I and 3, respectively, and If all 3-ary Walsh codes are available for use by terminal 1, all 32-ary Walsh codes are utilized In the PDCH during time Interval 1. 1-lo\vever, If the available \)G'alsh codes decrease in time interval 3, all decreased Walsh codes are unllzed for the PDCH Even before terminal 3 can use the changed/decreased Walsh codes In time Interval 3, it needs to know this information. In order to achieve this, the BS broadcasts such Information using a Walsh Code Space Identification Identifier (WSI) field in the PDCCH (without PDCH) with AL\C_ID field nformanon bit of (000000)2 before ume Inter al 3 to all terminals within a cell And, the base station explicitly transmits a control message including 1\L\C_ID to the ternloals on PDCCH A base station regularly or irregularly broadcasts WSI on the PDCCH without the PDCH to all terminals under its management. In the course of the broadcast, the base station uses ever.> possible power for all terminals (even including terminals In the worst environment) tc, be able to receive the nformanon such that even the terminals In the worst environment can recede the \;iSI. Hence, the broadcasting consumes much power.

I\loreover, u hen the PEPSI change, the base station has to inform the changes to all terminals every ume In those cases, the base station cannot transmit PDCH, so the transmission efficiency of the entire system Is consequently reduced.

She above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical

background

SUMMARY OF THE INVENTION

An object of the nvenuon Is to solve at least the above problems and/or dsad\ranta,res and to provdc at least the advantages described hereinafter

S

An object of the present invention is to provide a modified control message format Another object of the present indention is to provide an additional field for the control message format and reduce the number of bits of the control message format.

A further object of the Invention is to Improve the error detection capability of the PDCC1:.

Another object of the present Invention is to provide an error detection code generating method and an error detection code generator enabling to Increase a use efficiency of resources and improve an error detection capability.

A further another object of the present Invention Is to transmit an SLAC_ID Implicitly.

To achieve at least these and other advantages In whole or In part, there Is provided In a mobile commumcaton sly stem using time division multiplexing and code division multlple.ng, an error detection code generating method according to the present nvenuon Is characterized In that an error detection code Is generated using selectively a control Information for data transmission, a Walsh space Indication Identifier of another terrrunal, and a corresponding terminal Identifier.

To further achevc at least these and other advantages In whole or In part, there Is provided a method that includes generating a first error detection code using the control ntormaton for the data transmission and the Walsh space ndcanon Identifier of another terminal and generating a second error dctecton code using the first error detection code and the terminal Identifier.

PrcEerably, wherein O or 1 bits are padded on the terminal identifier so that a Icogth of the terminal Identifier coincides with that of the first error detection code.

Preferably, the Walsh space indication identifier of another terminal and terminals denufier are not transmitted to a terminal to which the data will be transmitted.

Preferably, the step of gencraung the second error detection code further Includes a step of carrying out an exclusive or operation on the first error detection code and corresponding terminal identifier.

Preferably, the method further Includes adding the second error detecuion code to the control Information for the data transmission.

I'ret'erably, the method Includes annualizing an error detection code generator using the term nal dentfcr and generating an error cletecuon code from the ntalzea error detection code generator using the control nforrnanon for the data transmission PrefcraLly, the method includes ninalzng an error detection code generator using the terminal denufier and generating an error detection code from the annualized error detection code generator using the control nformauon for the data transrnsson and the Walsh space ndcanon dcnuifier of another terminal.

Preferably, the method Includes intualizng an error detection code generator usmg the terminal Identifier and \X;'alsh space ndcanon Identifier of another terminal and gencratrng an error detection code from the malted error detection code generator using the control nformanon for the data transmission.

I'refcrably, the control nformanon for the data transmission Includes an dentificr of a retransmission channel used for retransmission, a subpacket denufier In the retransmission channel, a dare size of a channel through which the data are transmitted, and a Walsh space indication Identifier of a corresponding terminal.

To further achieve at least these and other advantages in whole or in part and In accordance with the purpose of the present invention, as embodied and broadly described herein, there Is provided In a mobile commumcanon system using time division multiplexing and code damson multiplexing, an apparatus for generating an error detection code Is characterized in that an error detection code Is generated using selectively a control Information for data transmission, a Walsh space Indication idenuficr of another terminal, and a corresponding terminal denufier.

I'referably the apparatus Includes an error detection code generator generating a first error detection code using the control nformanon for the data transmission and the Walsh space ndcanon denufier of another terminal and a module operator generating a second error detccuon code using the first error detection code and the terminal Identifier Preferably, the error detection code generator adds the second error detection code to the control Information for the data transmission so as to transmit.

Preferably, the apparatus is annualized by the terminal denufier and generates an error detection code using the control information for the data transmission Prefcrably, the apparatus Is nunhzcd by the terminal denufier and generates an error detection code using the control mformauon for the data transmission and the Walsh space nclcanon denufier of another terminal

G

I3referably, the apparatus Is inualzecl by the terminal Identifier and Walsh space indication identifier of another terminal and generates an error detection code using the control information for the data transmission.

Additional advantages, objects, and features of the invention will be set forth In part in the description which follows and In part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as parucula.ly pointed out In the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

I'he nvcnton will be dcscrbed In detail with reference to the following drawings In hich like retcrence numerals refer to like elements wherein: FIG. I illustrates a message format of the background art; FIG.. .' illustrates a message format In accordance with a preferred embodiment; FIG 3 illustrates a message format in accordance with a prcEerred embodiment; FIG. 4 illustrates a frame structure In accordance with a preferred embodiment; FIG. 5A Illustrates a block diagram of a transmission chain structure of PDCCH In accordance with a preferred cmbodment; FIG. SO illustrates a block diagram of a PDCCH transmission structure In accordance with a preferred cmbodment; FIG. GA Illustrates a block diagram of the outer quality frame quality Indicator of E-PIG 53 m accordance with a preferred embodiment; FIG. 6B Illustrates an inner frame quality Indicator of I7IG 5B In accordance \hth a preferred embodiment; FIG. 7 illustrates a block diagram of an error detection code addition block In accordance with a preferred embodiment; FIG 8 and FIG. 9 Illustrate block diagrams of an error detccuon code addition block In accordance with a preferred embodiment; FIG. 10 Illustrates a diagram of an output result of the error detection code addition block shown In FIG. 8 or FIG 9 In accordance with a preferred embodiment; FIG 11 and FIG. 12 Illustrate block diagrams of the error detection code addition block In accordance with a preferred embodiment; FIG 13 lhsriates a detailed block diagram of the error detection code adduon block n1 accordance with a preferred embodiment; and [:IC]. 14 llustlatcs a diagram of an output result of the error detection code addition block shown In FIG. 13 In accordance with a preferred embodiment.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Prior to the description of the present Invention, parameters used In the present invention are explained as follows.

Walsh code Is a common name of codes having orthogonality to each other and used for transmitting physical channels.

Walsh code space Is a set of Walsh codes available for the current use when a base Station transmits packet data, and elements thereof vary in accordance with time PDCH() means PDCH If at least two PDCHs are available for use. In this case, each of PDCHs divides to use Walsh codes in Walsh code space.

PDCCH(), if it is possible for at least two PDCHs to exist, is a common name of a physical channel Including control Information that a base station transmits to terminals In order to receive PDCH() successfully.

The present invention related to a packet data transmission system of a TDM/CD>f system, whereby a plurality of PDCHs and PDCCHs exist. Hence, expressions of PDCH() and PDCCH() are used In the following description. In other words, when PDCCH(1), PDCCH(2),., PDCCH() and PDCH(1), PDCH(2),.. ., PDCH(N') exists, PDCCH() nL1cates PDCCH that the base station transmits to the terminal to receive PD(:H() successfullv Fgure 2 llustrates the format of the Packet Data Control Channel (I'DCChI) Message In accordance with the preferred embodiment (described hereinafter), over the l'I)CCH, e g., fovard PVCCH (F-PDCCH). l he message format of the PDCCE] includes an additional field called Walsh Code Allocation (WCA) field (e.g., CDM Walsh space Identification (CWSI) field/ (Last Walsh Code Index (LWSI) field), which preferably prevents wasted power consumption caused by broadcasting, and eliminates such broadcast.

Even it broadcasting Is used, the additional field of WCA field reduces the ncEfcences of a prescribed system. She description of the fields illustrated in Figure 2 and the bayous mplernentaton of the WCA field can be found in co-pendng U.S. Application Senal.No., 10/259,292 filed "September 30, 2002, whose entire disclosure Is incorporated herein by re ference This message format can be used In both a TD\f system, he., one PDCH physical channel and one PDCCH physical channel within a prescribed time interval and uses the available Walsh codes, and a Code Division Multiplex (CDM) system, i.e., a plurality of PDCH() physical channels and a plurality of PDCCH() physical channels, where i is an Integer number that Is greater than or equal to 0, within a prescribed period of time and the plurality of users are assigned to a plurality of physical channels by allocation of the Walsh codes within the Walsh code space.

In comparing the fields (EP_SIZE, ACID, SPID, NLAC_ID, and WCA) of Figure 1 (Til'_SIZE,.NCID, SPID, and I\lAC_ID) and Figure 2 (EP_SIZE, ACID, SPID, MAC_ID, and Y'CA), the number of information bits has increased from 13 bits to 20 bits. With the aclduon of the INCA field, the number of bits for the PDCCH In IDl\I/CD!I mode ncrcased, resulting or. more power consumption. Hence, there is a need to decrease the

number of information bits of the PI)CCH fields.

three following approaches may be used for reducing the number of information bits of the PDCCH Method 1 Is to use explicit 8 bits NLAC_ID and add 8 bits CRC (cyclic redundancy check code), which is a class of linear error detecting codes which generate parity check bits by finding the remainder of a polynonual division, for error detection.

Method 2 Is to mask the 16 bits CRC with the implicit user I\L\C_ID and not to transmit the NI;\C_ID Method 3 is to use a 'double CRC', wherein a first CRC Is masked by 8 bit Implicit NIAC_ID and a second CRC is added with the first CRC and the MAC_ID is not transmitted.

The advantage of method 1 Is that the maximum number of blind decodings of the forward PDCCH (E.-PDCCH) is limited to 4, while method 2 rcqures a maximum of G bland decodings of F-PDCCH. Therefore, method 1 may be a prefctred solution in terms of mobile complexity. The advantage of method 2 is that the UDER (UnDetectcd Error Ratio) performance Is better than method 1 due to the increased CRC length l!/Iethod 3 Is a hybrid of method 1 and method 2. If two PDCCHs are supported by a system and the PDCCHs have three types of transmission format, AIethod 3 11 provide approximately the same l.DER performance as method 9, while maintaining the same level of mobile station complexity Since the complexity of method and method 3 Is similar, it is reasonable to choose a method that provides better performance. Hence, the preferred embodiment of the present Invention utilizes method 3 for reducing the number of bits of the PDCCH.

In accordance with a preferred embodiment, which uses the third method, Figure 3 Illustrates the message format of PDCCH when the number of bits of WALtSH_I\.ASK, EXT_NISG_I'E and RESERVED holds equals O (see co-pendng U.S. Application Serial No 10/259,292). As shown therein, the number of bits of the T'DCCH Is decreased to 13 bits, even with the additional sequence number held bits.

The I'DCCl-I frame structure Is shown In Figure 4 including the encoder tall bits of 8 bits lurther, the number of bits can be further reduced by decreasing the number of bits of 1 1 the second CRC to be less than 8 bits, e g, 4 bits, depending upon the system requirements In order to generate the PDCCH frame structure, the following steps are used: Step 1: First CRC bits are calculated based on the 13 input bits of the scrambled PDCCH and masked by the implcit'\lAC_ID'; and Step 2 Second CRC bits are calculated based on the 13 input bits and the first CRC bits generated In step 1.

Step 3: Encoder Tall bits are added.

Depending upon the terminology used, the first CRC may be referred to as the outer CRC and the second CRC may be referred to as the inner CRC Altcrnatvely, the first CRC may be referred to as the inner CRC and the second CRC may be referred to as the outer CRC depending upon the terminology used. For convenience, the former will be used herernaitcr in this prcEcrred embodiment. Figure 5 illustrates a general block diagram of a transmission chain structure of PDCCH in accordance with a preferred embodlrnent.

Referring to Engurc jA, an input sequence of PDCCH, as shown In Figure 3, Includes an ARQ channel Identifier field of 2 bits, an encoder packet size field of 3 bits, and a subpacket identifier field of 2 bits, WCA field of 5 bits and optional sequence number field of t bit. An error detection code such as a CRC (cyclic redundancy check code) Is added to the input sequence In an error detection code addition block 101.

1'a'1 bits for sending a final state of a trellis termination are added to an output sequence of the error detection code addition block 101 in a tall bit addition block 102. The sequence to which else tail bits are added are encoded as a convolution code In an encoder 103. After the outputted sequence having been encodecl, it Is repeated In a symbol repetition block 104. The repeated bits arc punctured in a puncturing block 105 and thereafter, Is Interleaved In a block interleaves 106, and then modulated in a QPSK modulator 107.

Figure 5B Illustrates a detailed PDCCH transmission chain structure in accordance with a preferred embodiment of the present Invention. In this case, the base station preferably transmit on the Forward Packet Data Control Channel at prescribed variable data rates, e.g., of 29G00, 14800, and 7400 bps, depending on the frame duration. The frame duration is preferably NU.\I_SLOTS (NUM_SLOTS = 1, 2, or 4) 1.25-ms slots. All Packet Data Control Channels and Packet Data Channels transmitted simultaneously preferably start ther'ransmssions at the same time (SYS_TI\IE) and have the same durations.

For a Oven base station, the I and Q pilot PN sequences for the Forward Packet Data Control Channel pret'erably use the same pilot PN sequence offset as for the Forward Pilot Clhannei l'hc modulation! symbols transmitted on the first Forward l'acDct Data Control Channel (PDCCI-_ID = '0') should preferably be transmitted using at least as much cocrgy as title modulation symbols transmttcd on the second E onward Packet Data Control Chancel (PVCCH_ID = '1') that Is being transmitted simultaneously, ''max_l'DCH Is 2.

See co-pendng Application Serial 'o.10/259,292.

The Information transmitted on the Forward Packet Data Control Channel preferably comprises scrambled SDU[12 0] and the frame quality ndcatorcovcrcd SDU[20 13], where SDU (Service Data Unit) Is a parameter passed by the SAC Layer. The Forward Packet Data (control Channel frame preferably comprises scrambled SDU[12.0J, the 8-bt frame quality indcator- covered SDU[20.13], the 8-bit inner frame quality indicator (CHIC), and the e,ht l.,ncoder Tall Airs.

First CRC generator 201A and Second CRC generator 201B. The S-bit frame quality indicator-covered SDU[20:13] (first CRC) is generated by performing the modulo-2 addition of the SDU[20 13] (NIAC_ID) passed by the NIAC Layer, with an outer frame quality indicator, which is calculated on the scrambled SDU[12:0]. Second CRC generator 201B: The inner frame quality indicator (second CRC) Is calculated on all bits within the frame, except the inner frame quality indicator itself and the encoder tall bits.

The tall bit generator (202) generates the last eight bits of each Forward Packet Data Control Channel frame are called the Encoder Tall Bits. Preferably, each of the eight bits Is set to 'O'. The cocoder (203) convolutonally encodes as the PDCCH frame. Preferably, the cacoder is initialized to the all-zero state at the cod of each frame. The encoded PDCCH frame undergoes code symbol repetition (204) and the code symbols resulting from the symbol repetucn arc punctured (205) The modulation symbols on the PDCCH are then interleaved, and the nterleavcr block (206) is aligned with the PDCChI frame The modulation symbol Is provided to the signal point mapping block 207 (e.g. modulator) for transmission.. l. 'gure 6A illustrates details of the first (outer) CRC generator 201A of Figure 5 The Abet frame quality ndcator-cocred SDUt20 13] (first CRC) Is generated by performing the modulo-2 addition of the SDU[20:13] (NLAC_ID) passed by the lVlAC I ayer with an outer frame quality Indicator, which Is calculated on the scrambled SDU[12 0] The generator polynomial for the outer frame quality Indicator Is based on g(x) = x8+ x2+x+ 1.

lineally, all shift register elements 201aO-201a7 is preferably set to a logical one and the swtchcs are preferably set In the up position. The register arc clocked once for each of the first 13 scrambled input bits of the Forward I,acket Data Control Channel frame with those bits as input. Then, the switches are set in the down position so that the output is a modulo-2 addition with the 8-bit SDU[20:13] and the successive shift register inputs are 'O's.

Each register Is clocked an additional eight Ames These additional bits form the frame quality ndcator-covered SDL.J[20 13] field, e., the outer CRC, which are transmitted In the order calculated as output.

Figure 6B Illustrates the details of the second (inner) CRC generator 201B Illustrated In Figure 5 The Inner frame quality Indicator (CRC) Is generated based on all bits within the frame, except the Inner frame quality Indicator Itself and the Encoder watt Bits The Forward Packet Data Control Channel preferably uses an 8-bit frame qualty'ndcator The generator polynomial for the Inner frame qua]; Indicator Is preferably based on g(x) = x + x / + x + it; 3 + x T 1 Screen, the Inner frame quality Indicator and the outer frame quality Indicator may be generated by deferent polynomials, repecavely.

Initially, if the frame duration of the Forward Packet Data Control Channel Is 1.25 or 2.5 ms, all shift register elements 201bO-201b7 are preferably ntlalzed to logical one and the switches are preferably set In the up position. If the frame duration of the Forward Packet Data Control (channel Is 5 ms, all shift register elements are preferably mtalzed to logical zero and the switches are preferably set In the up position Each register Is clocked once for each of the first 21 bits of the Forward Packet Data Control Channel frame with those bits as input The switches are set In the down position so that the output is a modulo- 2 addition filth a 'O' and the successive shift register Inputs are 'O's The rester Is clocked an additional eight times These additional bits shall be the inner frame quality Indicator bits, which are transmitted in the order calculated as output.

Figure 7 illustrates a block diagram of an error detection code addition block of Figure 5.\ In accordance with another preferred embodiment. In Figure 7, the error detection code addition block Is called a MAC_ID/WCACRC generator and an error detection code generated from the MAC_ID/WCACRC generator Is called a NLAC_ID/ CA-CRC code, where WCA Is e.g., C\Y7SI or LWCI. The symbol "/" Is generally interpreted as "and" or "or." If "/" is interpreted as an "or," either the NIAC_ID or WCA can be used If "/" Is interpreted as an "and," both NLAC_ID and WCA arc used RcEerrng to Figure 7, an error detection code added to PDCCH() according to this preferred embedment of the present invcr1ton, e.g. a NI.4 C_ID/WCA-CRC code, is generated usn1g the Input sequcoce of PDCCH() Input sequence With WCA(]) and-or ILIAC Identifier (I) (MC_ID()). Selectively, the MAC_ID/4'CA-CRC code can be generated using the PDCCH() sequence and XY7CA(1) of another control chancel PDCCH()). In this case, WCA0) means WCA transmitted on I'DCCH(), where At) and preferably) = 1 - I when > I Ihe NIAC dentfier() Is allocated to a terminal or user which is to receive the information on l'DCCH().

Figure Illustrates a more detailed block diagram of the error detection code addition block illustrated In Figure 7 In accordance with this preferred embodiment. A l\l.NC_ED/\Y'G\-CRC generator 201 according to the present Invention Includes a CRC generator 301 generating a general CRC code and a moclulo operator 303.

IG

In tints instance, the CRC generator ^01 uses PDCCH() input sequence (EP_SIZE, ACID, SPID, \VCA(i) and AI_SN) of x bits and WCA(j) as inputs so as to generate a CRC code having a general M-bits length. The CRC generator 102 is a common name of the CRC generator constituted with transition registers The modulo operator 303 carries out a modulo-2 operation (e.g., exclusive OR opcraton) on the general CRC code of M-bits length and an ILIAC rdentificr(r) of S-bts length so as to generate a MAC_ID/WCA-CRC code of M bits. In this case, If S<Ivl, the remaining bits (M-S) arc padded with '0's or'1's In front or rear of the MAC identifier() and the modulo-2 operation is then carried out.

In Fig. 8, 'CAL) and NIAC_ID() are selectively used to generate the T\IAC_ID/WC.-CRC code. That is, SL\C_ID/WC.-CRC generator uses both or either of then1 Figure 9 illustrates a more detalcd block diagram of the error detection code addition block tI!ustrared In l;gure 7 In accordance with another preferred ernbodrnent. Referring to Figure 9, a CRC generator 401 included In a MAC_ID/WCA-CRC generator iniuallzes values of its transition registers using the NIAC_ID(). If a length of the NL\C denufier(r) Is shorter than that for ntialrzrng the values of the transuon registers of the CRC generator 401, '0's or L's amounting to the necessary number are padUcd in front or rear of the NI.(2 dentifcr() and a modulo operation Is cawed out. The CRC generator 401 having the annualized transition registers based on MAC_ID() uses an PDCCH(i) Input sequence of x- brts number and WCA() of PDCCH() so as to generate a MAC_ID/WCA-CRC code having an NI-brt length. In Fig 9, WCA() and MAC_ID(r) are alternately used to generate the NIAC_ID/WCA-CRC code. That Is NIAC_ID/W CA-CRC generator uses both or either of them.

Figure 10 Illustrates a diagram of an output result of each of the error detection code addition blocks of Figures 8 and 9. The NIAC_ID/WCA-CRC() code Is added to the PDDCH() input sequence for Input to the tall bit addition block 102 of Figure A\. As can be appreciated the arrangement order of the MAC_ID/WC.-CRC() code and PDCCH() input sequence can be reversed. The SIAC dentfier() is used for generating I<-\C_ID/CA-CRC() and need not be transmitted separately to a reccvmg end when WCA(J) Is not used ( / = or) Likewise when the SIAC dentfier() and WCA(J) are both used ( / = and) these parameters need not be transmitted separately to therccevng end Instead the Nl.NC_ID 'WCA-CRC() and PDCCIf() input sequence are transmitted to the recess ink- end If only the i\lAC_ID() Is used for generating the AL\C_ID/WCA-CRC code (he.

w Shout \( A0) there arc no special consderatons/factor that need to be tal;en Into account. However if the WCA( ) Is used with or without bL\C_ID()) by the NLAC_ID/\Y CA-CRC generator the following operational factors should be considered.

First OperauQnal Consideration When N number of PDCI-()s and N number of PDCCH()s are used a terminal should rccognze NIAC idcntfier() and WCA(J) In order to receive PDCCH(). Hence in order to rcccvc PDCCEf() I'DCCH0) needs to be correctly received in order to interpret WCA(J). If the Interpretation of WCA()) Is wrong or incorrect the terminal Is unable to receive l'VCCH() correctly.

Second Operation al Con sld eratton In the first operational consideration, assuming that) is (i-1), a terminal should recognize NfAC tdcntifier(i) and WCA(t-1) in order to receive the PDCCH(i). In order to receive the PDCCH(t), PDCCH0-1) needs to be correctly received in order to interpret WCA(t-1). However, a value of WCA(0) should be determined previously, e.g., WCA (0) = (00000), Figure 11 illustrates a more detailed block diagram of the error detection code addition block of Figure 7 In accordance with another preferred embodiment. Referring to Figure 11, a hIAC_ID/WCA-CRC generator 201 according to the present tnventton tocludes a CRC generator 501 generating a general CRC code and a modulo operator 502.

Tl1c CRC generator 501 uses PDCCH(t) input sequence of x-btts to generate a general CRC code of.NI-btr Icngrh. The modulo operator 502 carries out modulo operation on the general CT'C code and {.\l.-\C tdenubter(t) of S bits 4- WCA()) of V bits}, where A, so as to generate hIAC_ID/\Y'CA-CRC(t) of!\f bits. If (S+)<Nl, '0's or'1's are padded in front or rear of the sequence comprising the {?IAC tdenttfier(t) + WCA0)}, prior to the modulo 2 operation being carried out. In Fig. 11, WCA0) and NfAC_ID(t) are selectt\:ely used to generate the NIAC_ID/WCA-CRC code That is, NIAC_ID/WCA-CRC generator uses both or either of them I-'tgurc 12 illustrates a more block diagram of the error detection code addition block In Figure 7 in accordance with another preferred embodiment. Refcrrtng to Figure 12, a CRC generator G01 included in a NfAC_ID/WCA-CRC generator 201 imttaltzcs values of its transition registers ustog {ILIAC identther(t) + WCA()}, where tie' The CRC generator G01 having the tnttaltzed transition registers uses the I,DCCH(t) toput sequence of xbtt length as an Input so as to generate IvL\C_ID/;'CA-CRC(I) of NI-blts length. If a length of the {MAC identifier(l) + WCA(j), icy} is shorter than that for initializing the values of the transition registers of the CRC generator 601, 'O's or'1's amounting to the necessary number are padded In front or rear of the sequence constituted with the {MAC dentlfier(l) + N>;'CA()), Il.} and Inltiallzaton Is then carried out.

Figure 13 illustrates a detailed block diagram of the error detection code addluion block of Figure 5 in accordance with another preferred embodiment. The error derecuon code addition block serves as an overlap hL\C_ID/WCA-CRC generator 703 to generate an of erlap),C_ID/V'CA-CRC code. The overlap M AC_ID/WCA-CRC generator 703 ncludcs a NL4C_ID/\X'CA-CRC generator 701 and a CRC generator 702 The CRC generator 03 Includes transition registers. al he I\LiLC_ID/\C'CA-CRC generator 701 may comprise ens one of the preferred crnbodlments shown In Figures 8,'), 11 and 12.

The NIAC_IDjWCA-CRC generator 701 uses the PDCCH(i) Input sequence of x bts, Including \\CA(J) of Y-bts and a hIAC dentifier() of S-bts from Its Inputs so as to generate MAC_ID/WCA-CRC(I) of NI-blts. The MAC dentficr(l) IS allocated to a terminal or a user Intended to receive the information on the PDCCH().

The CRC generator 702 uses PDCCH(I), and NL\C_ID/WCA-CRC() sequence to generate CRC() of P bits The generated CRC() and hI:\C_ID/WC N-CRC(I) are connected to each other to generate the overlap N'L\C_ID/WCA-CRC(I), which IS In Inputted to a following stage In the transmission chain structure of Figure SA or Fgurc 5B.

Figure 14 Illustrates a diagram of an output result of the error detccton code addition block of Figure 13. The arrangement order of the l\L\C_ID/WCA-CRC(i) and PDCCH(I) input sequence can be reversed Since, the NL\C dentificr(i) and X'CA(1) are used for generating MAC_ID/WCA- CRC(i), these fields need not be transmitted to a receiving end, and the overlap MAC_ID/WCA-CRC(i) and PDCCH(i) sequence are transmitted to the receiving end If the WCA(1) Is not used, this embodiment is quite similar or the same as the embodiment of the double CRC First Operational Consideration of Figure 13 Cohen N number of I,DCH()s and N number of PDCCH()s are used, a terminal fudges whether l'DDCH() Is received normally or not through a series of the following processes using the overlap MAC_TD/WCA-CRC() The terminal checks CRC() In the overlap l\lAC_ID/'CA-CRC() to fudge Whetller l'DDCH() Is received correctly or not If a transmission length of PDCCH() Is Sealable, talc terminal recognizes the transmission length of PDCCH() by chcckng the CR( Id).

Having determined that the PDDCH(i) Is correctly received, the terminal judges whether PDCCH() is its control channel or not using the TvLAC_ID/WCA-CRC() in the overlap I\ LAC_ID/WCA-CRC() as well as judging again as to whether PDCCH() Is correctly recent ed In this case, In order to check the MAC_ID/WCA-CRC(), the terminal needs to knov. the ALEC denufier() ndcpendently or both the ILIAC denufier() and XY'CA(J). In case that the terminal needs to know both the l\L\C identifier() and WCA() , 1'DCCH()) needs to be correctly reccvcd so that SX'CA(1) can be interpreted In order to recevc I'DCCH() If the nterpretanon of \'Y'CA() Is wrong, an error will be detected when NIAC_TD/WCA-CRC(i) is checked.

Second Operational Consideration of Figure 13 If one or more PDCCH(i)'s are simultaneously transmitted, the PDCCH(i)'s transmitted simultaneously have the same transmission length, and a specific PDCCH(k) and the rest of the PDCCH(i)s (except the specific PDCCH(k)) can have the overlap NL\C_ID/'CA-CRC()s of different structures, respectively.

Assuming that the specific PDCCH(k) Is PDCCH(I), the process goes as follows.

The PDDCH(1) generates the overlap NIAC_ID/WCA-CRC(1) through the same process of Figure 13, and the terminal checks as to whether an error of PDDCH(1) has occurred or not through the first operational conslderanon.

The PDCCH(l)s, except PDCCH(l) excludes the generation process of CRC() of Figure 13, and an overlap Nf.NC_ID/\Y'C.-CRC() of L bits Is generated by the NLiC_ID/'\Y'CA-CRC generator. '1'he terminal checks whether errors of the 1'DCCH()s have occurred or not through the first operational consideration. Hence, the check for CRC() IS not carrel cut.

1'hlrd Operational Consideration of Figure 13 In the first and second operational considerations, assuming that I Is (-1), a terminal should recogmze NIAC dentfier(l) and WCA(-1) In order to receive PDCCH(l). In order to receive l'DCCI-I(), POCCH0-1) needs to be correctly received so that WCA(I-I) can be correctly interpreted. FIence, a value of VC'CA(0) needs to be previously determined For example, it may be that WCA(0) = (00000): Accordingly, the preferred embodiment enables operation In CDM/l'Dil mode, thereby reducing waste of avarlahle sources Iloreover, the present Invention uses double CRC or the ?vlAC_ID/WCA-CRC code, thereby reducing the number of bits of the PDCCH and improving the error detection capability of PDCCH(i).

The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses The description of the present Invention is Intended to be Illustrative, and not to limit the scope of the claims. Many alternatives, modfcatlons, and variations Null be apparent to those skilled in the art. In the claims, means-plusfuncton clauses are intended tO cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.

Claims

CLAIMS: 1. A method of performing an error detection of a received frame

over a prescribed channel, comprising: 5performing a first error detection using a first frame quality indicator from the received frame; and performing a second error detection using a second frame quality indicator from the received frame and an assigned terminal identifier.
2. The method of claim 1, wherein the first frame quality indicator is covered by the assigned terminal identifier.
153. The method of claim 1, wherein the assigned terminal identifier is a MAC identifier.
4. A method of generating an error indication code for a frame of a first prescribed bits to be transmitted over a prescribed channel, comprising: generating a first error indication code of a first prescribed length based on masking of second prescribed bits corresponding to a prescribed field excluded from the frame; and generating a second error indication code of a second prescribed length.
5. The method of claim 4, wherein the first prescribed bits equals 13 bits and the prescribed channel is a packet data control channel.
6. The method of claim 4, wherein each of the first and second prescribed lengths is 8 bits and each of the first and second error indication codes is a cyclic redundancy check code.
7. The method of claim 4, wherein the first prescribed bits corresponding to a message format of the frame includes information corresponding to encoder packet size field, ARQ channel identifier field, subpacket identifier field, Walsh Code Allocation field and sequence

number field of the message format.
8. The method of claim 4, wherein the prescribed field is a terminal identifier intended to receive the frame over the prescribed channel.
9. The method of claim 4, wherein the second prescribed bits equals 8 bits.
10. The method of claim 4, wherein a modulo-2 operation is performed for masking of the second prescribed bits.
11. The method of claim 10, wherein the modulo-2 operation is an exclusive OR operation.
12. The method of claim 4, wherein the masking is performed by initializing a plurality of transition register of a code redundancy check code generator based on the second prescribed bits.
13. A method of determining a terminal identification and error detection of a received frame over a first prescribed channel, comprising: obtaining a terminal identification from a first frame quality indicator; and determining an error of the received frame from a second frame quality indicator.
14. The method of claim 13, wherein the prescribed channel is packet data control channel.
15. The method of claim 13, wherein each of the first and second frame quality indicators is a cyclic redundancy check code (CRC), and the first and second frame quality indicators are outer and inner CRCs, respectively.
16. The method of claim 13, wherein the frame comprises information bits corresponding to a message format having encoder packet size field, ARQ channel identifier field, subpacket identifier field, Walsh Code Allocation

field, and sequence number field.
17. The method of claim 16, wherein the frame further comprises the first and second quality frame indicators and encoder tail bits.
18. The method claim of 17, wherein the encoder packet size field comprises 3 bits, ARQ channel identifier field comprises 2 bits, subpacket identifier field comprises 2 bits, first Walsh Code Allocation field comprises 5 bits, sequence number field comprises 1 bit, each of the first and second quality frame indicators comprises 8 bits and encoder tail bits comprises 8 bits.
19. The method of claim 13, wherein the first terminal identification is masked within the first quality frame indicator by a modulo-2 operation.
20. A method of performing an error detection of a received frame over a prescribed channel, comprising: performing a first error detection using a second frame quality indicator from the received frame; and performing a second error detection using a first quality indicator from the received frame and an assigned terminal identifier.
21. The method of claim 20, wherein the first quality indicator is covered by the terminal identifier.
22. A channel transmission chain structure comprising: an error detection code addition block coupled for receiving a frame of a first prescribed channel, and for generating a first error indication code having a masked terminal identification of a first prescribed channel and a second error indication code; a tail bit generator coupled to the error detection code addition block for generating encoder tail bits; an encoder coupled to the tail bit generator for encoding a frame received from the tail bit generator to output an encoded frame; and an output circuit for transmitting the encoded frame.
23. The channel transmission chain structure of claim 22, wherein the error detection code addition block, comprising: a first cyclic redundancy check code generator (first CRC generator) receiving information bits of the first prescribed channel and the terminal identification to output an outer CRC corresponding to the first error indication code; and a second cyclic redundancy check code generator (second CRC generator) coupled to the first CRC for generating an inner CRC corresponding to the second error indication code.
24. The channel transmission chain structure of claim 23, wherein the terminal identification is masked by a modulo-2 operation.
25. A channel frame structure of prescribed channel comprising: a first prescribed number of first information bits of a prescribed channel; a first quality frame indicator of a second prescribed number of bits, the first quality frame indicator being based on a second information bits of a prescribed channel and 5a second quality frame indicator of a third prescribed number of bits.
26. The channel frame structure of claim 25, wherein the second information bits indicate a MAC identifier of a first terminal intended to receive the first information bits.
27. The channel frame structure of claim 26, the second information bits further indicates Walsh Code Allocation information for a second terminal.
28. The channel frame structure of claim 27, the first quality frame indicator is generated based on one of modulo- 2 operation of the second information bits and initialization of a plurality of cyclic redundancy code generator registers with the second information bits.
29. The channel frame structure of claim 25, wherein the prescribed channel comprises a packet data control channel.
30. The channel frame structure of claim 25, wherein the first prescribed number is 13 bits.
531. The channel frame structure of claim 25, wherein the second information bits equals 8 bits.
32. The channel frame structure of claim 25, wherein each of the second and third prescribed number of bits equals 8 bits.
33. The channel frame structure of claim 25, further comprising an encoder tail bits of a fourth prescribed number of bits.
34. The channel frame structure of claim 33, wherein the fourth prescribed number of bits equals 8 bits.
35. The channel frame structure of claim 25, wherein the first information bits are scrambled information bits.
36. The channel frame structure of claim 25, wherein the first and second frame quality indicators comprises a cyclic redundancy check code (CRC).
37. The channel frame structure of claim 25, wherein the first frame quality indicator is based on modulo-2 operation using the second information bits.
38. The channel frame structure of claim 25, wherein the first information bits further includes Walsh Code Allocation information of a second packet data control channel, which is different from a first packet data control channel.
39. The channel frame structure of claim 38, wherein the first quality frame indicator is generated based on one of modulo-2 operation of the second information bits and initialization of a plurality of cyclic redundancy code generator registers with the second information bits.
40. The channel frame structure of claim 39, wherein the second information bits is indicative of a terminal identification of the first packet data control channel.
41. An apparatus for generating an error detection code for a mobile communication system, the improvement comprising an error detection code being generated by selective use of an information for data transmission on a first prescribed channel for a first terminal, a Walsh Code Allocation identifier of a second prescribed channel for a second terminal and a terminal identifier corresponding to the first terminal.
42. The apparatus of claim 41, wherein the error detection code is generated by an error detection code generator receiving the control information and the Walsh Code Allocation identifier selectively; and a modulo operator performing an exclusive OR operation based on the terminal identifier.
43. The apparatus of claim 41, wherein the error detection code is generated by a cyclic redundancy check code (CRC) generator having a plurality of transition registers, which are initialized based on the terminal identifier.
44. The apparatus of claim 43, wherein the plurality of transition registers are further initialized based on the Walsh Code Allocation identifier.
45. The apparatus of claim 41, wherein the error detection code is generated by an error detection code generator receiving the control information; and a modulo operator performing an exclusive OR operation based on the terminal identifier and the Walsh Code Allocation identifier alternatively.
46. A method of generating error indication codes for a frame to be transmitted over a prescribed channel, comprising: generating a first masked error indication code of a first prescribed length based on masking a terminal identifier on a first error indication code generated based on a first information; and generating a second error indication code based on the first information and the first masked error indication code.
47. The method of claim 46, wherein the prescribed channel is a packet data control channel.
48. The method of claim 46, wherein the first information have a variable length.
49. The method of claim 46, wherein the first masked error indication code and the second error indication code is the same length.
50. The method of claim 46, wherein the first error indication code and the second error indication code is generated by each different polynomial.
51. A method of receiving a data frame having two frame quality indicators over a prescribed channel, comprising: determining whether the prescribed channel is assigned to a mobile station or not by detecting a terminal identification from a first frame quality indicator.
52. The method of claim 51, further comprising the steps of: checking whether the received frame is good or bad based the first frame quality indicator; and checking whether the received frame is good or bad based the second frame quality indicator.
53. The method of claim 51, wherein the prescribed channel is a packet data control channel.