GB2415100A - A steering current generator for a four-quadrant phase interpolator - Google Patents
A steering current generator for a four-quadrant phase interpolator Download PDFInfo
- Publication number
- GB2415100A GB2415100A GB0511984A GB0511984A GB2415100A GB 2415100 A GB2415100 A GB 2415100A GB 0511984 A GB0511984 A GB 0511984A GB 0511984 A GB0511984 A GB 0511984A GB 2415100 A GB2415100 A GB 2415100A
- Authority
- GB
- United Kingdom
- Prior art keywords
- current
- steering
- switch
- bleed
- generator according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/661—Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
Abstract
A set of current switches 21 provides complementary weighting current signals to switches 23 and 26 which each direct one of the weighting current signals to one of the two current mirrors in each half of the circuit, each mirror output controlling the current source in a respective branch of a phase interpolator (figure 1). The small bleed currents 25 ensure that none of the four output weighting currents is ever zero. The quadrant selection code applied to the switches 22,23,26,27 is a Gray code. Only a single bit change occurs when the required phase moves between neighbouring points on either side of a quadrant boundary (32,3 3 in figure 3).
Description
IMPROVEMENTS IN OR RELATING TO TNTERPOLATTON.
This invention relates to interpolation and more particularly to an interpolator structure suitable for fabrication as part of an integrated circuit. The invention relates more particularly still to the generation of steering currents required to move the operating point of the interpolator are around the phase circle.
The present invention provides a steering current generator as defined in the appended claims.
There will now be described an example of the invention, with reference to the accompanying drawings, of which: Figure I is a circuit diagram of a phase interpolator.
Figure 2 is a steering current generator according to the invention.
Figure 3 is diagram plotting the outputs of the current generator.
A schematic of the structure of an interpolator is shown in Figure 1. For more details of the operation and function of such a circuit the reader is referred to the applicant's co-pending application filed under the designation TI-38552. 66 g O5 1 I A=' O) It will be observed that the interpolator has a four stage structure and that each stage is biased by a current mirror, such as current mirror 11. The presence of the current mirror enables the stage to be controlled by a steering currents In, It, T2, 13 and the generation of such a steering current will now be considered in more detail.
A steering current generator 20 is shown in Figure 2. The required resultant current is generated by summing a number of currents generated and controlled within the circuit. Sub-circuit 21 may for example be controlled by differential inputs PS and PSZ to sum current into the summing node of switching circuit stages B0 and Bl respectively (i.e. stages 23 and 26). In an exemplary embodiment of the current steering control arrangement, there are 31 instances of circuit block 21, receiving 31 separate single bit inputs such that each of the transistors within the Instances of the circuit maybe individually controlled to supply current to either stage B(), B I l in accordance with the single bit inputs. Note that since the PS<i> is the inverse of PSZ<i> the total current provided to the stages BO and B 1 is a constant, namely 31 times Tb.
Referring now to Figure 3, assume that the interpolator is operating at operating point 31, equivalent to a PS input of O; i.e. 31 bits each with a value of 0. The operating point may be stepped by gradually increasing the number of bits set and eventually the operating point reaches 32, where all 31 bits have the logic value of 1.
Thus far, the operating point of the interpolator has been restricted to a first quadrant of operation 30. The operating quadrant is defined by a two bit code (QS), which in the first quadrant 30 has the value 00. In that quadrant the control signals QS cause the current summed from the circuit blocks 21 to form currents IBO and 131. Those currents also comprise an additional unit of lb provided by a current source 28, 29 respective to each of the stages 23 and 26. These currents TBO and To are mirrored into the interpolator of Figure I as mentioned above.
In the circuit implementation (Figure 2) the QS inputs, also control further the stages of the circuit, such as stages 22 and 27 (stages B2 and B3) and are input to one of two coupled transistors in each stage, such as input 24.
In quadrant 00 stages B2 and B3 do not receive any current from the circuit blocks 21 but only units of I/' Ib from respective current sources, which currents respectively form currents TB2 and TB3, which are mirrored into other stages of the interpolator.
Stages B2 and BO are cross coupled togcthcr, and stages B I and B3 likewise. Each of the stages are fed from a different leg of the single bit driven circuits, 21. (B2 and BO from one leg and Bl and B3 from the other.) Moving the operating point to the first point of the second quadrant 35 is achieved by altering the QS Code from the value 00 to the value 01. This switches the current from circuit blocks 21 from contributing to IBO to contributing to Ins, and Ir30 becomes IN Tb. It is not necessary to alter the individual bit codes applied to the circuit blocks 21.
The operating point may then be stepped through the second quadrant, 35 by stepwise reduction of the number of set bits applied to the circuits 21, eventually reaching operating point 34, which corresponds to the all zeros input condition.
In Figure 3, the operating point of the current generator is illustrated by the current summation of (IBO-II32) as the x-axis and (l[31-IB3) as the y-axis. In the circuit of Figure I, however, of course, 1BO T[3I, TI32, II33 control the four stages individually and respectively, but the angular position of the spots in the diagram about the origin nonetheless also represent the phase of the signal output by the interpolator.
A number of advantages of the circuit has thus far described will be apparent.
Firstly, the circuit is fully differential.
The quadrant selection code is intrinsically, Gray-coded, it and since the single bit values for operating points, which our neighbours across the reference phase boundaries such as points 32 and 33 are the same, by virtue of the Gray-code only a single bit change in the entire circuit is required to cross the reference phase boundary, for example from the first sector quadrant 30 the second quadrant 35. It will be appreciated that the entire phase wheel, may be transitioned by changing a single bit at a time.
It will be noted that the bleed current applied to stage 22 is in magnitude of one half different to that applied to circuit portion 23. In this way, when the circuit switches quadrants, a full step value is achieved by switching from for example -/21b to +/21b. By virtue of this arrangement the output of the interpolator is never derived from a single reference phase. This has the important consequence that the current in any of the stages is never reduced to zero.
In particular embodiments, it may be found that other bleed current combinations are advantageous for example, 7/2 for circuit 22 and for circuit 23.
Note also that the architecture of the interpolator of Figure 1 allows other numbers of reference phases and respective circuit stages therefor, from a minimum of three. Versions of the steering current generator comprise two summing nodes and sector switches that direct the currents from the circuit blocks 21 to the two active circuit stages of the circuit of Figure I. ("Sector" has been used since there may be a number of "quadrants" unequal to four.) Bleed currents (e.g. '/21b) are switched to the remaining circuit stages.
Claims (9)
- CLAIMS: 1. A steering current generator for a phase interpolator,comprising: a plurality of steering current outputs, first and second summing nodes, a plurality of current source blocks, each having two output legs respectively connected to one of the summing nodes, having a control input and being responsive to that control input to switch an output current to one or other of the legs, first and second switching circuit stages, each having a current input respectively connected to one of the summing nodes and a control input, and each being connected so that in response to the control input they switch the currents from their respective summing nodes to different ones of the steering current outputs.
- 2. A steering current generator according to claim I wherein the first switching circuit stage is connected to switch the current from the first summing node to either a first or a second one of the current steering outputs and the second switching circuit stage is connected to switch the current from the first summing node to either a third or a fourth one of the current steering outputs, the third and fourth ones being different from the first and second ones.
- 3. A steering current generator according to claim I comprising a bleed current source and a third switching stage connected to receive the current from the bleed current source and switch it to a steering current output that is not receiving a current from a summing node.
- 4. A steering current generator according to claim 3 comprising a second bleed current source and a fourth switching stage connected to receive the current from the second bleed current source and switch it to a steering current output that is not receiving a current from a summing node.
- 5. A steering current generator according to claim 2 comprising first and second bleed current sources and third and fourth switching stages connected to receive respectively current from the first and second bleed current sources and to switch them to ones of the steering current outputs that is not connected to receive current from a summing node.
- 6. A steering current generator according to claim 5 wherein the first bleed current generator is connected to switch its current to either the first or second steering current output and the second bleed current generator is connected to switch its current to either the third or fourth steering current output.
- 7. A steering current generator according to any preceding claim comprising first and second additional current sources connected to supply a fixed unswitched current to the first and second summing nodes respectively.
- 8. A steering current generator according to any preceding claim wherein the number of steering current outputs is exactly four.
- 9. A phase interpolator comprising a steering current generator according to any preceding claim.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0413149A GB0413149D0 (en) | 2004-06-12 | 2004-06-12 | Improvements in or relating to interpolation |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0511984D0 GB0511984D0 (en) | 2005-07-20 |
GB2415100A true GB2415100A (en) | 2005-12-14 |
GB2415100B GB2415100B (en) | 2007-02-14 |
Family
ID=32732400
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0413149A Ceased GB0413149D0 (en) | 2004-06-12 | 2004-06-12 | Improvements in or relating to interpolation |
GB0511984A Expired - Fee Related GB2415100B (en) | 2004-06-12 | 2005-06-13 | Improvements in or relating to interpolation |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0413149A Ceased GB0413149D0 (en) | 2004-06-12 | 2004-06-12 | Improvements in or relating to interpolation |
Country Status (1)
Country | Link |
---|---|
GB (2) | GB0413149D0 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6107848A (en) * | 1997-10-08 | 2000-08-22 | Pheonex Vlsi Consultants Ltd. | Phase synchronisation |
EP1104110A2 (en) * | 1999-11-26 | 2001-05-30 | Fujitsu Limited | Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission |
US20030183842A1 (en) * | 2002-03-22 | 2003-10-02 | Kizer Jade M. | System with phase jumping locked loop circuit |
-
2004
- 2004-06-12 GB GB0413149A patent/GB0413149D0/en not_active Ceased
-
2005
- 2005-06-13 GB GB0511984A patent/GB2415100B/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6107848A (en) * | 1997-10-08 | 2000-08-22 | Pheonex Vlsi Consultants Ltd. | Phase synchronisation |
EP1104110A2 (en) * | 1999-11-26 | 2001-05-30 | Fujitsu Limited | Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission |
US20030183842A1 (en) * | 2002-03-22 | 2003-10-02 | Kizer Jade M. | System with phase jumping locked loop circuit |
Also Published As
Publication number | Publication date |
---|---|
GB2415100B (en) | 2007-02-14 |
GB0413149D0 (en) | 2004-07-14 |
GB0511984D0 (en) | 2005-07-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20210613 |