GB2412987A - Programmable hashing circuit - Google Patents

Programmable hashing circuit Download PDF

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Publication number
GB2412987A
GB2412987A GB0512314A GB0512314A GB2412987A GB 2412987 A GB2412987 A GB 2412987A GB 0512314 A GB0512314 A GB 0512314A GB 0512314 A GB0512314 A GB 0512314A GB 2412987 A GB2412987 A GB 2412987A
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Prior art keywords
input
gates
xor
memory address
programmed
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GB0512314A
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GB2412987B (en
GB0512314D0 (en
Inventor
Paul J Moyer
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HP Inc
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Hewlett Packard Co
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Priority claimed from US10/123,755 external-priority patent/US6804768B2/en
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Publication of GB0512314D0 publication Critical patent/GB0512314D0/en
Publication of GB2412987A publication Critical patent/GB2412987A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

An embodiment of the invention provides a circuit and method for optimizing an index hashing function in a cache memory on a microprocessor. A programmable index hashing function is designed that allows the index hashing function to be programmed after the microprocessor has been fabricated. The index hashing function may be "tuned" by running an application on the microprocessor and observing the performance of the cache memory based on the type of index hashing function used. The index hashing function may be programmed by several methods.

Description

24 1 2987 A Programmable Microprocessor Cache Index Hashing Function
s FIELD OF TIIE INVENTION
This invention relates generally to electronic circuits. More particularly, this invention relates to integrated electronic circuits and cache memory.
BACKGROUND OF TlIE INVENTION
Hashing is the transformation of a string of characters into a usually shorter fixed-length value or key that represents the original string. Hashing may be used to index and retrieve items in a database or a memory hierarchy because it is usually faster to find the item using the shorter hashed key than to find it using the original value. It may also be used in many encryption algorithms.
The hashing algorithm is called a hash function. The hash function is used to index the original value or key and then used later each time the data associated with the value or key is to be retrieved. A good hash function also should not produce the same hash value from two different inputs. If it does, this is known as a "collision". A hash function that offers an extremely low risk of collision may be considered
acceptable.
If a collision occurs, another function may be used. This function is commonly called a "collision rule." The collision rule generates a succession of locations until one is found that is not in use already.
Is It is desirable, for efficiency reasons, to have as few collisions as possible. To achieve this, the hash function should not be pre-disposed to favor any one particular location or set of locations. In other words, it should spread the potential keys around l the table as evenly as possible. This is normally done by making the haste fi'nction depend on all parts of the key, computing a large integer from the key, dividing this integer by the table size, and using the remainder as the hash function value. Other commonly used hash functions are the "folding" method, the "radix transformation" method, and "digit rearrangement" method. The type of hash function used is dependent on the application it is designed for.
A hashing function may be designed for indexing memory addresses to cache memory. Designing such a hashing function requires considerable insight into the memory access behavior ofthe applications that will access the cache. It is not realistically feasible to simulate all possible programs to find an optimal hashing function before the CPU is fabricated. As a result, the hashing function used for indexing memory addresses to cache memory is most likely not optimal for any one application. Having a programmable hashing function would allow the flexibility of index calculation "tuning" after the CPU has been designed and implemented. A "tuned" hashing function would then allow the cache to operate more efficiently.
This invention allows for many different possible index mappings by programming the hashing Unction after the CPU has been designed and implemented.
By running an application many times, information may be obtained about the application cache memory behavior. With this information, a more optimal hashing no function may be derived and implemented for cache indexing. In turn, this results in significant improvement in cache memory performance.
SUMMARY OF THE INVENTION
An embodiment of the invention provides a circuit and method for optimizing as an index hashing function in a cache memory on a microprocessor. A programmable of index hashing function is designed that allows the index hashing function to be programmed after a microprocessor has been fabricated. The index hashing function may be "tuned " by running an application on the microprocessor and observing the performance of the cache memory based on the type of index hashing function used.
s The index hashing function may be programmed by several methods.
Other aspects and advantages ofthe present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawing, illustrating by way of example the principles of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a schematic drawing of a generic index hashing function. Prior Art Is Figure 2 is a schematic drawing of a programmable index hashing function.
DETAILED DESCRIPTION OF TlIE PREFERRED EMBODIMENT
to Figure I is a schematic drawing of an example of a index hashing function.
The lower half, B(N)-B(I), 118-104, ofthe memory address (2N+X bits), 102 is connected to an input of each XOR of N XORs, 150136, respectively. The upper half, B(2N)-B(N+1), 134-120, ofthe memory address (2N+X bits), 102, is connected to the other input of each XOR of N XORs, 150-136, respectively. The outputs of the as N XORs, 150-136, form a new N-bit memory index, ID(N/IDl, 166-152.
B1, 104, of memory address, 102 is connected to an input of XOR1, 136. B2, 106, of memory address, 102 is connected to an input of XOR2, 138. B3, 108, of memory address, 102 is connected toaninputofXOR3, 140. B4, 110, ofmemory address, 102 is connected toaninputofXOR4, 142. B(N-3), 112, ofmemory address, 102 is connected to an input of XOR(N-3), 144. B(N-2), 114, of memory address, 102 is connected to an input of XOR(N-2), 146. B(N-1), 116, of memory address, 102 is connected to an input of XOR(N- 1), 148. B(N), 118, of memory address, 102 is connected to an input of XOR(N) , 150. B(N+I), 120, of memory address, 102 is connected to an input of XORI, 136. B(N+2), 122, of memory address, 102 is connected to an input of XOR2, 138. B(N+3), 124, of memory address, 102 is connected to an input of XOR3, 140. B(N+4), 126, of memory address, 102 is connected to an input of XOR4, 142. B(2N-3), 128, of memory address, 102 is connected to an input of XOR(N-3), 144. B(2N-2), 130, of memory address, 102 iscoMectedtoaninputofXOR(N-2), 146. B(2N-1), 132,ofmemory IS address, 102 is connected to an input of XOR(N-I), 148. B(2N), 134, of memory address, 102 is connected to an input of XOR(N), IS0. The outputs of XOR(N) XOR1, 150-136, form the indexed memory address, ID(N) -ID I, 166-152, respectively.
Figure 2 is a schematic drawing of one example of a programmed hashing function. In this example, the bits ofthe upper half, B(2N)-B(N+1), of memory address, 202, (2N+X bits) are each connected to an input of AND gates, AND(2N) AND(N+1) respectively. The other input of AND gates, AND(2N) AND(N+l), are connected to programmable nodes, 278-268, 213, respectively. The programmable nodes, 278-268, 213 may be programmed aRer a microprocessor is fabricated to improve the performance of the hashing function. The outputs of AND gates, AND(2N)-AND(N+1), 296, 298,201-211, are connected to an input of each XOR gate, XOR(N)-XOR1, 250-236 respectively. The memory address bits B(N) B1, 218 204, are connected to a second input of each XOR gate, XOR(N}XORI, 250- 23C, respectively. The outputs, lD(N) ID1, 266-252, of XOR gates, XOR(N} XORI, 250 23C, form the N-bit indexed memory address.
B 1, 204, of memory address, 202 is connected to an input of XOR1, 236. B2, 206, of memory address, 202 is connected to an input of XOR2, 238. B3, 208, of memory address, 202 is connected to an input of XOR3, 240. B4, 210, of memory address, 202 is connected to an input of XOR4, 242. B(N-3), 212, of memory lo address, 202 is connected to an input of XOR(N-3), 244. B(N-2), 214, of memory address, 202 is connected to an input of X0R(N-2), 246. B(N-I), 216, of memory address, 202 is connected to an input of XOR(N-I), 248. B(N), 218, of memory address, 202 is connected to an input of XOR(N), 250. B(N+1), 220, of memory address, 202 is connected to an input of AND(N+I), 294. B(N+2), 222, of memory address, 202 is connected to an input of AND(N+2), 292. B(N+3), 224, of memory address, 202 is connected to an input of AND(N+3), 290. B(N+4), 226, of memory address, 202 is connected to an input of AND(N+4), 288. B(2N-3), 228, of memory address, 102 is connected to an input of AND(2N-3), 286. B(2N-2), 230, of memory address, 202 is connected to an input of AND(2N-2), 284. B(2N-1), 232, of memory to address, 202 is connected to an input of AND(2N-1), 282. B(2N), 234, of memory address, 202 is connected to an input of AND(N), 280. Node 213 may be programmed to a logical "high" or "low" and is connected to a second input of AND(N+1), 294. Node 268 may be programmed to a logical "high" or "low" and is connected to a second input of AND(N+ 2), 292. Node 270 may be programmed to a logical "high" or "low" and is connected to a second input of AND(N+3), 290. Node 272 may be programmed to a logical "high" or"low" and is connected to a second input of ANDY), 288. Node 274 may be programmed to a logical "high" or "low" and is connected to a second input of AND(2N-3), 28C. Node 276 may be programmed to a logical "high" airflow" and is connected to a second input of s AND(2N-2), 284. Node 277 may be programmed to a logical "high" or "low" and is connected to a second input of AND(2N- 1), 282. Node 278 may be programmed to a logical "high" or "low and is connected to a second input of AND(2N), 280. The output, 211, of AND(N+1), 294, is electrically connected to a second input of XORI, 236. The output, 209, of AND(N+2), 292, is electrically connected to a second input lo of XOR2, 238. The output, 207, of AND(N+3), 290, is electrically connected to a second input of XOR3, 240. The output, 205, of AND(N+4), 288, is electrically connected to a second input of XOR4, 242. The output, 203, of AND(2N-3), 286, is electrically connected to a second input of XOR(N-3), 244. The output, 201, of AND(2N-2), 284, is electrically connected to a second input of XOR(N-2), 24C. The IS output, 298, of AND(2N-1), 282, is electrically connected to a second input of XOR(N-I), 248. The output, 296, of AND(2N), 280, is electrically connected to a second input of XOR(N), 250. The outputs of XOR(N) -XOR1, 250-236, form the indexed memory address, ID I, 2C252, respectively.
Other logic gates with programmable inputs may be used in place of the AND to gates, AND(2N)-AND(N+I), 280-294, used in Figure 2, to achieve a programmable hashing function.
The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other s alternative embodiments of the invention except insofar as limited by the prior art.

Claims (7)

  1. Claims 1) A circuit for programming a hashing function comprising: 2 a set
    of N AND gates, wherein each AND gate in said set of N AND gates has two inputs and one output; 4 a set of N XOR gates, wherein each XOR gate in said set of N XOR gates has two inputs and one output; 6 a N-bit hashing mask, wherein filch bit in said hashing mask is programmable; a 2N+X bit memory address; x wherein each bit from a first set of N bits from said 2N+X bit memory address is individually electrically connected to a Bust input of each AND gate respectively 0 from said set of N AND gates; wherein each bit of said N-bit hashing mask is individually electrically 12 connected to a second input of each ADD gate respectively from said set of N AND gates; l4 wherein each output of each AND gate from said set of N AND gates is individually electrically connected to a first input of each XOR gate respectively from 16 said set of N XOR gates; wherein each bit from a second set of N bits from said 2N+X memory address 8 is individually electrically connected to a second input of each XOR gate respectively from said set of N XOR gates.
  2. 2) The circuit as in Claim I wherein said hashing mask is programmed using 2 EEPROMs.
  3. 3) The circuit as in Claim I wherein said hashing mask is programmed using 2 EPROMs.
  4. 4) The circuit as in Claim I wherein said hashing mask is programmed using 2 electrically blown fillies.
  5. 5) The circuit as in Claim I wherein said hashing mask is programmed using laser 2 blown fuses.
  6. 6)The circuit as in Claim I wherein said hashing mask is programmed using remote 2 diagnostic registers.
  7. 7) The circuit in Claim 1 wherein said AND gates and said XOR gates are designed using static CMOS.
    8)Thc circuit in Claim 1 wherein said AND gates and said XOR gates are designed 2 using dynamic CMOS.
GB0512314A 2002-04-15 2003-04-03 A programmable microprocessor cache index hashing function Expired - Fee Related GB2412987B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/123,755 US6804768B2 (en) 2002-04-15 2002-04-15 Programmable microprocessor cache index hashing function
GB0307750A GB2389933B (en) 2002-04-15 2003-04-03 A programmable microprocessor cache index hashing function

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GB0512314D0 GB0512314D0 (en) 2005-07-27
GB2412987A true GB2412987A (en) 2005-10-12
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008008147A2 (en) * 2006-07-12 2008-01-17 Hewlett-Packard Development Company, L.P. Address masking between users
WO2013104875A1 (en) * 2012-01-13 2013-07-18 Commissariat à l'énergie atomique et aux énergies alternatives System and method for managing correspondence between a cache memory and a main memory
EP2709017A1 (en) * 2012-09-14 2014-03-19 Barcelona Supercomputing Center-Centro Nacional de Supercomputación Device for controlling the access to a cache structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2240413A (en) * 1990-01-25 1991-07-31 Int Computers Ltd Hashing of data
US20020032551A1 (en) * 2000-08-07 2002-03-14 Jabari Zakiya Systems and methods for implementing hash algorithms

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2240413A (en) * 1990-01-25 1991-07-31 Int Computers Ltd Hashing of data
US20020032551A1 (en) * 2000-08-07 2002-03-14 Jabari Zakiya Systems and methods for implementing hash algorithms

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008008147A2 (en) * 2006-07-12 2008-01-17 Hewlett-Packard Development Company, L.P. Address masking between users
WO2008008147A3 (en) * 2006-07-12 2008-05-08 Hewlett Packard Development Co Address masking between users
US8819348B2 (en) 2006-07-12 2014-08-26 Hewlett-Packard Development Company, L.P. Address masking between users
WO2013104875A1 (en) * 2012-01-13 2013-07-18 Commissariat à l'énergie atomique et aux énergies alternatives System and method for managing correspondence between a cache memory and a main memory
FR2985825A1 (en) * 2012-01-13 2013-07-19 Commissariat Energie Atomique SYSTEM AND METHOD FOR CORRESPONDENCE MANAGEMENT BETWEEN A CACHE MEMORY AND A MAIN MEMORY
US9330006B2 (en) 2012-01-13 2016-05-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives System and method for managing correspondence between a cache memory and a main memory
EP2709017A1 (en) * 2012-09-14 2014-03-19 Barcelona Supercomputing Center-Centro Nacional de Supercomputación Device for controlling the access to a cache structure
US9396119B2 (en) 2012-09-14 2016-07-19 Barcelona Supercomputing Center Device for controlling the access to a cache structure

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GB0512314D0 (en) 2005-07-27

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Effective date: 20090403