GB2411326A

GB2411326A - Viterbi decoder with single wrong turn correction using path discriminant values

Info

Publication number: GB2411326A
Application number: GB0403734A
Authority: GB
Inventors: Laolu Lijofi
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2004-02-19
Filing date: 2004-02-19
Publication date: 2005-08-24
Anticipated expiration: 2024-02-19
Also published as: GB0403734D0; GB2411326B

Abstract

A Viterbi decoder computes and stores path discriminant values relating to the trellis nodes to enable application of single wrong turn corrections following detection of errors in a block or data resulting from the identification of the initial maximum likelihood path. Specifically: a sequence of symbols received at the decoder are decoded to produce a most likely path through the decoder; the decoded sequence produced from the most likely path is checked to see if it passes a quality check (e.g. using a cyclic redundancy check (CRC)); if the sequence fails the quality check, the best direct descendant of the most likely path is obtained by deviating from the maximum likelihood path at the node having the minimum path discriminant (the discriminant being indicative of the reliability of the path choice made at that node). The decoded sequence produced from the best direct descendant of the most likely path is then checked to see if it passes the quality check, and the process is repeated using the next L best direct descendant paths in turn until either a decoder sequence passes the quality check or all of the L descendant paths fail to produce a sequence passing the quality check.

Description

2411 326 Viterbi decoder with single wrong turn correction This invention

relates to digital communication systems and in particular it relates to maximum likelihood sequence or Viterbi decoders.

The Viterbi algorithm has general application in communication systems for equalization and convolutional decoding. Block coding such as cyclic redundancy code (CRC) may be used to detect the incidence of an error within a block (frame) of data at the receiver.

A frame of data output from a Viterbi decoder is checked for errors by means of the CRC and if no errors are detected then the frame of data is accepted. When errors are detected by the CRC check then various methods may be employed in attempting to reclaim the correct symbol sequence from the parameters stored in relation to the nodes of the Viterbi trellis. The parameters normally stored are path metric and branch metric.

One method is to supplement the most likely path (or maximum likelihood path) traced along the trellis of the Viterbi with a secondary path, a tertiary path et seq., all to be checked via CRC to find an error free sequence.

These so-called list Viterbi decoders provide improved performance but require a significant increase in processing.

The patent application EP 1 056 212 proposes a method for obtaining the performance of a list Viterbi decoder without incurring the usual processing penalty. The method proposed in EP 1 056 212 uses single wrong turn correction when a frame error is detected in respect of the decoding of the maximum likelihood path. In a further traceback, a time instance in the trellis, along the maximum likelihood path, is chosen arbitrarily at which the losing state is taken rather than the winning state (as was chosen for the maximum likelihood path). If this second decoding does not give rise to any errors then it is accepted as correct otherwise a wrong turn is assumed at a different time instance of the trellis in a further traceback, a losing state is again taken rather than the winning state at this time instance and subsequent error check of the frame is carried out. This process continues until a traceback yields a path for which no errors are detected.

This invention provides a Viterbi decoder in which additional data relating to the trellis nodes are computed and stored to enable application of single wrong turn corrections following detection of errors in a block of data resulting from the identification of the initial maximum likelihood path.

The additional data relating to the trellis nodes are the path discriminant (see below). This data can be computed and stored either: for every node at the time the initial data of the trellis is computed to determine the maximum likelihood path (see example 1 below); or for selected nodes/states identified after the maximum likelihood path has been determined (see

example 2 below).

A f rst application of single wrong turn correction in the preferred sequence is to correct the maximum likelihood path at the node for which the minimum path discriminant value is stored.

Subsequent applications of single wrong turn corrections in the preferred sequence are sequentially to correct the maximum likelihood path at the node associated with the lowest value of path discriminant not previously considered.

Some examples of the invention will now be described.

The wrong turn correction Viterbi decoder (WTC Viterbi) in these examples is for use in an adaptive multi rate GSM speech channel in the receiver of a portable wireless communications terminal.

In this first embodiment, Example 1, the WTC Viterbi decoder of this invention operates in a fashion similar to the standard Viterbi decoder. In addition to computing branch and path metrics of the standard maximum likelihood decoder, however, it computes the difference between metrics of the different paths arriving at a node. This difference which we shall term the 'path discriminant" ( PD) is a measure of the Euclidean distance in signal space between the paths. As a general rule, the greater the absolute value of the path discriminant at any node, the greater the distinction between the paths (arriving at that node) and thus the higher the probability that the path decisions leading to that node are correct.

The parameters normally stored in relation to each node are path metric and branch metric. In accordance with this invention the following parameters are stored in addition at the same time the path metric and branch metric are calculated and stored; the path discriminant between the paths leading to the node at every node (for each time instance and for each state).

Received frames of data are at first decoded in accordance with standard techniques whereby computation of branch and path metrics establish a maximum likelihood path across a trellis. The sequence of decoded bits is then checked for errors by means of a cyclic redundancy check (CRC) or some other error criterion such as estimated number of bit errors per frame.

If no errors are detected then the decoding is assumed to have been successful and the sequence of decoded bits is accepted.

When the error check indicates an error then the decoding is assumed to have been unsuccessful and triggers an iteration of the decoding process.

In the first iteration, traceback starts from the specified terminating node in accordance with standard Viterbi operation. However, at the node on the traceback path with the minimum path discriminant the (symbol/bit) decision made for the most likely path of the first decode is toggled (reversed). For example if a '1' was decoded previously then the decision is changed to a 'O'. This toggling leads to a change in the subsequent traceback path.

The sequence of decoded bits obtained from this first iteration is subjected to an error check and if no errors are detected then the decoding from the first iteration is assumed successful.

If the error check after the first iteration indicates errors then a second iteration is needed. In the second iteration, toggling the symbol/bit decision along the traceback path does not occur where PD is minimum but occurs where the PD is smallest compared to all PDs on the traceback path for the first iteration except the minimum PD. (i.e. smallest but one PD value).

If the error check after the second iteration indicates errors then a further attempt at decoding by means of a third iteration may proceed, which if unsuccessful, is followed by a fourth iteration et seq. The WTC is applied, for a third iteration at the node associated with the PD value smallest but two, for the fourth iteration the node associated with the PD value smallest but three et seq.

It has been found that a satisfactory balance of performance and processing is obtained for this embodiment by limiting the number of WTC's to two.

Therefore when two iterations fail to deliver an error free output the original traceback of the maximum likelihood path is accepted and the data block passed to the next stage of the receiver.

The overall increase in processing load associated with implementation of the WTC Viterbi decoder of this invention is not significant since most of the additional processing required is in the traceback functionality. There is, however, a small additional memory storage requirement because the path discriminant at every state (or node) and every time instance of the trellis must be stored for this example.

Alternatively, for Example 2, the path discriminant at each time instance is stored but only for the state (node) on the maximum likelihood traceback path. This requires the calculation of the path discriminant for each node on the maximum likelihood traceback path after this path has been determined.

This leads to a slight reduction in the required memory for a small increase in the required processing.

A further reduction in the memory requirements for implementing the WTC Viterbi decoder at the expense of a small increase in processing can be realised by the following implementation applied in conjunction with either of the above examples. In this implementation a memory is used to record the minimum PD so far encountered along the path leading to each state.

This memory is updated at every time instance but only the minimum PD need be retained, not the value at each time instance.

At each node when the minimum PD is calculated, the minimum PD along the path leading to the node is stored. This is a process involving comparison of the PD at the current node with the stored minimum PD for the paths leading to this node and updating of this minimum PD accordingly. The time instance in the trellis where the minimum PD is updated is also stored when the stored value is updated. In other words, there is updated at each time instance, for every node of interest, the minimum PD and associated time instance of occurrence in the trellis along the path leading to that node.

If this implementation is applied to the second example above, the additional storage requirement is then limited in a TCH/AFS7.95 channel for example to 128 words of memory for one iteration of this algorithm.

Increasing the number of iterations increases the memory needed by a linear factor (for example two iterations need 256 words, since at every node we maintain the two smallest PD values along the path leading to the node).

The time instance associated with the stored minimum PD at the terminating node indicates where the wrong-turn correction (or toggling) is to be performed. Toggling is then performed as described previously.

Viterbi decoding with single-wrong-turn correction is illustrated for the two examples with the reduced-memory operation implemented below.

Example 1, let

k= code constraint length B= the number of bits in a frame R=2(k-l) xprev = "R x 1" array containing minimum path difference values.

Yprev = "R x 1" array containing time instance (or stage) in the trellis where the minimum path difference values in xprev are obtained.

xcurr = "R x 1" array containing current minimum path difference values.

Ycrr = "R x 1" array containing time instance (or stage) in the trellis where the minimum path difference values in xcurr are obtained.

The operation ofthis method (in the simplest form) is described as follows: 1. Initialise all elements of xprev, Yprev, xcurr and Yc.,rr to infinity.

2. Let i = 0 be the 1 st stage of the trellis 3. Compute the Euclidean distance between the paths arriving at every node in the ith stage of the trellis.

. Let node 'j' be the direct ancestor of node 'k' (i.e. the node of the (i-1)th stage that lies on the maximum-likelihood path to node 'k' ofthe ith stage).

Compare Euclidean distance at node 'k' of the ith stage (Ek) with the jth element of Xprev i e Xprevi) If E k < Xprev(j)' Xcurr (k) = E k; Ycurr(k) = i; . Else Xcurr (k)= xprevll) Ycurr(k) = YprevO) 4. Repeat (3) for all nodes in the ith stage.

5. Replace xprev with xcurr Replace Ypre, with Ycurr 6. Increment i(i.e. i= i+1) 7. Return to (3) until whole trellis is built S. Perform traceback to decode frame.

9. Check (via CRC or their frame quality metrics) if there are any errors. If no error, go to (11). If errors exist, do the following lO.Let p be the terminating node where traceback starts and h=Yc,rrO.

Perform traceback as usual but when the hth stage is reached jump to the losing state (or toggle the bit decision in the original traceback) and continue traceback to get decoded frame.

1 l.The decoded frame is obtained.

(This illustrations only considers one iteration.)

Example 2

A simpler method (and equivalent) is described below: 1. lnitialise variables xcurr and Ycurr to infinity.

2. Build the trellis and perform traceback as usual. Let D bits be the array of decoded bits.

3. Check (via CRC or their frame quality metrics) if there are any errors. If no error, go to (9). If errors exist, do the following 4. Rebuild the trellis. Let i = 0 be the 1 st stage of the trellis 5. Compute the Euclidean distance between the paths arriving at the node on the maximum likelihood traceback path in the ith stage of the trellis. (i.e. compute Euclidean distance at only one node per time instance) . Let node 'j' be the direct ancestor of node 'k' (i.e. the node of the (i-1)th stage that lies on the maximum-likelihood path to node 'k' ofthe ith stage).

Compare Euclidean distance at node 'k' of the ith stage (Ek) with

X CIIIT

. If Ek < xcurr X CUrT E k; Y curr = i; 6. Increment i(i.e. i= i+l) 7. Return to (5) until whole trellis is built 8. Let h=ycurr. Perform traceback as usual but when the hth stage is reached jump to the losing state (or toggle the bit decision in the original traceback) and continue traceback to get decoded frame.

9. The decoded frame is obtained.

The method defined above only specifies one-iteration of the algorithm.

Suppose for example that NT iterations are needed, the algorithm is specified as follows: Let XNT = "NT X 1" array containing minimum path difference values for each iteration-stage.

YNT = "NT X 1" array containing time instance (or stage) in the trellis where the minimum path difference values in xNT are obtained.

1. Initialise variables xNT and ye to infinity.

2. Build the trellis and perform traceback as usual. Let Db,s be the array of decoded bits.

3. Check (via CRC or their frame quality metrics) if there are any errors. if no error, go to (9). Tf errors exist, do the following 4. Rebuild the trellis. Let i = 0 be the 1St stage of the trellis 5. Compute the Euclidean distance between the paths arriving at the node on the traceback path in the ith stage of the trellis. (i.e. compute Euclidean distance at only one node per stage) Let node 'j' be the direct ancestor of node 'k' (i.e. the node of the (i-1)th stage that lies on the maximum-likelihood path to node 'k' ofthe iti. stage).

Compare Euclidean distance at node 'k' of the iti. stage (Ek) with X Err . Tf Ek < XNT (N) for w = NT: N+1 X T (W) X (W- 1); yNT (w) = yNT (W 1); end X r (N) = E k; y T (N) i; 6. Increment i (i.e. i = i + 1) 7. Return to (5) until whole trellis is built 8. Let h=ycurr. Perform traceback as usual but when the hth stage is reached jump to the losing state (or toggle the bit decision in the original traceback) and continue traceback to get decoded frame.

9. The decoded frame is obtained.

Claims

Claims 1. A method of decoding a received sequence of symbols using a

decoder comprising: a) decoding the received sequence of symbols to produce a most likely path through the decoder, b) checking whether the decoded sequence produced from the most likely path passes a quality check, c) if the sequence fails the quality check, obtaining the best direct descendant of the most likely path by deviating from the maximum likelihood path at the node having the minimum path discriminant, the discriminant being indicative of the reliability of the path choice made at that node, d) checking whether the decoded sequence produced from the best direct descendant of the most likely path passes the quality check, e) repeating step (d) using the next L best direct descendant paths in turn until either a decoder sequence passes the quality check or all of the L descendant paths fail to produce a sequence passing the quality check.
2. A method according to claim 1 in which each direct descendant of the most likely path is derived from a single wrong turn deviation from the most likely path.
3. A method according to claim 1 in which each next best direct descendant of the maximum path is derived by correcting the maximum likelihood path at the node associated with the lowest value of path discriminant not previously considered. 1&
4. A method as claimed in any of claims 1 to 3 including storing at least the minimum path discriminant so far encountered along the path leading to each state.
S. A method as claimed in any preceding claim including storing in relation to each path node of the most likely path the path discriminant between the paths leading to the node.
6. A method as claimed in any proceeding claim including storing in relation to all nodes of the decoder the path discriminant between paths leading to the node.
7. A method as claimed in any preceding claim in which the decoder is a Viterbi decoder.
8. A method as claimed in any preceding claim in which the path discriminant is a measure of the Euclidean distance in signal space between the different paths arriving at a node.
9. A decoder capable of decoding a received sequence of symbols using the method claimed in any preceding claim.