GB2410652A

GB2410652A - Timing control circuit and related method

Info

Publication number: GB2410652A
Application number: GB0401935A
Authority: GB
Inventors: Tony Banks
Original assignee: NEC Technologies UK Ltd
Current assignee: NEC Technologies UK Ltd
Priority date: 2004-01-29
Filing date: 2004-01-29
Publication date: 2005-08-03
Also published as: GB0401935D0

Abstract

The present invention provides for a timing and control circuitry comprising a system clock generator (36) associated with processing means (28) and arranged for receiving power from power supply means (30), a second clock arranged to operate at a clock frequency slower than that of the system clock (36), means (38) for selectively disabling the system clock so as to enter a power-saving mode in which the processing means (28) operates in accordance with the second clock, the circuit further being arranged with means (38) for decreasing power supplied by the said power supply means (30) for a period during which the system clock (36) is disabled. In a preferred embodiment, the processing means comprises baseband processing means of a mobile radio communications device.

Description

TIMING CONTROL CIRCUIT AND RELATED METHOD

The present invention relates to a timing and control circuit, and related method, and in particular to such a circuit and related method arranged for use with a mobile radio communications device such as a cellular phone.

In order to reduce power consumption within circuitry employing a timing control circuit and associated processing means, it is currently known to alter the clock frequency with which the circuit is controlled so as to reduce overall power consumption within the circuitry. Such alteration can be achieved by disabling the faster clock so as to remove the power consumption of that element.

A known arrangement is commonly used in mobile radio communication devices such as cellular phones in which two clocks, arranged to operate at different speeds, are employed. A system clock, running at the fast of the two speeds, is employed to control the circuitry during communication sessions, whereas a slower clock is controlled so as to replace the system clock when the device is not required for the communications system. The device can then enter a standby mode during which the slower, and less power- consuming, clock serves to maintain the operating timebase.

However, such known arrangements employing a standby mode nevertheless still exhibit unnecessarily high levels of power consumption particularly in view of leakage current within the processing means.

Thus, it has been found that the adoption of two different clocks as noted above can only have a limited effect on the reduction in power consumption. This therefore limits the degree to which battery lifetime can be extended.

The present invention seeks to provide for a timing control circuit arrangement and related method having advantages over known such circuitry and methods.

According to a first aspect of the present invention, there is provided timing and control circuitry comprising a first clock associated with processing means and arranged for receiving power from power supply means, a second clock arranged to operate at a clock frequency slower than that of the first clock, means for selectively disabling the first clock so as to enter a power saving mode in which the processing means operates in accordance with the second clock, the circuit further being arranged with means for decreasing power supplied by the said power supply means to the processing means for a period during which the first clock is disabled.

The present invention is therefore advantageous in reducing leakage current within the processing means, and therefore power consumption, both in view of the adoption of the slower clock, and also for example through switching to a reduced power supply voltage for periods when the slower clock is used in a standby mode.

As a particular advantage, the manner of controlling the switching between the two power supply values comprises, or is associated with, the currently existing control logic serving to switch between the two clocks.

In this manner, the advantages of the present invention can be readily achieved with the standby systems of currently available radio communication devices.

The reduction in power supplied to the processing means can advantageously be achieved by a reduction in the voltage supplied to the processing means which, in turn, can advantageously be provided by the control of a switch mode power supply.

The timing control circuit is advantageously provided within a mobile radio communications device, such as a cellular phone, and in which the processing means can comprise a digital processing means arranged to have the core voltage supplied thereto buried in accordance with the present invention.

Advantageously, the control arrangement provided for controlling the use of the second clock in favour of the first clock, is likewise arranged to control the decreasing power supplied by the said power supply means.

According to another aspect of the present invention, there is provided a mobile radio communications device including timing control circuit as defined above.

According to yet a further aspect of the present invention, there is provided a method of controlling timing in relation to processing means arranged for receiving power from power supply means, the method including disabling a first clock in favour of a second clock arranged to operate as a slower frequency than the first clock and further including the steps of reducing the power supplied to the processing means during the periods for which the first clock is disabled.

The method is advantageously used for controlling timing and power supply within a mobile radio communications device and in accordance with timing control circuitry as defined above.

The invention is described further hereinafter, by way of example only with reference to the accompanying drawings in which: Fig. 1 is a schematic block diagram of a power supply timing control circuitry associated with a cellular phone as currently available; and Fig. 2 is a similar schematic block diagram of the timing and power supply circuitry associated with a mobile phone and according to an embodiment of the present invention.

Turning first to Fig. 1, there is illustrated timing and power supply control circuitry of a mobile phone 10 having baseband core logic 12 arranged to receive a core voltage from a switch mode power supply 14 which in turn receives a battery voltage from a battery 16.

The baseband core logic 12 is arranged to operate in accordance with a system clock signal 18 received from a system clock generator 20 and which operates in accordance with a clock enable signal 22 delivered from a base band sleep-timing control logic circuitry 24. As an example, such a system clock generator can comprise a Temperature Compensated Voltage Controlled Crystal Oscillator (TCVCXO).

Such a known arrangement employs a technique referred to as Discontinuous Reception (DRX) whereby, in a standby mode, the mobile phone 10 is only required to monitor a paging channel during certain periods of time and as defined by the associated basestation of the network. During the remainder of the period, the handset is arranged to enter a low power mode operation during which time a slower clock, for example 32Khz clock (not shown), is used to maintain synchronism with the air interface. In this low power mode, commonly referred to as "a 32Khz sleep mode", the system clock is turned off and operation maintained on the basis of the 32Khz clock which leads to marked power saving due to the periodic disabling of the system clock.

Thus, with reference to Fig. 1, at times when the mobile phone 10 is required to enter into a low power mode of operation in which a 32Khz clock is to effectively replace the system clock 20, the clock enable signal 22 is removed by the base band sleep timing control logic 24 so as disable the system clock generator 20 in favour of the 32Khz clock. The 32Khz clock is left continuously enabled so as to maintain synchronization with the air interface during such periods.

However, in accordance with the present invention, it has been determined that when, for example, the baseband core logic 12 is operating with the 32Khz clock during such a standby mode, the voltage requirement of the baseband core logic 12 is also reduced compared with that required for full speed operation, i.e. when the system clock generator 20 is enabled. As an example, it is noted that a typical baseband core logic device may require 1.6V for full speed operation whereas the requirement is decreased to 1.2V when operating in accordance with the 32Khz clock signal.

The present invention makes advantageous use of this realization for example in reducing the voltage supplied to the baseband core logic 12 during the standby periods when the 32Khz clock has been enabled in favour of the system clock 20.

It should of course be noted that the baseband core logic must ensure that it has switched over to using the 32Khz clock before the system clock 20 is disabled and the core voltage is reduced.

Reference is now made to Fig. 2 which is a similar illustration to that of Fig. 1 of a cellular phone 26 having baseband core logic 28 arranged to receive a core voltage from a switch mode power supply 30 which itself receives a battery voltage from the cellular phone's battery 32.

A system clock signal 34 is again delivered to the baseband core logic 28 in accordance with a system clock generator 36.

The system clock generator 36 is again controlled by way of a clock enable signal 38 by means of a baseband sleep timing control logic 40.

However, in accordance with this illustrated embodiment of the present invention, the clock enable signal 38 is also delivered to the switch mode power supply 30 where it is employed as a control signal serving to switch the core voltage supplied to the baseband core logic 28.

In this illustrated embodiment of the present invention, the reduction in the core voltage supplied to the baseband core logic 28 advantageously serves to reduce leakage currents within the logic circuitry. This, in turn, advantageously reduces power consumption within the mobile phone 26 which can then advantageously be used to extend battery life and also achieve secondary advantages associated therewith, such as possible reductions in size and weight of the mobile device.

Within the illustrated embodiment or otherwise, power consumption can be further reduced by removing the power supply to the system clock generator at times when it is disabled.

The illustrated embodiment of the present invention is particularly advantageous in that it is arranged simply to employ the clock enable signal 36 already being generated by the baseband sleep timing control logic. This serves to ensure that the reduction in the core voltage to the baseband core logic 28 only occurs during the standby periods during which a system clock generator 34 is disabled in favour of, for example, the "32Khz sleep" clock.

As will be appreciated therefore, the arrangement and associated method of the present invention can advantageously be employed as required in association with any circuitry operating in a reduced-clock power saving mode and, in particular, in relation to mobile radio communication devices and in particular cellular phones.

The invention is equally applicable to both single mode and dual mode, second generation and third generation communication devices.

The leakage current is advantageously reduced since, once the system clock is disabled and the lower core voltage employed, it becomes possible to maintain the internal state of base band processing circuitry merely in accordance with the lower core voltage.

Claims

Claims 1. Timing and control circuitry comprising a first clock

associated with processing means and arranged for receiving power from power supply means, a second clock arranged to operate at a clock frequency slower than that of the first clock, means for selectively disabling the first clock so as to enter a power-saving mode in which the processing means operates in accordance with the second clock, the circuit further being arranged with means for decreasing power supplied by the said power supply means to the processing means for a period during which the first clock is disabled.
2. Circuitry as claimed in Claim 1, wherein the processing means comprises processing means of a mobile device.
3. Circuitry as claimed in Claim 2, whereby the mobile device comprises a mobile radio communications device.
4. Circuitry as claimed in Claim 3, wherein the processing means comprises baseband processing means.
5. Circuitry as claimed in any one or more of the proceeding claims, wherein the decrease in the power supplied is achieved through reduction in a supply voltage.
6. Circuitry as claimed in Claim 5, wherein the reduction in power supplied by the power supply means is achieved by reducing the core voltage supplied to the processing means.
Circuitry as claimed in any one or more of the preceding claims, and arranged to employ a common control signal for disabling the system clock and initiating the decrease in the power supplied to the processing means.
8. A mobile radio communications device including a timing control circuit as defined in any one or more of the preceding claims.
9. A method of controlling timing in relation to processing means arranged for receiving power from power supply means, the method including disabling a first clock in favour of a second clock arranged to operate as a slower frequency than the first clock and further including the steps of reducing the power supplied to the processing means during the periods for which the first clock is disabled.
10. A method as claimed in Claim 9, wherein the processing means comprises processing means of a mobile device.
11. A method as claimed in Claim 10, whereby the mobile device comprises a mobile radio communications device.
12. A method as claimed in Claim 11, wherein the processing means comprises a baseband processing means.
13. A method as claimed in any one or more of the proceeding claims, wherein the decrease in the power supplied is achieved through reduction in supply voltage.
14. A method as claimed in Claim 13, wherein the reduction in power supplied by the power supply means is achieved by reducing the core voltage supplied to the processing means.
15. A method as claimed in any one or more of Claims 9 to 14, and arranged to employ a common control signal for disabling the system clock and initiating the decrease in the power supplied.
16. A timing control circuit substantially as hereinbefore described with reference to, and as illustrated in, Fig. 2 of the accompanying drawings.
17. A method of controlling timing substantially as hereinbefore described with reference to Fig. 2 of the accompanying drawings.