GB2409118A

GB2409118A - A sigma delta modulator utilizing feedback loop and logic circuit

Info

Publication number: GB2409118A
Application number: GB0326172A
Authority: GB
Inventors: Morgan James Colmer
Original assignee: Global Silicon Ltd
Current assignee: Global Silicon Ltd
Priority date: 2003-11-10
Filing date: 2003-11-10
Publication date: 2005-06-15
Anticipated expiration: 2023-11-10
Also published as: GB0326172D0; GB2409118B

Abstract

A sigma-delta modulator for forming a digital output signal representative of the magnitude of an analogue input signal, the modulator comprising: a summation unit for summing the analogue input signal with an adjustment signal to form a summation output signal; an integrator 1 arranged to receive the summation output signal and form an integrator output signal dependent thereon; a quantiser 2 arranged to receive the integrator output signal and form the digital output signal dependent thereon; and a feedback loop for generating the adjustment signal and comprising a logic circuit arranged to select between one of two predetermined values for the adjustment signal, the selection being performed in dependence on both the digital output signal and a control signal. The logic circuit may comprise an XOR gate. The sigma-delta modulator may be utilized in a digital media player.

Description

240911 8

A SIGMA-DELTA MODULATOR

The present invention relates to a sigma-delta modulator having a gain function and an offset function, both of which are implemented using a feedback loop and a logic circuit.

Sigma-delta modulators are used for analogue to digital conversion. Sigmadelta modulators offer high resolution, high integration and low cost, making them an ideal choice for many applications where analogue to digital conversion is required.

The operation of a sigma-delta modulator is best described using the simplest 1-bit implementation. A typical 1-bit sigma-delta modulator is illustrated in figure 1.

In the basic implementation illustrated in figure 1, the sigma-delta modulator comprises a summation unit (1), an integrator (2), a comparator (3) and a digital-to- analogue converter (DAC) (4). The summation unit may be, for example, a difference amplifier. The comparator may be an analogue-to-digital converter (ADC).

As can be seen in figure 1, the components of the modulator are connected in a feedback loop. The analogue input signal is fed into the summation unit, where a feedback signal is subtracted, before being fed into a loop filter, which in this case is an integrator. The signal output from the integrator is compared with a reference signal in the comparator. If the output signal from the integrator is greater than the reference signal, a 'one' is output, and if the integrator output signal is less than the reference signal, a 'zero' is output. Thus the analogue input signal has been converted into a digital output signal.

The digital output signal is fed back, via the DAC, to the summation unit, where it is subtracted from the input signal. The purpose of the feedback signal is to maintain the average output of the integrator near the comparator's reference level by making the ones and zeros of the digital output signal representative of the analogue input.

The DAC in the feedback loop has an upper reference voltage and a lower reference voltage. When the comparator outputs a 'one', the DAC outputs a signal at the upper voltage and when the comparator outputs a 'zero', the DAC outputs a signal at the lower voltage. The modulator is at full-range scale when the input signal is equal to the upper or lower reference voltages of the feedback DAC. For example, if the feedback DAC outputs -2. 5V when it receives a zero and 2.5V when it receives a one then the range of the input is i2.5V. The reference voltage of the comparator is halfway between the upper and lower boundaries of the input range, e.g. for an input range of i2.5V the reference voltage for the comparator would be 0V. The reference voltage for the comparator represents the virtual ground level for the modulator.

Obviously, for modulators having an input range that is symmetrical about zero, the virtual ground level will always be zero.

The output from the sigma-delta modulator is a stream of ones and zeros. The ratio of ones to zeros represents the magnitude of the input signal compared with the input range of the modulator. For example, if the range of the modulator is i2.5V and the input signal has a magnitude of 1.0V, then the input signal is 3.5V above the lower boundary of a 5V range. In this example, 70% of the output signal should consist of ones. For the modulator to produce a digital output signal that is an accurate representation of the analogue input signal, the modulator must sample at a much greater rate than the rate of change of the analogue input signal.

More sophisticated sigma-delta modulators than the 1-bit modulator described above may have multiple modulators and integrators.

A sigma-delta modulator offers improved noise performance over traditional ADCs.

This is achieved through oversampling, noise shaping, digital filtering and decimation.

A traditional multi-bit ADC converts an analogue signal into a digital signal by sampling the input signal at regularly spaced intervals in time and classifying the magnitude of the input signal as being one of a number of equally spaced, predetermined magnitudes. The simplest 1-bit ADC classifies the input signal according to two predetermined magnitude levels and the outputs either a one or a zero according to which of the two levels the input signal is closest to. Likewise, a 2- bit ADC classifies the input signal according to four predetermined levels and outputs either 00, 01, 10 or 11 during each sampling period and so on. The greater the number of magnitude levels to which the input signal is compared, the greater the resolution of the converter. By according the input signal one of an equally spaced number of values the output of the ADC is inherently inaccurate. This is because the ADC input is a continuous signal with an infinite number of possible states while the output signal is a discrete function whose number of different states is determined by the converter's resolution. The conversion from analogue to digital loses some information and introduces distortion into the signal. The magnitude of this error is random, with values up to +LSB (the least significant bit of the digital output).

A typical graph that would be obtained from an FFT analysis of the output signal from a traditional multi-bit ADC with a sine-wave input signal is illustrated in figure 2a. Fs is the sampling frequency of the input signal, which must be at least twice the bandwidth of the input signal according to Nyquist theory. The FFT analysis breaks down the signal into its frequency components. The sine-wave is clearly visible as a large spike at a single frequency. However, lots of random noise is also visible extending from DC to Fs/2. This noise is a result of the distortion discussed above and is known as quantisation noise.

The signal-to-noise ratio (SNR) is obtained by dividing the signal amplitude by the RMS sum of all the frequencies representing noise. In a conventional ADC the SNR can only be improved by increasing the resolution i.e. the number of bits.

If the sampling frequency is increased by the oversampling ratio k, to kFs, the noise floor drops. This is illustrated in figure 2b. The SNR is unchanged from the situation in figure 2a, but the noise has been spread over a wider frequency range. Sigma- delta converters are able to exploit this effect by following the 1-bit ADC with a digital filter. The effect of the filter is illustrated in figure 2c. The RMS noise is less, because most of the noise passes through the digital filter. This action allows sigma-delta modulators to achieve a wide dynamic range from a low-resolution ADC.

However, the sigma-delta modulator cannot achieve a high resolution from oversampling alone as the oversampling ratio required for even a reasonable resolution is generally too high to be realizable. The sigmadelta modulator also shapes noise away from the peak gain response of the modulator.

In the modulator illustrated in figure 1, the loop filter is an integrator, so the modulator shapes noise out of the lower frequencies and into the higher frequencies. This is because the integrator sums the error voltage, thereby acting as a lowpass filter to the input signal and a high pass filter to the quantisation noise. Thus, most of the quantisation noise is pushed into higher frequencies (see figure 3a). Oversampling has not changed the total noise power, but its distribution.

For higher order sigma-delta modulators, noise shaping can be achieved by including more than one stage of integration and summation.

If a digital filter is applied to the noise-shaped output of the sigmadelta modulator, as illustrated in figure 3b, it removes more noise than does oversampling alone.

The output of the sigma-delta modulator is a stream of ones and zeros at the sampling rate. This data rate is usually very high, so a digital-anddecimation filter can be used to reduce the data rate to a more useful value. No useful information is lost during this process, as illustrated in figure 5. As the bandwidth of the signal is reduced by the digital output filter, the output data rate can satisfy the Nyquist criterion even though it is lower that the original sampling rate. This can be accomplished by preserving certain input values and discarding the rest. This process is known by decimation by a factor M (the decimation ratio). M can have any integer value, provided that the output data rate is more than twice the signal bandwidth. If the input has been sampled at Fs, the filtered-output data rate can be reduced to Fs/M without loss of information. The complete system, as described, above is illustrated in figure 4.

Of course, the best possible resolution of a modulator is only achieved when the input signal varies in amplitude such that the variations cover nearly the whole of the input range. Also, the sigma-delta modulator as described above and illustrated in figure 1 can be considered as a closedloop control system. Within a closed-loop control system, the loop can only be as accurate as the feedback signal. Therefore, it would improve the dynamic range of the modulator if input signals that do not utilise the available input range could be amplified. Further, it is desirable that the amplification, or gain, can be controlled, so that the modulator can accept different signals having variable input ranges.

In one application, sigma-delta modulators are used in CD-players. CDs vary in their reflectivity; for example, CD-RW discs have a reflectivity that is about 4 times less than CD-R discs or pressed discs. Traditionally, this variation in reflectivity is accounted for by using a single gain switch option in the analogue amplifiers before the modulator. It would be useful to have a simple method and apparatus for applying variable gain to the input signal. Also, as reflectivity also varies over the radius of a disc, there is a need for a gain that can vary adaptively.

The signals processed by a CD player from reading CDs often have a bias or offset.

Therefore, there is a need for removing/applying an offset to input signals.

According to one aspect of the present invention there is provided a sigma-delta modulator for forming a digital output signal representative of the magnitude of an analogue input signal, the modulator comprising: a summation unit for summing the analogue input signal with an adjustment signal to form a summation output signal; an integrator arranged to receive the summation output signal and form an integrator output signal dependent thereon; a quantiser arranged to receive the integrator output signal and form the digital output signal dependent thereon; and a feedback loop for generating the adjustment signal and comprising a logic circuit arranged to select between one of two predetermined values for the adjustment signal, the selection being performed in dependence on both the digital output signal and a control signal.

Preferably the one of the predetermined values has a relatively low value. That relatively low value is preferably equal to the lower boundary of the allowable range for the analogue input signal. Preferably the other of the predetermined values has a relatively high value. Preferably that relatively high value is equal to the upper boundary for the allowable range of the input signal.

Preferably the modulator is arranged such that the digital output signal is representative of the magnitude of the analogue input signal when the analogue input signal is contained within the upper and lower boundaries of a quantisation range.

Conveniently the upper boundary of the quantisation range is less than or equal to the upper boundary of the allowable input range. Conveniently the lower boundary of the quantisation range is greater than or equal to the lower boundary of the allowable input range.

Preferably the lower boundary of the quantisation range is the average magnitude of the adjustment signal when the analogue input signal has the relatively low value.

Preferably the upper boundary of the quantisation range is the average magnitude of the adjustment signal when the analogue input signal has the relatively high value.

Conveniently the digital output signal is formed by the quantiser as a signal alternating between two voltage levels.

The control signal is suitably generated by a control unit.

The control unit may generate the control signal so as to cause effective amplification of the input signal by the sigma-delta modulator.

The control unit preferably generates the control signal so as to cause effective offset of the input signal by the sigma-delta modulator. Alternatively or in addition the control unit may generate the control signal so as to control the degree to which the adjustment signal follows the digital output signal. Alternatively or in addition the control unit may generate the control signal such that selected portions of the digital output signal are replaced with transition-cycles.

The control unit is suitably operable to increase the gain of the modulator by replacing an increased proportion of the digital output signal with transition-cycles.

The control unit is suitably operable to either increase or decrease the average magnitude of the adjustment signal by replacing selected portions of the digital output signal with transition-cycles, thereby changing the upper and lower boundaries of the quantisation range.

The control unit preferably generates the control signal in dependence on the digital output signal.

The control unit is preferably operable to introduce an offset by generating the control signal so as to replace a greater or lesser proportion of the digital output signal having the relatively high value.

Preferably the quantiser receives a first clock signal having a first frequency, such that transitions in the digital output signal can occur at intervals of a first time period.

Preferably the logic circuit receives a second clock signal having a second frequency, such that transitions in the adjustment signal can occur at intervals of a second time period.

The second frequency is preferably greater than or equal to the first frequency.

A transition-cycle suitably takes the relatively high value for some of the duration of the transition-cycle and takes the relatively low value for the remainder of the transition-cycle.

The net average value of a transition-cycle is conveniently equal to the virtual ground value for the modulator. The virtual ground value of the modulator is preferably mid- way between the relatively high value and the relatively low value.

The control signal may be a non return-to-zero signal. Alternatively, it could be a return-to-zero signal.

The logic circuit is preferably an exclusive OR means, most preferably a gate, arranged to receive the digital output signal and the control signal and generate an output dependent thereon.

The control unit may be implemented in software and/or hardware. Such hardware may be analogue and/or digital hardware.

According to a second aspect of the invention there is provided a digital media player comprising a detection device for detecting digital data and having a sigma-delta modulator for receiving an analogue input signal and forming a digital output signal representative of the magnitude of the analogue input signal, the modulator comprising: a summation unit for summing the analogue input signal with an adjustment signal to form a summation output signal; an integrator arranged to receive the summation output signal and form an integrator output signal dependent thereon; a quantifier arranged to receive the integrator output signal and form the digital output signal dependent thereon; and a feedback loop for generating the adjustment signal and comprising a logic circuit arranged to select between one of two predetermined values for the adjustment signal, the selection being performed in dependence on both the digital output signal and a control signal.

The digital media player preferably comprises a control unit arranged to generate the control signal.

The control unit is preferably arranged to select a predetermined control signal dependent on the type of digital data detected by the detection device.

The control unit is preferably arranged to receive information from the detection device, said information being dependent on the digital data detected by the detection device, and for generating a control signal thereon.

The player is preferably arranged for playing optical discs and the detection device is arranged to detect the content of an optical disc and generate the input signal in dependence thereon.

According to a third aspect of the invention there is provided a method for forming a digital output signal representative of the magnitude of an analogue input signal by means of a sigma-delta modulator, the method comprising the steps of: for summing the analogue input signal with an adjustment signal by means of a summation unit to form a summation output signal; receiving the summation output signal in an integrator, which is arranged to form an integrator output signal dependent thereon; receiving the integrator output signal in a quantiser, which is arranged to form the digital output signal dependent thereon; and generating the adjustment signal by selecting between one of two predetermined values for the adjustment signal by means a feedback loop; the feedback loop comprising a logic circuit arranged to perform the selection in dependence on both the digital output signal and a control signal.

For a better understanding of the present invention, reference is made by way of example to the following drawings, in which: Figure 1 shows a sigma-delta modulator according to the prior art.

Figures 2a-c show the effect of oversampling and digital filtering on the output noise level of an ADC.

Figures 3a-b show the effect of noise shaping on the output noise level of an ADC.

Figure 4 shows an overview of the stages involved in reducing noise levels in the output signal.

Figure 5 shows the effects of decimation on noise reduction.

Figures 6a-b show two possibilities for improving the resolution of the sigma-delta modulator.

Figure 7 shows a sigma-delta modulator according to an embodiment of the invention.

Figures 8a-d show waveforms for implementing a gain function in a sigmadelta modulator.

Figures 9a-c show waveforms for implementing a gain function in a sigmadelta modulator.

Figure 10 shows a sigma-delta modulator according to a general embodiment of the invention.

As described above, the sigma-delta modulator offers best resolution when the input signal varies between the upper and lower limits of the modulator's input range. The input range is determined by the amplitude of the DAC feedback signals. Although one option for improving the resolution of the modulator is to amplify the incoming signals so that they cover the input range of the modulator (figure 6a), a second option is to vary the input range of the modulator to suit the incoming signal (figure fib). This is employed by the present invention. Rather than amplifying a signal via an amplification stage prior to the sigma-delta modulator, the present invention seeks to change the amplitude of the feedback signals.

The output of the 1-bit DAC in the feedback path of a sigma-delta modulator varies between an upper and a lower limit according to whether the digital output signal is a one or a zero. The upper and lower limits can be considered as +Vcc/2 about the virtual ground level of the modulator (i.e. the modulator has an input range of Vcc). If these limits could be changed dependent on the incoming signal, for example to Vcc/4, for an input range of Vcc/2, then the modulator would have an increased implied gain: of 2 in this example. However, this is not generally an economically viable approach.

The present invention implements a gain function in a sigma-delta modulator by introducing transition-cycles into the feedback path. Transition-cycles have a net average value equal to the virtual ground level of the modulator.

By introducing more transition-cycles into the feedback path the overall average level of the feedback is reduced.

Figure 7 illustrates a sigma-delta modulator according to an embodiment of the present invention. The loop filter (1) is an integrator circuit, the quantifier is a latch (2) and the feedback DAC has been replaced by an exclusive-OR gate (an XOR gate).

The XOR gate has as its inputs the digital feedback signal and a control signal.

Waveform A of figure 8 shows a typical feedback signal for an input that is at the virtual ground level. In figure 8, the virtual ground level has been set at '/Vcc. The signal has a 50% duty cycle, i.e. half the cycles take the upper limit of Vcc and half the lower limit of 0V. The signal therefore represents an input having a magnitude that is midway between the upper and lower limits of the input range of the modulator i.e. ,/Vcc in this case.

Waveform B of figure 8 illustrates an equivalent feedback signal including transition- cycles. Waveform A, which is a non-return-to-zero or NRZ waveform, has been converted to a return-to-zero (RTZ) waveform. As can be seen from the figure, the transition-cycles have a net average value of'/Vcc (virtual ground).

Waveform B illustrated in figure 8 is difficult to directly synthesise. However, since the requirement for the transition-cycles is only that their net average value is equal to the virtual ground level, waveform C in figure 8 will have the same effect on the overall feedback level seen by the integrator as waveform B. In waveform C the transition-cycles have, in effect, been implemented as a pair of pulses, having an average value of '/Vcc.

Waveform C can be easily generated from waveform A by using an XOR gate with waveform D (also illustrated in figure 8). Therefore, in the sigmadelta modulator shown in figure 7, the digital output signal (waveform A) and the control signal (waveform D) are input into an XOR gate to create the feedback signal (waveform C).

Note that the feedback signal still has a 50% duty cycle so the modulator is still balanced with an input of '/Vcc. In other words, for an input signal at virtual ground, the situation is unchanged by the introduction of transition-cycles into the feedback signal.

Waveforms A, B and C of figure 9 are similar waveforms for the situation where the modulator has a full scale positive input (Vcc). The digital output signal of the modulator is waveform A. As the input is at the upper limit, the output signal is always high (100% ones). If the same control signal (waveform C) were applied to the XOR gate along with the digital output signal, then the feedback waveform B is generated.

This time, the feedback signal has a net DC content of 3/4VCC. Therefore, an input of 3/4VCC would be balanced by this feedback signal and the upper input limit to the modulator has been reduced by 1/.Vcc.

Similarly, if the input to the modulator has a full scale negative input (0V), the same control signal would produce a feedback signal having a net DC content of %Vcc.

Therefore, an input of '/4Vcc would be balanced by this feedback signal and the upper input limit to the modulator has been increased by '/.Vcc.

Therefore, overall, the waveform D of figure 8 and waveform C of figure 9 have managed to decrease the input range of the modulator from Vcc to '/Vcc. The modulator has an implied gain of two. By reducing the input range into the modulator by half, the control signal has effectively achieved the same result as an amplification by a factor of two prior to the sigma-delta modulator.

The control and feedback signals should preferably have a higher frequency than the digital output signal. To achieve this the XOR gate and the quantiser can receive different clock signals.

According to another embodiment of the invention, the control signal can be used to apply an offset. This can be achieved using the same basic circuit as illustrated in figure 7. In this application, the control signal is arranged such that transition-cycles are injected into the feedback signal in an asymmetric manner. Replacing more ones' than 'zeros' in the output signal, causes the generated feedback signal to apply a negative offset to the input signal. This is because the net DC content of the feedback signal is decreased relative to the situation where the same number of transition-cycles is inserted into the feedback signal, but in a symmetric manner.

Similarly, by replacing more 'zeros' than 'ones', a negative offset can be applied.

The ability to bias the net DC feedback signal in one direction is particularly useful in situations where the input signals have an undesirable offset. For example, in CD players, the ability to remove offsets from the input signals improves the quality of optical feedback signals.

Analogue methods of implementing variable gain and offset can be very complicated.

By implementing the gain and offset in the digital domain the present invention provides a simple and effective method for implementing variable gain and offset control in a sigma-delta modulator. In effect, the XOR gate can be seen as a programmable amplifier.

The control signal can be of a predetermined form that is arranged for a particular input. For example, in CD players, an appropriate, predetermined control signal may be selected according to the type of CD being played.

The control signal may be generated by a control unit.

The control unit can have analogue, digital or software implementations.

The control signal may be adaptive. For example, in CD players the control signal could be altered during operation to account for reflective variation over the radius of the disc.

The system may, using the principles set out above, apply both effective gain and effective offset to the input signal.

According to one embodiment, monitoring apparatus may be provided to monitor the conditions related to the input signal. For example, in the application of a CD player the monitoring apparatus may be arranged to monitor any reflective variations in the surface of the CD. The monitoring apparatus may be arranged to communicate with the control unit to allow adaptive control of the gain and/or offset functions. The communication between the monitoring apparatus and the control unit may take the form of a control signal. The communication between the monitoring apparatus and the control unit may take the form of monitoring information.

An adaptive control signal may be combined with an external control signal. The external control signal may have a predetermined form. For example, it might be desirable to apply a predetermined gain automatically to signals read from CDs of a particular type (e.g. CDs that have a low reflectivity). Therefore, predetermined control signals could be stored for use by the sigma-delta modulator when processing signals coming from a particular source.

The XOR gate may be under the control of a special logic unit within a chip.

Figure 10 illustrates a general embodiment of the present invention according to the above considerations.

As the method of the present invention requires removing some of the spectral noise shaping information from the feedback signal, there will inevitably be a reduction in the SNR that is achievable by the modulator. For example, in the situation where the control signal is of the form of waveform D of figure 8 and waveform C of figure 9 we have the situation where a quarter of the signal being fed back into the modulator is replaced with transition-cycles. In other words, only 75% of the feedback signal comprises noise shaping content while the remaining 25% comprises gain scaling (and offset) content. Therefore, for a gain of 6dB (a factor of 2), the SNR degradation is 2.5dB (a factor of approximately 1.3).

At first glance, the degradation of the SNR appears problematic. However, when the overall theoretical limit of the SNR of the first order modulatoris considered, we obtain a maximum SNR of 67dB for the highest frequency output the decimator can distinguish (22.05kHz with an output sample rate from the decimator of 44.1kHz).

The SNR of a first order sigma-delta modulator can be found with the following relationship for a noise transfer function: rms 3 [ is (1) n = e. [ 2 fo] (2) This is only the SNR of the modulator and assumes that the decimator has a perfect brick-wall filter response. As can be seen, the SNR capabilities of the modulator far outperform the decimator, which can only resolve to 8 bits, or 48dB, therefore losing 2.5dB of SNR for each 6dB of gain applied to the modulator is no great loss.

The situation in reality is not as simple as first indicated, the loss in SNR in the modulator might actually be lower than if the gain was performed in the analogue domain. If the signal were amplified with an operational amplifier then the signals would indeed be boosted by 6dB, but the noise floor would also be increased by a lower margin. From noise theory we know that noise in amplifiers increases according to the following relationship: n = , (3) In this case we get a 3dB increase in the level of the noise floor for each 6dB increase in gain. This makes the alternative 2.5dB reduction in SNR for putting the gain within the sigma-delta modulator look very favourable.

Although the present invention has been described in association with applications specifically involving CD players, it should be understood that the present invention is not limited to any specific application can be incorporated into any application requiring an ADC.

The principle of the present invention can be applied to any kind of sigma-delta modulator, for example, analogue, digital or switched capacitor. The description of the present invention has been limited to sigma-delta modulators having a loop filter that is an integrator, resulting in a low-pass sigma-delta modulator. However, in reality, the integrator could be replaced with any loop shaping element, thereby allowing for low-pass, band-pass or high-pass modulators, either analogue or digital.

Although the quantiser has been shown as a two-level type, it could have any number of levels. The method according to the present invention is applicable to any order of modulator. It should be understood that the first-order sigma-delta modulator as described above is only an example, and that the principle of the invention remains the same for other modulators.

The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

cowed 1 8 1. A sigma-delta modulator for forming a digital output signal

representative of the magnitude of an analogue input signal, the modulator comprising: a summation unit for summing the analogue input signal with an adjustment signal to form a summation output signal; an integrator arranged to receive the summation output signal and form an integrator output signal dependent thereon; a quantiser arranged to receive the integrator output signal and form the digital output signal dependent thereon; and a feedback loop for generating the adjustment signal and comprising a logic circuit arranged to select between one of two predetermined values for the adjustment signal, the selection being performed in dependence on both the digital output signal and a control signal.
2. A sigma-delta modulator as claimed in claim 1, wherein the one of the predetermined values has a relatively low value, which is equal to the lower boundary of the allowable range for the analogue input signal, and the other of the predetermined values has a relatively high value, which is equal to the upper boundary for the allowable range of the input signal.
3. A sigma-delta modulator as claimed in any preceding claim, wherein the modulator is arranged such that the digital output signal is representative of the magnitude of the analogue input signal when the analogue input signal is contained within the upper and lower boundaries of a quantisation range, such that the upper boundary of the quantisation range is less than or equal to the upper boundary of the allowable input range and the lower boundary of the quantisation range is greater than or equal to the lower boundary of the allowable input range.
4. A sigma-delta modulator as claimed in any preceding claim, wherein the lower boundary of the quantisation range is the average magnitude of the adjustment signal when the analogue input signal has the relatively low value and the upper boundary of the quantisation range is the average magnitude of the adjustment signal when the analogue input signal has the relatively high value.
5. A sigma-delta modulator as claimed in any preceding claim, wherein the digital output signal is formed by the quantiser as a signal alternating between two voltage levels.
6. A sigma-delta modulator as claimed in any preceding claim, wherein the control signal is generated by a control unit.
7. A sigma-delta modulator as claimed in any preceding claim, wherein the control unit generates the control signal so as to cause effective amplification of the input signal by the sigma-delta modulator.
8. A sigma-delta modulator as claimed in any preceding claim, wherein the control unit generates the control signal so as to cause effective offset of the input signal by the sigma-delta modulator.
9. A sigma-delta modulator as claimed in any preceding claim, wherein the control unit generates the control signal so as to control the degree to which the adjustment signal follows the digital output signal.
10. A sigma-delta modulator as claimed in any preceding claim, wherein the control unit generates the control signal such that selected portions of the digital output signal are replaced with transition-cycles.
11. A sigma-delta modulator as claimed in claim 10, wherein the control unit is operable to increase the gain of the modulator by replacing an increased proportion of the digital output signal with transition-cycles.
12. A sigma-delta modulator as claimed in claims 10 or 11, wherein the control unit is operable to either increase or decrease the average magnitude of the adjustment signal by replacing selected portions of the digital output signal with transition-cycles, thereby changing the upper and lower boundaries of the quantisation range.
13. A sigma-delta modulator as claimed in any preceding claim, wherein the control unit generates the control signal in dependence on the digital output signal.
14. A sigma-delta modulator as claimed in claim 13 as dependent on claim 10, wherein the control unit is operable to introduce an offset by generating the control signal so as to replace a greater or lesser proportion of the digital output signal having the relatively high value.
15. A sigma-delta modulator as claimed in any preceding claim, wherein the quantiser receives a first clock signal having a first frequency, such that transitions in the digital output signal can occur at intervals of a first time period.
16. A sigma-delta modulator as claimed in any preceding claim, wherein the logic circuit receives a second clock signal having a second frequency, such that transitions in the adjustment signal can occur at intervals of a second time period.
17. A sigma-delta modulator as claimed in any preceding claim, wherein the second frequency is greater than or equal to the first frequency.
18. A sigma-delta modulator as claimed in any preceding claim, wherein a transition-cycle takes the relatively high value for some of the duration of the transition-cycle and takes the relatively low value for the remainder of the transition-cycle.
19. A sigma-delta modulator as claimed in any preceding claim, wherein the net average value of a transition-cycle is equal to the virtual ground value for the modulator.
20. A sigma-delta modulator as claimed in claim 19, wherein the virtual ground value of the modulator is midway between the relatively high value and the relatively low value.
21. A sigma-delta modulator as claimed in any preceding claim, wherein the control signal is a non return-to-zero signal.
22. A sigma-delta modulator as claimed in any of claims 1 to 20, wherein the control signal is a return-to-zero signal.
23. A sigma-delta modulator as claimed in any preceding claim, wherein the logic circuit is an exclusive OR gate arranged to receive the digital output signal and the control signal.
24. A sigma-delta modulator as claimed in claim 6 or any of claims 7 to 23 as dependent on claim 6, wherein the control unit is implemented in software.
25. A sigma-delta modulator as claimed in claim 6 or any of claims 7 to 23 as dependent on claim 6, wherein the control unit is implemented in hardware.
26. A sigma-delta modulator as claimed in claim 25, wherein the control unit is implemented in analogue hardware.
27. A sigma-delta modulator as claimed in claim 25, wherein the control unit is implemented in digital hardware.
28. A digital media player comprising a detection device for detecting digital data and having a sigma-delta modulator for receiving an analogue input signal and forming a digital output signal representative of the magnitude of the analogue input signal, the modulator comprising: a summation unit for summing the analogue input signal with an adjustment signal to form a summation output signal; an integrator arranged to receive the summation output signal and form an integrator output signal dependent thereon; a quantiser arranged to receive the integrator output signal and form the digital output signal dependent thereon; and a feedback loop for generating the adjustment signal and comprising a logic circuit arranged to select between one of two predetermined values for the adjustment signal, the selection being performed in dependence on both the digital output signal and a control signal.
29. A digital media player as claimed in claim 28, comprising a control unit arranged to generate the control signal.
30. A digital media player as claimed in claim 29, wherein the control unit is arranged to select a predetermined control signal dependent on the type of digital data detected by the detection device.
31. A digital media player as claimed in claim 29 to 30, wherein the control unit is arranged to receive information from the detection device, said information being dependent on the digital data detected by the detection device, and for generating a control signal thereon.
32. A digital media player as claimed in any of claims 28 to 31, wherein the player is arranged for playing optical discs and the detection device is arranged to detect the content of an optical disc and generate the input signal in dependence thereon.
33. A method for forming a digital output signal representative of the magnitude of an analogue input signal by means of a sigma-delta modulator, the method comprising the steps of: for summing the analogue input signal with an adjustment signal by means of a summation unit to form a summation output signal; receiving the summation output signal in an integrator, which is arranged to form an integrator output signal dependent thereon; receiving the integrator output signal in a quantiser, which is arranged to form the digital output signal dependent thereon; and generating the adjustment signal by selecting between one of two predetermined values for the adjustment signal by means a feedback loop; the feedback loop comprising a logic circuit arranged to perform the selection in dependence on both the digital output signal and a control signal.